SLRC400 01T-SLRC40001T Fast Delivery |IC PHOENIX CO.,LIMITED

SLRC40001T ,Standard ISO/IEC 15693 reader solutionBlock diagram NWR NRD NCS ALE A0 A1 A2 AD0 to AD7/D0 to D710 11 9 21 22 23 24 13 14 15 16 17 18 19 ..
SLRC40001T ,Standard ISO/IEC 15693 reader solutionGeneral descriptionThe SLRC400 is a member of a new family of highly integrated reader ICs for cont ..
SLVU2.8 ,ESD Protection DevicesFeatures■ Peak pulse current : I = 30 A 8/20 µsPP■ Low capacitance : C = 1.5 pFtyp■ Stand-off volt ..
SLVU2.8 ,ESD Protection DevicesFeatures■ Peak pulse current : I = 30 A 8/20 µsPP■ Low capacitance : C = 1.5 pFtyp■ Stand-off volt ..
SLVU2.8 ,ESD Protection DevicesSLVU2.8Low voltage unit for Gigabit Ethernet protection
SLVU2.8 ,ESD Protection DevicesFeatures■ Peak pulse current : I = 30 A 8/20 µsPP■ Low capacitance : C = 1.5 pFtyp■ Stand-off volt ..
SMJ27C256-17JM , 256K UVEPROM
SMJ27C256-17JM , 256K UVEPROM
SMJ27C256-20JM , 256K UVEPROM
SMJ27C256-20JM , 256K UVEPROM
SMJ27C256-20JM , 256K UVEPROM
SMJ27C256-25JM , 256K UVEPROM

SLRC400 01T-SLRC40001T
Standard ISO/IEC 15693 reader solution
1. Introduction
This data sheet describes the functionality of the SLRC400 Integrated Circuit (IC). It
includes the functional and electrical specifications and from a system and hardware
viewpoint gives detailed information on how to design-in the device.
2. General description
The SLRC400 is a member of a new family of highly integrated reader ICs for contactless
communication at 13.56 MHz. This family of reader ICs provide: outstanding modulation and demodulation for passive contactless communication a wide range of methods and protocols
The transmitter module Section 8.9 on page 24 can directly drive an antenna designed for
proximity operating distance up to 100 mm without additional active circuitry. The receiver
module provides a robust and efficient demodulation/decoding circuitry implementation for
compatible transponder signals (see Section 8.10 on page 28).
All layers of the ICODE1 and ISO/IEC 15693 protocols are supported. The receiver
module provides a robust and efficient demodulation/decoding circuitry implementation for
ICODE1 and ISO/IEC 15693 compatible transponder signals. The digital module
manages ICODE1 and ISO/IEC 15693 framing and error detection (CRC).
A parallel interface can be directly connected to any 8-bit microprocessor to ensure
reader/terminal design flexibility.
3. Features and benefits
3.1 General Highly integrated analog circuitry for demodulating and decoding label response Buffered output drivers enable antenna connection using the minimum of external
components Proximity operating distance up to 100 mm Supports both ICODE1 and ISO/IEC 15693 protocols Parallel microprocessor interface with internal address latch and IRQ line Flexible interrupt handling Automatic detection of parallel microprocessor interface type 64-byte send and receive FIFO buffer Hard reset with low power function
SLRC400
ICODE reader IC
Rev. 3.3 — 23 March 2010
Product data sheet
PUBLIC
NXP Semiconductors SLRC400
ICODE reader IC Software controlled Power-down mode Programmable timer Unique serial number User programmable start-up configuration Bit-oriented and byte oriented framing Independent power supply pins for analog, digital and transmitter modules Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz
connection Clock frequency filtering 3.3 V operation for transmitter (antenna driver) in short range and proximity
applications
4. Applications Electronic payment systems Identification systems Access control systems Subscriber services Banking systems Digital content systems
5. Ordering informationTable 1. Ordering information
SLRC40001T/0FE SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1
NXP Semiconductors SLRC400
ICODE reader IC
6. Block diagram
NXP Semiconductors SLRC400
ICODE reader IC
7. Pinning information
7.1 Pin description
Table 2. Pin description OSCIN I oscillator or clock input:
crystal oscillator input to the oscillator’s inverting amplifier
externally generated clock input; fosc = 13.56 MHz IRQ O interrupt request output signals an interrupt event n.c. I connect this pin to ground SIGOUT O ICODE interface serial data output based on ICODE1 and ISO/IEC 15693 TX1 O transmitter 1 modulated carrier output; 13.56 MHz TVDD P power supply for transmitter output stage pins TX1 and TX2 TX2 O transmitter 2 modulated carrier output; 13.56 MHz TVSS G transmitter ground for the TX1 and TX2 output stages NCS I not chip select input selects and activates the SLRC400’s microprocessor
interface[2] NWR I not write input strobe signal for writing data to the SLRC400 registers when
applied to pins D0 to D7
R/NW I read not write input indicates that a read or a write cycle must be performed
nWrite I not write input indicates that a read or a write cycle must be performed[2] NRD I not read input strobe signal for reading data from the SLRC400 registers when
applied to pins D0 to D7
NDS I not data strobe input strobe signal for read and write cycles
nDStrb I not data strobe input strobe signal for read and write cycles
NXP Semiconductors SLRC400
ICODE reader IC
[1] Pin types: I= Input, O= Output, I/O= Input/Output, P= Power and G= Ground.
[2] These pins provide different functionality depending on the selected microprocessor interface type (see Section 8.1 on page 6 for
detailed information). DVSS G digital ground
13 to 20[2] D0 to D7 I/O 8-bit bidirectional data bus input/output on pins D0 to D7
AD0 to AD7 I/O 8-bit bidirectional address and data bus input/output on pins AD0 to AD7[2] ALE I address latch enable input for pins AD0 to AD5; HIGH latches the internal address I address strobe input for pins AD0 to AD5; HIGH latches the internal address
nAStrb I not address strobe input for pins AD0 to AD5; LOW latches the internal address[2] A0 I address line 0 is the address register bit 0 input
nWait O not wait output:
LOW starts an access cycle
HIGH ends an access cycle A1 I address line 1 is the address register bit 1 input A2 I address line 2 is the address register bit 2 input DVDD P digital power supply AVDD P analog power supply for pins OSCIN, AUX, RX, VMID and OSCOUT AUX O auxiliary analog test signal output. The output signal is selected using the
TestAnaSelect register’s TestAnaOutSel[4:0] bits AVSS G analog ground RX I receiver input for the label response. The carrier is load modulated at 13.56 MHz,
taken from the antenna circuit VMID P internal reference voltage: provides the internal reference voltage as a supply
Remark: It must be connected to ground using a 100 nF block capacitor. RSTPD I reset and power-down input:
HIGH: switches off the internal current sinks, inhibits the oscillator and
disconnects the input pads
LOW (negative edge): starts the internal reset phase OSCOUT O crystal oscillator output for the oscillator’s inverting amplifier
Table 2. Pin description …continued
NXP Semiconductors SLRC400
ICODE reader IC
8. Functional description
8.1 Digital interface
8.1.1 Overview of supported microprocessor interfaces
The SLRC400 supports direct interfacing to various 8-bit microprocessors. Alternatively,
the SLRC400 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 3 shows
the parallel interface signals supported by the SLRC400.
8.1.2 Automatic microprocessor interface detection
After a Power-On or Hard reset, the SLRC400 resets parallel microprocessor interface
mode and detects the microprocessor interface type.
The SLRC400 identifies the microprocessor interface using the logic levels on the control
pins after the reset phase. This is performed using a combination of fixed pin connections
and the dedicated Initialization routine (see Section 8.7.4 on page 23).
Table 3. Supported microprocessor and EPP interface signals
Separated read and
write strobes
control NRD, NWR, NCS NRD, NWR, NCS, ALE
address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5
data D0 to D7 AD0 to AD7
Common read and write
strobe
control R/NW, NDS, NCS R/NW, NDS, NCS, AS
address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5
data D0 to D7 AD0 to AD7
Common read and write
strobe with handshake
(EPP)
control - nWrite, nDStrb, nAStrb, nWait
address - AD0, AD1, AD2, AD3, AD4, AD5
data - AD0 to AD7
NXP Semiconductors SLRC400
ICODE reader IC
8.1.3 Connection to different microprocessor types
The connection to various microprocessor types is shown in Table4.
8.1.3.1 Separate read and write strobe
Refer to Section 12.4.1 on page 80 for timing specification.
Table 4. Connection scheme for detecting the parallel interface type
ALE HIGH ALE HIGH AS nAStrb A2 LOW A2 LOW HIGH A1 HIGH A1 HIGH HIGH A0 HIGH A0 LOW nWait
NRD NRD NRD NDS NDS nDStrb
NWR NWR NWR R/NW R/NW nWrite
NCS NCS NCS NCS NCS LOW
D7 to D0 D7 to D0 AD7 to AD0 D7 to D0 AD7 to AD0 AD7 to AD0
NXP Semiconductors SLRC400
ICODE reader IC
8.1.3.2 Common read and write strobe
Refer to Section 12.4.2 on page 81 for timing specification.
8.1.3.3 Common read and write strobe: EPP with handshake
Refer to Section 12.4.3 on page 82 for timing specification.
Remark: In the EPP standard a chip select signal is not defined. To cover this situation,
the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not
used, it is mandatory that pin NCS is connected to pin DVSS.
Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is
high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after
the reset phase. The SLRC400 does not support Read Address Cycle.
NXP Semiconductors SLRC400
ICODE reader IC
8.2 Memory organization of the EEPROM
Remark: It is recommend to use only the above EEPROM address area.
8.2.1 Product information field (read only)
Table 5. EEPROM memory organization diagram 0 00h to 0Fh R product
information field
Section 8.2.1 on page9 1 10h to 1Fh R/W StartUp register
initialization file
Section 8.2.2.1 on page10 2 20h to 2Fh R/W 3 30h to 3Fh R/W register
initialization file
user data or
second
initialization
Section 8.2.2.3 “Register
initialization file (read/write)”
on page 124 4 40h to 4Fh R/W 5 50h to 5Fh R/W 6 60h to 6Fh R/W 7 70h to 7Fh R/W
Table 6. Product information field byte allocation
Table 7. Product information field CRC R - the content of the product information field is secured using a
CRC byte which is checked during start-up RsMaxP R - maximum source resistance for the p-channel driver transistor
on pins TX1 and TX2
The source resistance of the p-channel driver transistors of pin
TX1 and TX2 can be adjusted using the value GsCfgCW[5:0] in
the CwConductance register (see Section 8.9.3 on page 25). The mean value of the maximum adjustable source resistance
for pins TX1 and TX2 is stored as an integer value in Ω in this byte. Typical values for RsMaxP are between 60 Ω to 140 Ω.
This value is denoted as maximum adjustable source resistance
RS(ref)maxP and is measured by setting the CwConductance register’s GsCfgCW[5:0] bits to 01h.
13 to 12 Internal R - two bytes for internal trimming parameters
11 to 8 Product Serial Number R - a unique four byte serial number for the device
7 to 5 reserved R - -
4 to 0 Product Type Identification R - the SLRC400 is a member of a new family of highly integrated reader ICs. Each member of the product family has a unique
product type identification. The value of the product type
identification is shown in Table8.
NXP Semiconductors SLRC400
ICODE reader IC
[1] Byte 4 contains the current version number.
8.2.2 Register initialization file (read/write)
Register initialization from address 10h to address 2Fh is performed automatically during
the initializing phase (see Section 8.7.3 on page 23) using the StartUp register
initialization file.
In addition, the SLRC400 registers can be initialized using values from the StartUp
register initialization file when the LoadConfig command is executed (see Section 10.4.1
on page 75).
Remark: The following points apply to initialization: the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. make sure that all PreSetxx registers are not changed. make sure that all register bits that are reserved are set to logic 0.
8.2.2.1 StartUp register initialization file (read/write)
The EEPROM memory block address 1 and 2 contents are used to automatically set the
register subaddresses 10h to 2Fh during the initialization phase. The default values stored
in the EEPROM during production are shown in Section 8.2.2.2 “Factory default StartUp
register initialization file”.
The byte assignment is shown in Table9.
8.2.2.2 Factory default StartUp register initialization file
During the production tests, the StartUp register initialization file is initialized using the
default values shown in Table 10. During each power-up and initialization phase, these
values are written to the SLRC400’s registers.
Table 8. Product type identification definition
Table 9. Byte assignment for register initialization at start-up
10h (block 1, byte 0) 10h skipped
11h 11h copied …
2Fh (block 2, byte 15) 2Fh copied
NXP Semiconductors SLRC400
ICODE reader ICTable 10. Shipment content of StartUp register initialization file
10h 10h 00h Page free for user
11h 11h 58h TxControl transmitter pins TX1 and TX2 are switched off, bridge driver
configuration, modulator driven from internal digital circuitry
12h 12h 3Fh CwConductance source resistance of TX1 and TX2 is set to minimum
13h 13h 05h ModGsCfg source resistance of TX1 and TX2 at modulation to determine the
modulation index
14h 14h 2Ch CoderControl selects the bit coding mode and framing during transmission
15h 15h 3Fh ModWidth pulse width for used code (1 out of 256 RZ or 1 out of 4); pulse
coding is set to standard configuration
16h 16h 3Fh ModWidthSOF pulse width of Start Of Frame (SOF)
17h 17h 00h PreSet17 -
18h 18h 00h Page free for user
19h 19h 8Bh RxControl1 internal amplifier gain is maximum
1Ah 1Ah 00h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream
1Bh 1Bh 54h BitPhase BitPhase[7:0] is set to standard configuration
1Ch 1Ch 68h RxThreshold MinLevel[3:0] and CollLevel[3:0] are set to maximum
1Dh 1Dh 00h PreSet1D -
1Eh 1Eh 41h RxControl2 use Q-clock for the receiver, automatic receiver off is switched on,
decoder is driven from internal analog circuitry
1Fh 1Fh 00h ClockQControl automatic Q-clock calibration is switched on
20h 20h 00h Page free for user
21h 21h 08h RxWait frame guard time is set to eight bit-clocks
22h 22h 0Ch ChannelRedundancy channel redundancy is set in accordance with ICODE1
23h 23h FEh CRCPresetLSB CRC preset value is set in accordance with ICODE1
24h 24h FFh CRCPresetMSB CRC preset value is set in accordance with ICODE1
25h 25h 00h PreSet25 -
26h 26h 00h SIGOUTSelect pin SIGOUT is set LOW
27h 27h 00h PreSet27 -
28h 28h 00h Page free for user
29h 29h 3Eh FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard
configuration
2Ah 2Ah 0Bh TimerClock TPreScaler[4:0] is set to standard configuration, timer unit restart
function is switched off
2Bh 2Bh 02h TimerControl Timer is started at the end of transmission, stopped at the beginning
of reception
2Ch 2Ch 00h TimerReload TReloadValue[7:0]: the timer unit preset value is set to standard
configuration
2Dh 2Dh 02h IRQPinConfig pin IRQ is set to high-impedance
2Eh 2Eh 00h PreSet2E -
2Fh 2Fh 00h PreSet2F -
NXP Semiconductors SLRC400
ICODE reader IC
8.2.2.3 Register initialization file (read/write)
The EEPROM memory content from block address 3 to 7 can initialize register sub
addresses 10h to 2Fh when the LoadConfig command is executed (see Section 10.4.1 on
page 75). This command requires the EEPROM starting byte address as a two byte
argument for the initialization procedure.
The byte assignment is shown in Table 11.
The register initialization file is large enough to hold values for two initialization sets and
up to one block (16-byte) of user data.
Remark: The register initialization file can be read/written by users and these bytes can
be used to store other user data.
8.3 FIFO buffer
An 8× 64 bit FIFO buffer is used in the SLRC400 to act as a parallel-to-parallel converter.
It buffers both the input and output data streams between the microprocessor and the
internal circuitry of the SLRC400. This makes it possible to manage data streams up to 64
bytes long without needing to take timing constraints into account.
8.3.1 Accessing the FIFO buffer
8.3.1.1 Access rules
The FIFO buffer input and output data bus is connected to the FIFOData register. Writing
to this register stores one byte in the FIFO buffer and increments the FIFO buffer write
pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO
buffer read pointer and increments the FIFO buffer read pointer. The distance between the
write and read pointer can be obtained by reading the FIFOLength register.
When the microprocessor starts a command, the SLRC400 can still access the FIFO
buffer while the command is running. Only one FIFO buffer has been implemented which
is used for input and output. Therefore, the microprocessor must ensure that there are no
inadvertent FIFO buffer accesses. Table 12 gives an overview of FIFO buffer access
during command processing.
Table 11. Byte assignment for register initialization at StartUp
EEPROM starting byte address 10h skipped
EEPROM + 1 starting byte address 11h copied
EEPROM + 31 starting byte address 2Fh copied
Table 12. FIFO buffer access
StartUp - -
Idle - -
Transmit yes -
Receive - yes
NXP Semiconductors SLRC400
ICODE reader IC
8.3.2 Controlling the FIFO buffer
In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
8.3.3 FIFO buffer status information
The microprocessor can get the following FIFO buffer status data: the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0] the FIFO buffer full warning: bit HiAlert the FIFO buffer empty warning: bit LoAlert the FIFO buffer overflow warning: bit FIFOOvfl.
Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.
The SLRC400 can generate an interrupt signal when: bit LoAlertIRq is set to logic 1 and bit LoAlert= logic 1, pin IRQ is activated. bit HiAlertIRq is set to logic 1 and bit HiAlert= logic 1, pin IRQ activated.
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by Equation1:
(1)
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by Equation2:
(2)
8.3.4 FIFO buffer registers and flags
Table 13 shows the related FIFO buffer flags in alphabetical order.
Transceive yes yes the microprocessor has to know the state of the
command (transmitting or receiving)
WriteE2 yes -
ReadE2 yes yes the microprocessor has to prepare the arguments,
afterwards only reading is allowed
LoadConfig yes -
CalcCRC yes -
Table 12. FIFO buffer access …continued
HiAlert 64 FIFOLength– () WaterLevel≤=
LoAlert FIFOLength WaterLevel≤=
NXP Semiconductors SLRC400
ICODE reader IC
8.4 Interrupt request system
The SLRC400 indicates interrupt events by setting the PrimaryStatus register bit IRq (see
Section 9.5.1.4 “PrimaryStatus register” on page 41) and activating pin IRQ. The signal on
pin IRQ can be used to interrupt the microprocessor using its interrupt handling
capabilities ensuring efficient microprocessor software.
8.4.1 Interrupt sources overview
Table 14 shows the integrated interrupt flags, related source and setting condition. The
interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows: the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady= logic 1 when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit
E2Ready= logic 1
The RxIRq flag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq flag bit is set when a command finishes and the content of the Command
register changes to Idle.
When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 8.3.3 on page 13) and bit HiAlert= logic 1, then the HiAlertIRq flag bit is set to
logic1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 8.3.3 on page 13) and bit LoAlert= logic 1, then LoAlertIRq flag bit is set to
logic1.
Table 13. Associated FIFO buffer registers and flags
FIFOLength[6:0] FIFOLength 6 to 0 04h
FIFOOvfl ErrorFlag 4 0Ah
FlushFIFO Control 0 09h
HiAlert PrimaryStatus 1 03h
HiAlertIEn InterruptEn 1 06h
HiAlertIRq InterruptRq 1 07h
LoAlert PrimaryStatus 0 03h
LoAlertIEn InterruptEn 0 06h
LoAlertIRq InterruptRq 0 07h
WaterLevel[5:0] FIFOLevel 5 to 0 29h
NXP Semiconductors SLRC400
ICODE reader IC
8.4.2 Interrupt request handling
8.4.2.1 Controlling interrupts and getting their status
The SLRC400 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
If any interrupt request flag is set to logic 1 (showing that an interrupt request is pending)
and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is
set to logic 1. Different interrupt sources can activate simultaneously because all interrupt
request bits are ORed, coupled to the IRq flag and then forwarded to pin IRQ.
8.4.2.2 Accessing the interrupt registers
The interrupt request bits are automatically set by the SLRC400’s internal state machines.
In addition, the microprocessor can also set or clear the interrupt request bits as required.
A special implementation of the InterruptRq and InterruptEn registers enables changing
an individual bit status without influencing any other bits. If an interrupt register is set to
logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. Vice
versa, if a specific interrupt flag is cleared, zero must be written to the SetIxx and the
interrupt register address must be set to logic 1 at the same time.
If a content bit is not changed during the setting or clearing phase, zero must be written to
the specific bit location.
Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0
while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq
to logic 1 and leaves all other bits unchanged.
8.4.3 Configuration of pin IRQ
The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be
controlled using the following IRQPinConfig register bits. bit IRQInv: the signal on pin IRQ is equal to the logic level of bit IRq when this bit is set
to logic 0. When set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq.
Table 14. Interrupt sources
TimerIRq timer unit timer counts from 1 to 0
TxIRq transmitter a data stream, transmitted to the label, ends
CRC coprocessor all data from the FIFO buffer has been processed
RxIRq receiver a data stream, received from the label, ends
IdleIRq Command register command execution finishes
HiAlertIRq FIFO buffer FIFO buffer is full
LoAlertIRq FIFO buffer FIFO buffer is empty
Table 15. Interrupt control registers
NXP Semiconductors SLRC400
ICODE reader IC bit IRQPushPull: when set to logic 1, pin IRQ has CMOS output characteristics. When
it is set to logic 0, it is an open-drain output which requires an external resistor to
achieve a HIGH-level at pin IRQ.
Remark: During the reset phase (see Section 8.7.2 on page 23) bit IRQInv is set to
logic 1 and bit IRQPushPull is set to logic 0. This results in a high-impedance on pin IRQ.
8.4.4 Register overview interrupt request system
Table 16 shows the related interrupt request system flags in alphabetical order.
8.5 Timer unit
The timer derives its clock from the 13.56 MHz on-board chip clock. The microprocessor
can use this timer to manage timing-relevant tasks.
The timer unit may be used in one of the following configurations: Timeout counter WatchDog counter Stopwatch Programmable one shot Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific timed event occurred. The timer is triggered by events but does not
influence any event (e.g. a time-out during data receiving does not automatically influence
the receiving process). Several timer related flags can be set and these flags can be used
to generate an interrupt.
Table 16. Associated Interrupt request system registers and flags
HiAlertIEn InterruptEn 1 06h
HiAlertIRq InterruptRq 1 07h
IdleIEn InterruptEn 2 06h
IdleIRq InterruptRq 2 07h
IRq PrimaryStatus 3 03h
IRQInv IRQPinConfig 1 07h
IRQPushPull IRQPinConfig 0 07h
LoAlertIEn InterruptEn 0 06h
LoAlertIRq InterruptRq 0 07h
RxIEn InterruptEn 3 06h
RxIRq InterruptRq 3 07h
SetIEn InterruptEn 7 06h
SetIRq InterruptRq 7 07h
TimerIEn InterruptEn 5 06h
TimerIRq InterruptRq 5 07h
TxIEn InterruptEn 4 06h
TxIRq InterruptRq 4 07h
NXP Semiconductors SLRC400
ICODE reader IC
8.5.1 Timer unit implementation
8.5.1.1 Timer unit block diagram
Figure 6 shows the block diagram of the timer module.
The timer unit is designed, so that events when combined with enabling flags start or stop
the counter. For example, setting bit TStartTxBegin= logic 1 enables control of received
data with the timer unit. In addition, the first received bit is indicated by the TxBegin event.
This combination starts the counter at the defined TReloadValue[7:0].
The timer stops automatically when the counter value is equal to zero or if a defined stop
event happens (TautoRestart not enabled).
8.5.1.2 Controlling the timer unit
The main part of the timer unit is a down-counter. As long as the down-counter value is
not zero, it decrements its value with each timer clock cycle.
If the TAutoRestart flag is enabled, the timer does not decrement down to zero. On
reaching value 1, the timer reloads the next clock function with the TReloadValue[7:0].
NXP Semiconductors SLRC400
ICODE reader IC
The timer is started immediately by loading a value from the TimerReload register into the
counter module.
This is activated by one of the following events: transmission of the first bit to the label (TxBegin event) with bit TStartTxBegin=
logic1 transmission of the last bit to the label (TxEnd event) with bit TStartTxEnd= logic1 bit TStartNow is set to logic 1 by the microprocessor
Remark: Every start event reloads the timer from the TimerReload register. Thus, the
timer unit is re-triggered.
The timer can be configured to stop on one of the following events: receipt of the first valid bit from the label (RxBegin event) with bit
TStopRxBegin= logic1 receipt of the last bit from the label (RxEnd event) with bit TStopRxEnd= logic1 the counter module has decremented down to zero and bit TAutoRestart= logic0 bit TStopNow is set to logic 1 by the microprocessor.
Loading a new value, e.g. zero, into the TimerReload register or changing the timer unit
while it is counting will not immediately influence the counter. In both cases, this is
because this register only affects the counter content after a start event. Thus, the
TimerReload register may be changed even if the timer unit is already counting. The
consequence of changing the TimerReload register will be visible after the next start
event.
If the counter is stopped when bit TStopNow is set, no TimerIRq is flagged.
8.5.1.3 Timer unit clock and period
The timer unit clock is derived from the 13.56 MHz on-board chip clock using the
programmable divider. Clock selection is made using the TimerClock register
TPreScaler[4:0] bits based on Equation3:
(3)
The values for the TPreScaler[4:0] bits are between 0 and 21 which results in a minimum
periodic time (TTimerClock) of between 74 ns and 150 ms.
The time period elapsed since the last start event is calculated using Equation4:
(4)
This results in a minimum time period (tTimer) of between 74 ns and 40 s. TimerClock 1 TimerClock------- -------------------- 2 TPreScaler
13.56------------ -------------- MHz][== Timer TReLoadValue TimerValue– TimerClock-------------------------------------------------------------- ---------------s[]=
NXP Semiconductors SLRC400
ICODE reader IC
8.5.1.4 Timer unit status
The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start
events start the timer at the TReloadValue[7:0] and changes the status flag TRunning to
logic 1. Conversely, configured stop events stop the timer and sets the TRunning status
flag to logic 0. As long as status flag TRunning is set to logic 1, the TimerValue register
changes on the next timer unit clock cycle.
The TimerValue[7:0] bits can be read directly from the TimerValue register.
8.5.1.5 Time-slot period
When sending ICODE1 Quit frames, it is necessary to generate the exact chronological
relationship to the start of the command frame.
If at the end of command execution TimeSlotPeriod > 0, the TimeSlotPeriod starts. If the
FIFO buffer contains data when the end of TimeSlotPeriod is reached, the data is sent. If
the FIFO buffer is empty nothing happens. As long as the TimeSlotPeriod is > 0, the
TimeSlotPeriod counter automatically starts on reaching the end.
This forms the exact time relationship between the start and finish of the command frame
used to generate and send ICODE1 Quit frames.
When the TimeSlotPeriod > 0, the next Frame starts with exactly the same interval
TimeSlotPeriod/CoderRate delayed after each previous send frame. CoderRate defines
the clock frequency of the encoder. If TimeSlotPeriod[7:0] = 0, the send function is not
automatically triggered.
The content of the TimeSlotPeriod register can be changed while it is running but the
change is only effective after the next TimeSlotPeriod restart.
Example: CoderRate = 0× 0.5 (~52.97 kHz) The interval should be 8.458 ms for ICODE1 standard mode
TimeSlotPeriod = CoderRate × Interval = 52.97 kHz × 8.458 ms −1 = 447 = 1BFh
Remark: The TimeSlotPeriod MSB bit is contained in the SIGOUTSelect register.
NXP Semiconductors SLRC400
ICODE reader IC
Remark: Set bit TxCRCEn to logic 0 before the Quit frame is sent. If TxCRCEn is not set
to logic 0, the Quit frame is sent with a calculated CRC value. Use the CRC8 algorithm to
calculate the Quit value.
8.5.2 Using the timer unit functions
8.5.2.1 Time-out and WatchDog counters
After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue
register beginning with a given start event. If a given stop event occurs, such as a bit
being received from the label, the timer unit stops without generating an interrupt.
If a stop event does not occur, such as the label not answering within the expected time,
the timer unit decrements down to zero and generates a timer interrupt request. This
signals to the microprocessor the expected event has not occurred within the given time
(tTimer).
8.5.2.2 Stopwatch
The time (tTimer) between a start and stop event is measured by the microprocessor using
the timer unit. Setting the TimerReload register triggers the timer which in turn, starts to
decrement. If the defined stop event occurs, the timer stops. The time between start and
stop is calculated by the microprocessor using Equation 5, when the timer does not
decrement down to zero.
(5)
8.5.2.3 Programmable one shot timer and periodic trigger
Programmable one shot timer: The microprocessor starts the timer unit and waits for
the timer interrupt. The interrupt occurs after the time specified by tTimer (TAutoRestart bit
= logic 0).
Periodic trigger: If the microprocessor sets the TAutoRestart bit, and TReloadValue is
not equal to zero, it generates an interrupt request after every tTimer cycle.
8.5.3 Timer unit registers
Table 18 shows the related flags of the timer unit in alphabetical order.
Table 17. TimeSlotPeriod
standard mode BFh 1BFh
fast mode 5Fh 67h TReLoad value TimerValue– ()t Timer×=
Table 18. Associated timer unit registers and flags
TAutoRestart TimerClock 5 2Ah
TimerValue[7:0] TimerValue 7 to 0 0Ch
TReloadValue[7:0] TimerReload 7 to 0 2Ch
TPreScaler[4:0] TimerClock 4 to 0 2Ah
TRunning SecondaryStatus 7 05h
TStartNow Control 1 09h
NXP Semiconductors SLRC400
ICODE reader IC
8.6 Power reduction modes
8.6.1 Hard power-down
Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pads and
defined internally (except pin RSTPD itself). The output pins are frozen at a given value.
The status of all pins during a hard power-down is shown in Table 19.
8.6.2 Soft power-down mode
Soft power-down mode is entered immediately using the Control register bit PowerDown.
All internal current sinks, including the oscillator buffer, are switched off. The digital input
buffers are not separated from the input pads and keep their functionality. In addition, the
digital output pins do not change their state.
TStartTxBegin TimerControl 0 2Bh
TStartTxEnd TimerControl 1 2Bh
TStopNow Control 2 09h
TStopRxBegin TimerControl 2 2Bh
TStopRxEnd TimerControl 3 2Bh
Table 18. Associated timer unit registers and flags …continued
Table 19. Signal on pins during Hard power-down
OSCIN 1 I not separated from input, pulled to AVSS
IRQ 2 O high-impedance
n.c. 3 I separated from input
SIGOUT 4 O LOW
TX1 5 O HIGH
TX2 7 O LOW
NCS 9 I separated from input
NWR 10 I separated from input
NRD 11 I separated from input
D0 to D7 13 to 20 I/O separated from input
ALE 21 I separated from input 22 I/O separated from input 23 I separated from input 24 I separated from input
AUX 27 O high-impedance 29 I not changed
VMID 30 A pulled to VDDA
RSTPD 31 I not changed
OSCOUT 32 O HIGH
NXP Semiconductors SLRC400
ICODE reader IC
After resetting the Control register bit PowerDown, the bit indicating Soft power-down
mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The
PowerDown bit is automatically cleared when the Soft power-down mode is exited.
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
8.6.3 Standby mode
The Standby mode is immediately entered when the Control register StandBy bit is set. All
internal current sinks, including the internal digital clock buffer are switched off. However,
the oscillator buffer is not switched off.
The digital input buffers are not separated by the input pads, keeping their functionality
and the digital output pins do not change their state. In addition, the oscillator does not
need time to wake-up.
After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for
Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is
automatically cleared when the Standby mode is exited.
8.6.4 Automatic receiver power-down
It is a power saving feature to switch off the receiver circuit when it is not needed. Setting
bit RxAutoPD= logic 1, automatically powers down the receiver when it is not in use.
Setting bit RxAutoPD= logic 0, keeps the receiver continuously powered up.
8.7 StartUp phase
The events executed during the StartUp phase are shown in Figure8.
8.7.1 Hard power-down phase
The hard power-down phase is active during the following cases: a Power-On Reset (POR) caused by power-up on pins DVDD activated when VDDD is
below the digital reset threshold. a Power-On Reset (POR) caused by power-up on pins AVDD activated when VDDA is
below the analog reset threshold. a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100 μs (tPD ≥ 100 μs). Shorter phases will not
necessarily result in the reset phase (treset). The rising or falling edge slew rate on pin
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
NXP Semiconductors SLRC400
ICODE reader IC
8.7.2 Reset phase
The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see Section 9.5 on page 40).
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
8.7.3 Initialization phase
The initialization phase automatically follows the reset phase and takes 128 clock cycles.
During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the
register subaddresses 10h to 2Fh (see Section 8.2.2 on page 10).
Remark: During the production test, the SLRC400 is initialized with default configuration
values. This reduces the microprocessor’s configuration time to a minimum.
8.7.4 Initializing the parallel interface type
A different initialization sequence is used for each microprocessor. This enables detection
of the correct microprocessor interface type and synchronization of the microprocessor’s
and the SLRC400’s start-up. See Section 8.1.3 on page 7 for detailed information on the
different connections for each microprocessor interface type.
During StartUp phase, the command value is set to 3Fh once the oscillator attains clock
frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At
the end of the initialization phase, the SLRC400 automatically switches to idle and the
command value changes to 00h.
To ensure correct detection of the microprocessor interface, the following sequence is
executed: the Command register is read until the 6-bit register value is 00h. On reading the 00h
value, the internal initialization phase is complete and the SLRC400 is ready to be
controlled write 80h to the Page register to initialize the microprocessor interface read the Command register. If it returns a value of 00h, the microprocessor interface
was successfully initialized write 00h to the Page registers to activate linear addressing mode.
NXP Semiconductors SLRC400
ICODE reader IC
8.8 Oscillator circuit
The clock applied to the SLRC400 acts as a time basis for the synchronous system
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain highest performance, clock jitter must be as small as possible. This is
best achieved by using the internal oscillator buffer with the recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock
quality has been verified. It must meet the specifications described in Section 12.4.4 on
page 84.
Remark: We do not recommend using an external clock source.
8.9 Transmitter pins TX1 and TX2
The signal on pins TX1 and TX2 is the 13.56 MHz carrier modulated by an envelope
signal. It can be used to drive an antenna directly, using minimal passive components for
matching and filtering (see Section 14.1 on page 85). To enable this, the output circuitry is
designed with a very low-impedance source resistance. The TxControl register is used to
control the TX1 and TX2 signals.
8.9.1 Configuring pins TX1 and TX2
TX1 pin configurations are described in Table 20.
TX2 pin configurations are described in Table 21.
Table 20. Pin TX1 configurations X LOW (GND) 0 13.56 MHz modulated carrier 1 13.56 MHz unmodulated carrier
NXP Semiconductors SLRC400
ICODE reader IC
8.9.2 Antenna operating distance versus power consumption
Using different antenna matching circuits (by varying the supply voltage on the antenna
driver supply pin TVDD), it is possible to find the trade-off between maximum effective
operating distance and power consumption. Different antenna matching circuits are
described in the Application note Ref.1.
8.9.3 Antenna driver output source resistance
The output source conductance of pins TX1 and TX2 for driving a HIGH level can be
adjusted between 1 Ω and 100 Ω using the CwConductance register GsCfgCW[5:0] bits.
The values are relative to the reference source resistance (RS(ref)) which is measured
during the production test and stored in the SLRC400 EEPROM. It can be read from the
product information field (see Section 8.2.1 on page 9). The electrical specification can be
found in Section 12.3.3 on page 79.
Table 21. Pin TX2 configurations X X X LOW (GND) 0 0 0 13.56 MHz modulated carrier 0 0 1 13.56 MHz unmodulated carrier 0 1 0 13.56 MHz modulated carrier frequency,
180° phase-shift relative to TX1 0 1 1 13.56 MHz unmodulated carrier, 180°
phase-shift relative to TX1 1 0 X 13.56 MHz unmodulated carrier 1 1 X 13.56 MHz unmodulated carrier, 180°
phase-shift relative to TX1
NXP Semiconductors SLRC400
ICODE reader IC
8.9.3.1 Source resistance table
8.9.3.2 Changing the modulation index
Table Table 23 shows the modulation index values when using an antenna with a
resistance (Rant) of 50 Ω with ModConductance register’s GsCfgMod[5:0] values between
00h and 3Fh. Note that if the modulation index value is changed the GsCfgMod[5:0] value
must also be changed.
Table 22. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW
MANT = Mantissa; EXP = Exponent.
NXP Semiconductors SLRC400
ICODE reader IC
Table 23. Modulation index values ∝ - 18 0.065 4.15 ∝ - 19 0.058 3.63 ∝ - 25 0.054 3.35 ∝ - 1A 0.052 3.22 1 43.45 1B 0.047 2.87 0.522 28.44 33 0.047 2.82 0.5 27.57 26 0.045 2.69 0.333 20.08 1C 0.043 2.58 0.27 16.83 1D 0.040 2.33 0.261 16.33 27 0.039 2.22 0.25 15.73 1E 0.037 2.12 0.2 12.88 34 0.035 1.95 0.174 11.32 1F 0.035 1.93 0.167 10.88 28 0.034 1.86 0.143 9.38 29 0.030 1.58 0.14 9.21 35 0.028 1.43 0.135 8.89 2A 0.027 1.35 0.13 8.59 2B 0.025 1.17 0.125 8.23 36 0.023 1.08 0.111 7.32 2C 0.023 1.01 0.104 6.86 2D 0.021 0.88 0.1 6.57 37 0.02 0.82 0.091 5.95 2E 0.019 0.77 0.090 5.89 2F 0.018 0.67 0.087 5.68 38 0.018 0.63 0.083 5.43 39 0.016 0.48 0.077 4.98 3A 0.014 0.36 0.075 4.81 3B 0.013 0.26 0.071 4.59 3C 0.012 0.18 0.070 4.5 3D 0.011 0.11 0.068 4.32 3E 0.01 0.05 0.067 4.26 3F 0.009 0
NXP Semiconductors SLRC400
ICODE reader IC
8.9.3.3 Calculating the relative source resistance
The reference source resistance RS(ref) can be calculated using Equation6.
(6)
8.9.3.4 Calculating the effective source resistance
Wiring resistance (RS(wire)): Wiring and bonding add a constant offset to the driver
resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The
additional resistance for pin TX1 (RS(wire)TX1) can be set approximately as shown in
Equation7.
(7)
Effective resistance (RSx): The source resistances of the driver transistors (RsMaxP
byte) read from the Product Information Field (see Section 8.2.1 on page 9) are measured
during the production test with CwConductance register’s GsCfgCW[5:0]= 01h.
To calculate the driver resistance for a specific value set in ModConductance register ‘s
GsCfgMod[5:0], use Equation8.
(8)
8.9.4 Pulse width
The envelope carries the data signal information that is transmitted to the label. The data
signal is encoded using either 1 out of 256 RZ, or 1 out of 4 codes. In addition, each
pause of the encoded signal is again encoded as a pulse of a certain width. The width of
the pulse is adjusted using the ModWidth register. The pulse width (tw) is calculated using
Equation 9 where the clock frequency constant (fclk)= 13.56 MHz.
(9)
8.10 Receiver circuitry
The SLRC400 uses an integrated quadrature demodulation circuit which extracts the
subcarrier signal from the 13.56 MHz ASK-modulated signal on pin RX.
The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90° between them. Both resulting subcarrier signals are amplified, filtered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
8.10.1 Receiver circuit block diagram
Figure 10 shows the block diagram of the receiver circuit. The receiving process can be
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see Section 8.10.2.1 on page 29). Sref() 1
MANT GsCfgCW 77------⎝⎠⎛⎞ EXP GsCfgCW•
---------------------- ----------------------------------------------------------= Swire ()TX1 500 mΩ≈Sx R Sref ()maxP R Swire ()TX1– () R Srel() R Swire ()TX1+•=w 2 ModWidth 1+clk-------------------------------------=
NXP Semiconductors SLRC400
ICODE reader IC
The demodulated signal is amplified by an adjustable amplifier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
The signal can be observed on its way through the receiver as shown in Figure 10. One
signal at a time can be routed to pin AUX using the T estAnaSelect register as described in
Section 14.2.2 on page 88.
8.10.2 Receiver operation
In general, the default settings programmed in the StartUp initialization file are suitable for
use with the SLRC400 to ICODE label data communication. However, in some
environments specific user settings will achieve better performance.
8.10.2.1 Automatic Q-clock calibration
The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
and a 90° phase-shifted quadrature signal (Q-clock). To achieve the optimum
demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90°. After
the reset phase, a calibration procedure is automatically performed.
Automatic calibration can be set-up to execute at the end of each Transceive command if
bit ClkQCalib= logic 0. Setting bit ClkQCalib= logic 1 disables all automatic calibrations
except after the reset sequence. Automatic calibration can also be triggered by the
software when bit ClkQCalib has a logic 0 to logic 1 transition.
NXP Semiconductors SLRC400
ICODE reader IC
Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or
approximately 4.8 μs.
The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift
between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the
phase-shift between the Q-clock and the I-clock is greater than 180°.
Remark: The StartUp initialization file enables automatic Q-clock calibration after a reset If bit ClkQCalib= logic 1, automatic calibration is not performed. Leaving this bit set to
logic 1 can be used to permanently disable automatic calibration. It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The
aim could be to disable automatic calibration and set the delay using the software.
Configuring the delay value using the software requires bit ClkQCalib to have been
previously set to logic 1 and a time interval of at least 4.8 μs has elapsed. Each delay
value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the
configured delay value is overwritten by the next automatic calibration interval.
8.10.2.2 Amplifier
The demodulated signal must be amplified by the variable amplifier to achieve the best
performance. The gain of the amplifiers can be adjusted using the RxControl1 register
Gain[1:0] bits; see Table 24.
8.10.2.3 Correlation circuitry
The correlation circuitry calculates the degree of matching between the received and an
expected signal. The output is a measure of the amplitude of the expected signal in the
received signal. This is done for both, the Q and I-channels. The correlator provides two
outputs for each of the two input channels, resulting in a total of four output signals.
Table 24. Gain factors for the internal amplifier
See Table 77 “RxControl1 register bit descriptions” on page 52 for additional information. 22 20 35 24 82 31 130 35
NXP Semiconductors SLRC400
ICODE reader IC
The correlation circuitry needs the phase information for the incoming label signal for
optimum performance. This information is defined for the microprocessor using the
BitPhase register. This value defines the phase relationship between the transmitter and
receiver clock in multiples of the BitPhase time (tBitPhase)=1/13.56MHz.
8.10.2.4 Evaluation and digitizer circuitry
The correlation results are evaluated for each bit-half of the Manchester coded signal. The
evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if the
current bit is valid If the bit is valid, its value is identified If the bit is not valid, it is checked to identify if it contains a bit-collision
Select the following levels for optimal using RxThreshold register bits: MinLevel[3:0]: defines the minimum signal strength of the stronger bit-halve’s signal
which is considered valid. CollLevel[3:0]: defines the minimum signal strength relative to the amplitude of the
stronger half-bit that has to be exceeded by the weaker half-bit of the Manchester
coded signal to generate a bit-collision. If the signal’s strength is below this value,
logic 1 and logic 0 can be determined unequivocally.
After data transmission, the label is not allowed to send its response before a preset time
period which is called the frame guard time in the ISO/IEC 15693 standard (similar to
ICODE1). The length of this time period is set using the RxWait register’s RxWait[7:0] bits.
The RxWait register defines when the receiver is switched on after data transmission to
the label in multiples of one bit duration.
If bit RcvClkSelI is set to logic 1, the I-clock is used to clock the correlator and evaluation
circuits. If bit RcvClkSelI is set to logic 0, the Q-clock is used.
Remark: It is recommended to use the Q-clock.
8.11 Serial signal switch
The SLRC400 comprises two main blocks: digital circuitry: comprising the state machines, encoder and decoder logic etc. analog circuitry: comprising the modulator, antenna drivers, receiver and
amplification circuitry
The interface between these two blocks can be configured so that the interface signals
are routed to pin SIGOUT.
8.11.1 Serial signal switch block diagram
Figure 12 shows the serial signal switches. Three different switches are implemented in
the serial signal switch enabling the SLRC400 to be used in different configurations.
The serial signal switch can also be used to check the transmitted and received data
during the design-in phase or for test purposes. Section 14.2.1 on page 87 describes the
analog test signals and measurements at the serial signal switch.
NXP Semiconductors SLRC400
ICODE reader IC
Section 8.11.2 describes the relevant registers and settings used to configure and control
the serial signal switch.
8.11.2 Serial signal switch registers
The RxControl2 register DecoderSource[1:0] bits define the input signal for the internal
Manchester decoder and are described in Table 25.
The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the
transmitted 13.56 MHz carrier frequency. The modulated signal drives pins TX1 and TX2.
Table 25. DecoderSource[1:0] values
See Table 86 on page 54 for additional information. 00 constant 0 01 output of the analog part. This is the default configuration
210 reserved
311 reserved
NXP Semiconductors SLRC400
ICODE reader IC
The SIGOUTSelect register’s SIGOUTSelect[2:0] bits select the input signal to be routed
to the internal Manchester decoder.
Remark: To use the SIGOUTSelect[2:0] bits, the TestDigiSelect register SignalToSIGOUT
bit must be logic 0.
Table 26. ModulatorSource[1:0] values
See Table 86 on page 54 for additional information. 00 constant 0 (carrier signal off on pins TX1 and TX2) 01 constant 1 (continuous carrier signal on pins TX1 and TX2) 10 modulation signal (envelope) from the internal encoder. This is the
default configuration. 11 reserved
Table 27. SIGOUTSelect[2:0] values
See Table 100 on page 57 for additional information. 000 constant LOW 001 constant HIGH 010 modulation signal (envelope) from the internal encoder 011 serial data stream to be transmitted; the same as for
SIGOUTSelect[2:0]= 001 but not encoded by the selected pulse
encoder 100 output signal of the receiver circuit; label modulation signal
regenerated and delayed 101 output signal of the subcarrier demodulator; Manchester coded label
signal
6110 reserved
7111 reserved
NXP Semiconductors SLRC400
ICODE reader IC
9. SLRC400 registers
9.1 Register addressing modes
Three methods can be used to operate the SLRC400: initiating functions and controlling data by executing commands configuring the functional operation using a set of configuration bits monitoring the state of the SLRC400 by reading status flags
The commands, configuration bits and flags are accessed using the microprocessor
interface. The SLRC400 can internally address 64 registers using six address lines.
9.1.1 Page registers
The SLRC400 register set is segmented into eight pages containing eight registers each.
A Page register can always be addressed, irrespective of which page is currently
selected.
9.1.2 Dedicated address bus
When using the SLRC400 with the dedicated address bus, the microprocessor defines
three address lines using address pins A0, A1 and A2. This enables addressing within a
page. To switch between registers in different pages a paging mechanism needs to be
used.
Table 28 shows how the register address is assembled.
9.1.3 Multiplexed address bus
The microprocessor may define all six address lines at once using the SLRC400 with a
multiplexed address bus. In this case either the paging mechanism or linear addressing
can be used.
Table 29 shows how the register address is assembled.
9.2 Register bit behavior
Bits and flags for different registers behave differently, depending on their functions. In
principle, bits with same behavior are grouped in common registers. Table 30 describes
the function of the Access column in the register tables.
Table 28. Dedicated address bus: assembling the register address PageSelect2 PageSelect1 PageSelect0 A2 A1 A0
Table 29. Multiplexed address bus: assembling the register address
Paging mode 1 PageSelect2 PageSelect1 PageSelect0 AD2 AD1 AD0
Linear
addressing AD5 AD4 AD3 AD2 AD1 AD0
NXP Semiconductors SLRC400
ICODE reader IC Table 30. Behavior and designation of register bits
R/W read and write These bits can be read and written by the microprocessor.
Since they are only used for control, their content is not
influenced by internal state machines.
Example: TimerReload register may be read and written by
the microprocessor. It will also be read by internal state
machines but never changed by them. dynamic These bits can be read and written by the microprocessor.
Nevertheless, they may also be written automatically by
internal state machines.
Example: the Command register changes its value
automatically after the execution of the command. read only These registers hold flags which have a value determined by
internal states only.
Example: the ErrorFlag register cannot be written externally
but shows internal states. write only These registers are used for control only. They may be written
by the microprocessor but cannot be read. Reading these
registers returns an undefined value.
Example: The TestAnaSelect register is used to determine the
signal on pin AUX however, it is not possible to read its
content.
0, 1 or X generic value Where applicable, the values 0 and 1 indicate the expected
logic value for a given bit. Where X is used, any logic value can
be entered.
NXP Semiconductors SLRC400
ICODE reader IC
9.3 Register overviewTable 31. SLRC400 register overview
Page 0: Command and status
00h Page selects the page register Table 33 on page40
01h Command starts and stops command execution Table 35 on page40
02h FIFOData input and output of 64-byte FIFO buffer Table 37 on page41
03h PrimaryStatus receiver and transmitter and FIFO buffer status flags Table 39 on page41
04h FIFOLength number of bytes buffered in the FIFO buffer Table 41 on page42
05h SecondaryStatus secondary status flags Table 43 on page43
06h InterruptEn enable and disable interrupt request control bits Table 45 on page43
07h InterruptRq interrupt request flags Table 47 on page44
Page 1: Control and status
08h Page selects the page register Table 33 on page40
09h Control control flags for functions such as timer and power saving Table 49 on page45
0Ah ErrorFlag show the error status of the last command executed Table 51 on page45
0Bh CollPos bit position of the first bit-collision detected on the RF interface Table 53 on page46
0Ch TimerValue value of the timer Table 55 on page46
0Dh CRCResultLSB LSB of the CRC coprocessor register Table 57 on page47
0Eh CRCResultMSB MSB of the CRC coprocessor register Table 59 on page47
0Fh PreSet0F these values must not be changed Table 61 on page47
Page 2: Transmitter and coder control
10h Page selects the page register Table 33 on page40
11h TxControl controls the operation of the antenna driver pins TX1 and TX2 Table 63 on page48
12h CwConductance selects the conductance of the antenna driver pins TX1 and TX2 Table 65 on page49
13h ModConductance defines the conductance of the output driver pins TX1 and TX2
during modulation
Table 67 on page49
14h CoderControl sets the bit encoding mode and framing during transmission Table 69 on page50
15h ModWidth selects the modulation pulse width Table 71 on page51
16h ModWidthSOF selects the SOF pulse-width modulation (ICODE1 fast mode) Table 73 on page51
17h PreSet17 these values must not be changed Table 75 on page51
Page 3: Receiver and decoder control Page selects the page register Table 33 on page40 RxControl1 controls receiver behavior Table 76 on page52 DecoderControl controls decoder behavior Table 78 on page52 BitPhase selects the bit-phase between transmitter and receiver clock Table 80 on page53 RxThreshold selects thresholds for the bit decoder Table 82 on page53 PreSet1D these values must not be changed Table 84 on page54
1Eh RxControl2 controls decoder and defines the receiver input source Table 85 on page54
1Fh ClockQControl clock control for the 90° phase-shifted Q-channel clock Table 87 on page54
NXP Semiconductors SLRC400
ICODE reader IC
Page 4: RF Timing and channel redundancy
20h Page selects the page register Table 33 on page40
21h RxWait selects the interval after transmission before the receiver starts Table 89 on page55
22h ChannelRedundancy selects the method and mode used to check data integrity on
the RF channel
Table 91 on page55
23h CRCPresetLSB preset LSB value for the CRC register Table 93 on page56
24h CRCPresetMSB preset MSB value for the CRC register Table 95 on page56
25h TimeSlotPeriod selects the time between automatically transmitted frames Table 97 on page57
26h SIGOUTSelect selects internal signal applied to pin SIGOUT, includes the MSB
of value TimeSlotPeriod; see Table 97 on page57
Table 99 on page57
27h PreSet27 these values are not changed Table 101 on page58
Page 5: FIFO, timer and IRQ pin configuration
28h Page selects the page register Table 33 on page40
29h FIFOLevel defines the FIFO buffer overflow and underflow warning levels Table 41 on page42
2Ah TimerClock selects the timer clock divider Table 104 on page59
2Bh TimerControl selects the timer start and stop conditions Table 106 on page59
2Ch TimerReload defines the timer preset value Table 108 on page60
2Dh IRQPinConfig configures pin IRQ output stage Table 110 on page60
2Eh PreSet2E these values are not changed Table 112 on page60
2Fh PreSet2F these values are not changed Table 113 on page60
Page 6: reserved registers
30h Page selects the page register Table 33 on page40
31h reserved reserved Table 114 on page61
32h reserved reserved
33h reserved reserved
34h reserved reserved
35h reserved reserved
36h reserved reserved
37h reserved reserved
Page 7: Test control
38h Page selects the page register Table 33 on page40
39h reserved reserved Table 115 on page61
3Ah TestAnaSelect selects analog test mode Table 116 on page61
3Bh PreSet3B reserved Table 118 on page62
3Ch PreSet3C reserved Table 119 on page62
3Dh TestDigiSelect selects digital test mode Table 120 on page62
3Eh reserved reserved Table 122 on page63
3Fh reserved reserved
Table 31. SLRC400 register overview …continued
NXP Semiconductors SLRC400
ICODE reader IC
9.4 SLRC400 register flags overview Table 32. SLRC400 register flags overview
AccessErr ErrorFlag 5 0Ah
BitPhase[7:0] BitPhase 7 to 0 1Bh
ClkQ180Deg ClockQControl 7 1Fh
ClkQCalib ClockQControl 6 1Fh
ClkQDelay[4:0] ClockQControl 4 to 0 1Fh
CollErr ErrorFlag 0 0Ah
CollLevel[3:0] RxThreshold 3 to 0 1Ch
CollPos[7:0] CollPos 7 to 0 0Bh
Command[5:0] Command 5 to 0 01h
CRC3309 ChannelRedundancy 5 22h
CRC8 ChannelRedundancy 4 22h
CRCErr ErrorFlag 3 0Ah
CRCMSBFirst ChannelRedundancy 6 22h
CRCPresetLSB[7:0] CRCPresetLSB 7 to 0 23h
CRCPresetMSB[7:0] CRCPresetMSB 7 to 0 24h
CRCReady SecondaryStatus 5 05h
CRCResultMSB[7:0] CRCResultMSB 7 to 0 0Eh
CRCResultLSB[7:0] CRCResultLSB 7 to 0 0Dh
DecoderSource[1:0] RxControl2 1 to 0 1Eh
E2Ready SecondaryStatus 6 05h
Err PrimaryStatus 2 03h
FIFOData[7:0] FIFOData 7 to 0 02h
FIFOLength[6:0] FIFOLength 7 to 0 04h
FIFOOvfl ErrorFlag 4 0Ah
FlushFIFO Control 0 09h
FramingErr ErrorFlag 2 0Ah
Gain[1:0] RxControl1 1 to 0 19h
GsCfgCW[5:0] CwConductance 5 to 0 12h
GsCfgMod[5:0] ModConductance 5 to 0 13h
HiAlert PrimaryStatus 1 03h
HiAlertIEn InterruptEn 1 06h
HiAlertIRq InterruptRq 1 07h
IdleIEn InterruptEn 2 06h
IdleIRq InterruptRq 2 07h
IFDetectBusy Command 7 01h
IRq PrimaryStatus 3 03h
IRQInv IRQPinConfig 1 2Dh
IRQPushPull IRQPinConfig 0 2Dh
LoAlert PrimaryStatus 0 03h
NXP Semiconductors SLRC400
ICODE reader IC
LoAlertIEn InterruptEn 0 06h
LoAlertIRq InterruptRq 0 07h
SIGOUTSelect[2:0] SIGOUTSelect 2 to 0 26h
MinLevel[3:0] RxThreshold 7 to 4 1Ch
ModemState[2:0] PrimaryStatus 6 to 4 03h
ModulatorSource[1:0] TxControl 6 to 5 11h
ModWidth[7:0] ModWidth 7 to 0 15h
PageSelect[2:0] Page 2 to 0 00h, 08h, 10h, 18h, 20h, 28h, 30h
and 38h
PowerDown Control 4 09h
RcvClkSelI RxControl2 7 1Eh
RxAutoPD RxControl2 6 1Eh
RxCRCEn ChannelRedundancy 3 22h
RxIEn InterruptEn 3 06h
RxIRq InterruptRq 3 07h
RxLastBits[2:0] SecondaryStatus 2 to 0 05h
RxWait[7:0] RxWait 7 to 0 21h
SetIEn InterruptEn 7 06h
SetIRq InterruptRq 7 07h
SignalToSIGOUT TestDigiSelect 7 3Dh
StandBy Control 5 09h
TAutoRestart TimerClock 5 2Ah
TestAnaOutSel[4:0] TestAnaSelect 3 to 0 3Ah
TestDigiSignalSel[6:0] TestDigiSelect 6 to 0 3Dh
TimerIEn InterruptEn 5 06h
TimerIRq InterruptRq 5 07h
TimerValue[7:0] TimerValue 7 to 0 0Ch
TPreScaler[4:0] TimerClock 4 to 0 2Ah
TReloadValue[7:0] TimerReload 7 to 0 2Ch
TRunning SecondaryStatus 7 05h
TStartTxBegin TimerControl 0 2Bh
TStartTxEnd TimerControl 1 2Bh
TStartNow Control 1 09h
TStopRxBegin TimerControl 2 2Bh
TStopRxEnd TimerControl 3 2Bh
TStopNow Control 2 09h
TX1RFEn TxControl 0 11h
TX2Cw TxControl 2 11h
TX2Inv TxControl 3 11h
TX2RFEn TxControl 1 11h
TxCRCEn ChannelRedundancy 2 22h
Table 32. SLRC400 register flags overview …continued
NXP Semiconductors SLRC400
ICODE reader IC
9.5 Register descriptions
9.5.1 Page 0: Command and status
9.5.1.1 Page register
Selects the page register.
9.5.1.2 Command register
Starts and stops the command execution.
TxIEn InterruptEn 4 06h
TxIRq InterruptRq 4 07h
TxLastBits[2:0] BitFraming 2 to 0 0Fh
UsePageSelect Page 7 00h, 08h, 10h, 18h, 20h, 28h, 30h
and 38h
WaterLevel[5:0] FIFOLevel 5 to 0 29h
ZeroAfterColl DecoderControl 5 1Ah
Table 32. SLRC400 register flags overview …continued
Table 33. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h)
reset value: 1000 0000b, 80h bit allocation
Table 34. Page register bit descriptions UsePageSelect1 the value of PageSelect[2:0] is used as the register address
A5, A4, and A3. The LSBs of the register address are defined using the address pins or the internal address latch,
respectively. the complete content of the internal address latch defines
the register address. The address pins are used as described in Table 4 on page7.
6 to 3 0000 - reserved
2 to 0 PageSelect[2:0]- when UsePageSelect= logic 1, the value of PageSelect is
used to specify the register page (A5, A4 and A3 of the
register address)
Table 35. Command register (address: 01h) reset value: x000 0000b, x0h bit allocation
NXP Semiconductors SLRC400
ICODE reader IC
9.5.1.3 FIFOData register
Input and output of the 64 byte FIFO buffer.
9.5.1.4 PrimaryStatus register
Bits relating to receiver, transmitter and FIFO buffer status flags.
Table 36. Command register bit descriptions IFDetectBusy - shows the status of interface detection logic interface detection finished successfully interface detection ongoing 0 - reserved
5 to 0 Command[5:0]- activates a command based on the Command code.
Reading this register shows which command is being
executed.
Table 37. FIFOData register (address: 02h) reset value: xxxx xxxxb, xxh bit allocation
Table 38. FIFOData register bit descriptions
7 to 0 FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. The FIFO
buffer acts as a parallel in to parallel out converter for all data streams.
Table 39. PrimaryStatus register (address: 03h) reset value: 0000 0001b, 01h bit allocation
NXP Semiconductors SLRC400
ICODE reader IC
9.5.1.5 FIFOLength register
Number of bytes in the FIFO buffer.
Table 40. PrimaryStatus register bit descriptions 0 - reserved
6 to 4 ModemState[2:0] shows the state of the transmitter and receiver
state machines:
000 Idle neither the transmitter or receiver are operating;
neither of them are started or have input data
001 TxSOF transmit start of frame pattern
010 TxData transmit data from the FIFO buffer (or
redundancy CRC check bits)
011 TxEOF transmit End Of Frame (EOF) pattern
100 GoToRx1 intermediate state 1; receiver starts
GoToRx2 intermediate state 2; receiver finishes
101 PrepareRx waiting until the RxWait register time period
expires
110 AwaitingRx receiver activated; waiting for an input signal on
pin RX
111 Receiving receiving data IRq - shows any interrupt source requesting attention
based on the InterruptEn register flag settings Err 1 any error flag in the ErrorFlag register is set HiAlert 1 the alert level for the number of bytes in the FIFO
buffer (FIFOLength[6:0]) is:
otherwise value= logic0
Example:
FIFOLength = 60, WaterLevel = 4 then
HiAlert= logic1
FIFOLength = 59, WaterLevel = 4 then
HiAlert= logic0 LoAlert 1 the alert level for number of bytes in the FIFO
buffer (FIFOLength[6:0]) is:
otherwise
value= logic0
Example:
FIFOLength = 4, WaterLevel = 4 then
LoAlert= logic1
FIFOLength = 5, WaterLevel = 4 then
LoAlert= logic0
HiAlert 64 FIFOLength– () WaterLevel≤=
LoAlert FIFOLength WaterLevel≤=
Table 41. FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation
NXP Semiconductors SLRC400
ICODE reader IC
9.5.1.6 SecondaryStatus register
Various secondary status flags.
9.5.1.7 InterruptEn register
Control bits to enable and disable passing of interrupt requests.
Table 42. FIFOLength bit descriptions 0 reserved
6 to 0 FIFOLength[6:0] gives the number of bytes stored in the FIFO buffer. Writing
increments the FIFOLength register value while reading decrements
the FIFOLength register value
Table 43. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit
allocation
Table 44. SecondaryStatus register bit descriptions TRunning 1 the timer unit is running and the counter decrements the
TimerValue register on the next timer clock cycle the timer unit is not running E2Ready 1 EEPROM programming is finished EEPROM programming is ongoing CRCReady 1 CRC calculation is finished CRC calculation is ongoing
4 to 3 00 - reserved
2 to 0 RxLastBits
[2:0] shows the number of valid bits in the last received byte. If zero,
the whole byte is valid
Table 45. InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation
Table 46. InterruptEn register bit descriptions SetIEn 1 indicates that the marked bits in the InterruptEn register are set clears the marked bits 0 - reserved TimerIEn - sends the TimerIRq timer interrupt request to pin IRQ[1] TxIEn - sends the TxIRq transmitter interrupt request to pin IRQ[1] RxIEn - sends the RxIRq receiver interrupt request to pin IRQ[1]
NXP Semiconductors SLRC400
ICODE reader IC
[1] This bit can only be set or cleared using bit SetIEn.
9.5.1.8 InterruptRq register
Interrupt request flags.
[1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq. IdleIEn - sends the IdleIRq idle interrupt request to pin IRQ[1] HiAlertIEn- sends the HiAlertIRq high alert interrupt request to pin IRQ[1] LoAlertIEn- sends the LoAlertIRq low alert interrupt request to pin IRQ[1]
Table 46. InterruptEn register bit descriptions …continued
Table 47. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation
Table 48. InterruptRq register bit descriptions SetIRq 1 sets the marked bits in the InterruptRq register clears the marked bits in the InterruptRq register - reserved TimerIRq 1 timer decrements the TimerValue register to zero timer decrements are still greater than zero TxIRq 1 TxIRq is set to logic 1 if one of the following events occurs:
Transceive command; all data transmitted
CalcCRC command; all data is processed
WriteE2 command; all data is programmed when not acted on by Transceive, CalcCRC or WriteE2 commands RxIRq 1 the receiver terminates reception still ongoing IdleIRq 1 command terminates correctly. For example; when the Command
register changes its value from any command to the Idle command. If an unknown command is started the IdleIRq bit is set.
Microprocessor start-up of the Idle command does not set the
IdleIRq bit. IdleIRq= logic 0 in all other instances HiAlertIRq 1 PrimaryStatus register HiAlert bit is set[1] PrimaryStatus register HiAlert bit is not set LoAlertIRq 1 PrimaryStatus register LoAlert bit is set[1] PrimaryStatus register LoAlert bit is not set
NXP Semiconductors SLRC400
ICODE reader IC
9.5.2 Page 1: Control and status
9.5.2.1 Page register
Selects the page register; see Section 9.5.1.1 “Page register” on page 40.
9.5.2.2 Control register
Various control flags, for timer, power saving, etc.
9.5.2.3 ErrorFlag register
Error flags show the error status of the last executed command.
Table 49. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation
Table 50. Control register bit descriptions
7 to 6 00 - reserved StandBy 1 activates Standby mode. The current consuming blocks are
switched off but the clock keeps running PowerDown 1 activates Soft Power-down mode. The current consuming
blocks are switched off including the clock 0 - reserved TStopNow 1 immediately stops the timer. Reading this bit always returns
logic 0 TStartNow 1 immediately starts the timer. Reading this bit will always
returns logic 0 FlushFIFO 1 immediately clears the internal FIFO buffer’s read and write
pointer, the FIFOLength[6:0] bits are set to logic 0 and the
FIFOOvfl flag. Reading this bit always returns logic 0
Table 51. ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 00h bit allocation
Table 52. ErrorFlag register bit descriptions
7 to 60 - reserved AccessErr 1 set when the access rights to the EEPROM are violated set when an EEPROM related command starts FIFOOvfl 1 set when the microprocessor or SLRC400 internal state machine (e.g. receiver) tries to write data to the FIFO buffer when it is full CRCErr 1 set when RxCRCEn is set and the CRC fails automatically set during the PrepareRx state in the receiver start
phase
NXP Semiconductors SLRC400
ICODE reader IC
9.5.2.4 CollPos register
Bit position of the first bit-collision detected on the RF interface.
9.5.2.5 TimerValue register
Value of the timer.
9.5.2.6 CRCResultLSB register
LSB of the CRC coprocessor register. FramingErr 1 set when the SOF is incorrect automatically set during the PrepareRx state in the receiver start
phase 0 - reserved CollErr 1 set when a bit-collision is detected automatically set during the PrepareRx state in the receiver start
phase
Table 52. ErrorFlag register bit descriptions …continued
Table 53. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation
Table 54. CollPos register bit descriptions
7 to 0 CollPos[7:0] this register shows the bit position of the first detected collision in a
received frame.
Example:
00h indicates a bit collision in the start bit
01h indicates a bit collision in the 1 st bit
08h indicates a bit collision in the 8 th bit
Table 55. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation
Table 56. TimerValue register bit descriptions
7 to 0 TimerValue[7:0] this register shows the timer counter value
NXP Semiconductors SLRC400
ICODE reader IC
9.5.2.7 CRCResultMSB register
MSB of the CRC coprocessor register.
9.5.2.8 BitFraming register
Adjustments for bit oriented frames.
Table 57. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit
allocation
Table 58. CRCResultLSB register bit descriptions
7 to 0 CRCResultLSB[7:0] gives the CRC register’s least significant byte value; only valid if
CRCReady= logic1
Table 59. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit
allocation
Table 60. CRCResultMSB register bit descriptions
7 to 0 CRCResultMSB[7:0] gives the CRC register’s most significant byte value; only valid if
CRCReady= logic1.
The register’s value is undefined for 8-bit CRC calculation.
Table 61. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation
NXP Semiconductors SLRC400
ICODE reader IC
9.5.3 Page 2: Transmitter and control
9.5.3.1 Page register
Selects the page register; see Section 9.5.1.1 “Page register” on page 40.
9.5.3.2 TxControl register
Controls the logical behavior of the antenna pin TX1 and TX2.
Table 62. BitFraming register bit descriptions - reserved
6 to 4 RxAlign[2:0] defines the bit position for the first bit received to be stored in
the FIFO buffer. Additional received bits are stored in the next
subsequent bit positions. After reception, RxAlign[2:0] is
automatically cleared. For example:
000 the LSB of the received bit is stored in bit position 0 and the
second received bit is stored in bit position 1
001 the LSB of the received bit is stored in bit position 1, the
second received bit is stored in bit position 2
111 the LSB of the received bit is stored in bit position 7, the
second received bit is stored in the next byte in bit position 0 - reserved
2 to 0 TxLastBits[2:0]- defines the number of bits of the last byte that shall be
transmitted. 000 indicates that all bits of the last byte will be
transmitted. TxLastBits[2:0] is automatically cleared after
transmission.
Table 63. TxControl register (address: 11h) reset value: 0100 1000b, 48h bit allocation
Table 64. TxControl register bit descriptions 0 - this value must not be changed
6 to 5 ModulatorSource[1:0] selects the source for the modulator input: modulator input is LOW modulator input is HIGH modulator input is the internal encoder reserved Force100ASK 1 forces a 100 % ASK modulation independent of the
ModConductance register setting TX2Inv 1 the output signal on pin TX2 is an inverted 13.56 MHz
carrier
NXP Semiconductors SLRC400
ICODE reader IC
9.5.3.3 CwConductance register
Selects the conductance of the antenna driver pins TX1 and TX2.
See Section 8.9.3 on page 25 for detailed information about GsCfgCW[5:0].
9.5.3.4 ModConductance register
Defines the driver output conductance.
See Section 8.9.3 on page 25 for detailed information about GsCfgMod[5:0]. TX2Cw 1 the output on pin TX2 is a continuously unmodulated
13.56 MHz carrier enables modulation of the 13.56 MHz carrier signal TX2RFEn 1 the output signal on pin TX2 is the 13.56 MHz carrier
modulated by the transmission data TX2 is driven at a constant output level TX1RFEn 1 the output signal on pin TX1 is the 13.56 MHz carrier
modulated by the transmission data TX1 is driven at a constant output level
Table 64. TxControl register bit descriptions …continued
Table 65. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit
allocation
Table 66. CwConductance register bit descriptions
7 to 6 00 these values must not be changed
5 to 0 GsCfgCW[5:0] defines the Cwconductance register value for the output driver. This can be used to regulate the output power/current consumption and
operating distance.
Table 67. ModConductance register (address: 13h) reset value: 0000 0101b, 05h bit
allocation
Table 68. ModConductance register bit descriptions
7 to 6 00 these values must not be changed
5 to 0 GsCfgMod[5:0] defines the ModConductance register value for the output
driver during modulation. This is used to regulate the
modulation index.
NXP Semiconductors SLRC400
ICODE reader IC
9.5.3.5 CoderControl register
Sets the clock rate and the coding mode.
Table 69. CoderControl register (address: 14h) reset value: 0010 1100b, 2Ch bit allocation
Table 70. CoderControl register bit descriptions SendOnePulse 1 forces ISO/IEC 15693 modulation. Used to switch to the next
TimeSlotPeriod if the Inventory command is used. This bit is
not cleared automatically, it must be reset by the user to logic0. 0 - this value must not be changed
5 to 3 CoderRate[2:0] this register defines the clock rate for the encoder circuit
000 reserved
001 reserved
010 reserved
011 reserved
100 ~106 kHz
101 ICODE1 standard mode and ISO/IEC 15693 (~52.97 kHz)
110 ICODE1 fast mode (~26.48 kHz)
111 reserved
2 to 0 TxCoding[2:0] this register defines the bit coding mode and framing during
transmission
000 reserved
001 reserved
010 reserved
011 reserved
100 ICODE1 standard mode (1 out of 256 coding)
101 ICODE1 fast mode (RZ coding)
110 ISO/IEC 15693 standard mode (1 out of 256 coding)
111 ISO/IEC 15693 fast mode (1 out of 4 coding)
NXP Semiconductors SLRC400
ICODE reader IC
9.5.3.6 ModWidth register
Selects the pulse-modulation width.
9.5.3.7 ModWidthSOF register
9.5.3.8 PreSet17 register
These bit values must not be changed.
9.5.4 Page 3: Receiver and decoder control
9.5.4.1 Page register
Selects the page register; see Section 9.5.1.1 “Page register” on page 40.
9.5.4.2 RxControl1 register
Controls receiver operation.
Table 71. ModWidth register (address: 15h) reset value: 0011 1111b, 3Fh bit allocation
Table 72. ModWidth register bit descriptions
7 to 0 ModWidth[7:0] defines the width of the modulation pulse based on
tmod =2× (ModWidth + 1)/ fclk where fclk = 13.56 MHz oscillator
clock. Preset for ICODE1 (fast and standard modes) and
ISO/IEC 15693 is 3Fh: modulation width = 9.44 μs.
Table 73. ModWidthSOF register (address: 16h) reset value: 0011 1111b, 3Fh bit allocation
Table 74. ModWidthSOF register bit descriptions
7 to 0 ModWidthSOF defines the width of the modulation pulse for SOF as
tmod =2× (ModWidth + 1)/ fclk the register settings are:
3Fh ICODE1 standard mode; modulation width SOF= 9.44 μs
73h ICODE1 fast mode; modulation width SOF= 18.88 μs
3Fh ISO/IEC 15693; modulation width SOF= 9.44 μs
Table 75. PreSet17 register (address: 17h) reset value: 0000 0000b, 00h bit allocation

Partno	Mfg	Dc	Qty	Available	Descript
SLRC400 01T \|SLRC40001T	NXP	N/a	335	avai	Standard ISO/IEC 15693 reader solution
SLRC40001T	PHILIPS	N/a	125	avai	Standard ISO/IEC 15693 reader solution
SLRC40001T	PHI	N/a	718	avai	Standard ISO/IEC 15693 reader solution