SJA1000T ,Stand-alone CAN controllerFUNCTIONAL DESCRIPTION10.2 Additional AC information6.1 Description of the CAN controller blocks11 ..
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SJA1000T
Stand-alone CAN controller
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
CONTENTS FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
6.1 Description of the CAN controller blocks
6.1.1 Interface Management Logic (IML)
6.1.2 Transmit Buffer (TXB)
6.1.3 Receive Buffer (RXB, RXFIFO)
6.1.4 Acceptance Filter (ACF)
6.1.5 Bit Stream Processor (BSP)
6.1.6 Bit Timing Logic (BTL)
6.1.7 Error Management Logic (EML)
6.2 Detailed description of the CAN controller
6.2.1 PCA82C200 compatibility
6.2.2 Differences between BasicCAN and PeliCAN
mode
6.3 BasicCAN mode
6.3.1 BasicCAN address layout
6.3.2 Reset values
6.3.3 Control Register (CR)
6.3.4 Command Register (CMR)
6.3.5 Status Register (SR)
6.3.6 Interrupt Register (IR)
6.3.7 Transmit buffer layout
6.3.8 Receive buffer
6.3.9 Acceptance filter
6.4 PeliCAN mode
6.4.1 PeliCAN address layout
6.4.2 Reset values
6.4.3 Mode Register (MOD)
6.4.4 Command Register (CMR)
6.4.5 Status Register (SR)
6.4.6 Interrupt Register (IR)
6.4.7 Interrupt Enable Register (IER)
6.4.8 Arbitration Lost Capture register (ALC)
6.4.9 Error Code Capture register (ECC)
6.4.10 Error Warning Limit Register (EWLR)
6.4.11 RX Error Counter Register (RXERR)
6.4.12 TX Error Counter Register (TXERR)
6.4.13 Transmit buffer
6.4.14 Receive buffer
6.4.15 Acceptance filter
6.4.16 RX Message Counter (RMC)
6.4.17 RX Buffer Start Address register (RBSA)
6.5 Common registers
6.5.1 Bus Timing Register 0 (BTR0)
6.5.2 Bus Timing Register 1 (BTR1)
6.5.3 Output Control Register (OCR)
6.5.4 Clock Divider Register (CDR) LIMITING VALUES THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS
10.1 AC timing diagrams
10.2 Additional AC information PACKAGE OUTLINES SOLDERING
12.1 Introduction
12.2 DIP
12.2.1 Soldering by dipping or by wave
12.2.2 Repairing soldered joints
12.3 SO
12.3.1 Reflow soldering
12.3.2 Wave soldering
12.3.3 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
FEATURES Pin compatibility to the PCA82C200 stand-alone CAN
controller Electrical compatibility to the PCA82C200 stand-alone
CAN controller PCA82C200 mode (BasicCAN mode is default) Extended receive buffer (64-byte FIFO) CAN 2.0B protocol compatibility (extended frame
passive in PCA82C200 compatibility mode) Supports 11-bit identifier as well as 29-bit identifier Bit rates up to 1 Mbits/s PeliCAN mode extensions: Error counters with read/write access Programmable error warning limit Last error code register Error interrupt for each CAN-bus error Arbitration lost interrupt with detailed bit position Single-shot transmission (no re-transmission) Listen only mode (no acknowledge, no active error
flags) Hot plugging support (software driven bit rate
detection) Acceptance filter extension (4-byte code, 4-byte
mask) Receptionof ‘own’ messages (self reception request) 24 MHz clock frequency Interfaces to a variety of microprocessors Programmable CAN output driver configuration Extended ambient temperature range (−40to +125 °C).
GENERAL DESCRIPTIONThe SJA1000isa stand-alone controllerfor the Controller
Area Network (CAN) used within automotive and general
industrial environments. It is the successor of the
PCA82C200 CAN controller (BasicCAN) from Philips
Semiconductors. Additionally,a new modeof operationis
implemented (PeliCAN) which supports the CAN 2.0B
protocol specification with several new features.
ORDERING INFORMATION
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
BLOCK DIAGRAM
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000 PINNING
Note XTAL1 and XTAL2 pins should be connected to VSS1 via 15 pF capacitors.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000 FUNCTIONAL DESCRIPTION
6.1 Description of the CAN controller blocks
6.1.1 INTERFACE MANAGEMENT LOGIC (IML)
The interface management logic interprets commands
from the CPU, controls addressing of the CAN registers
and provides interrupts and status informationto the host
microcontroller.
6.1.2 TRANSMIT BUFFER (TXB)
The transmit buffer is an interface between the CPU and
the Bit Stream Processor (BSP) that is able to store a
complete message for transmission over the CAN
network. The bufferis13 bytes long, writtentoby the CPU
and read out by the BSP.
6.1.3 RECEIVE BUFFER (RXB, RXFIFO)
The receive bufferisan interface between the acceptance
filter and the CPU that stores the received and accepted
messages from the CAN-bus line. The Receive Buffer
(RXB) representsa CPU-accessible 13-bytewindowof the
Receive FIFO (RXFIFO), which has a total length of bytes.
With the helpof this FIFO the CPUis ableto process one
message while other messages are being received.
6.1.4 ACCEPTANCE FILTER (ACF)
The acceptance filter compares the received identifier with
the acceptance filter register contents and decides
whether this message should be accepted or not. In the
eventofa positive acceptance test, the complete message
is stored in the RXFIFO.
6.1.5 BIT STREAM PROCESSOR (BSP)
Thebit stream processorisa sequencerwhichcontrols the
data stream between the transmit buffer, RXFIFO and the
CAN-bus. It also performs the error detection, arbitration,
stuffing and error handling on the CAN-bus.
6.1.6 BIT TIMING LOGIC (BTL)
The bit timing logic monitors the serial CAN-bus line and
handles the bus line-relatedbit timing.Itis synchronizedto
the bit stream on the CAN-bus on a
‘recessive-to-dominant’ busline transitionat the beginninga message (hard synchronization) and re-synchronized
on further transitions during the reception of a message
(soft synchronization). The BTL also provides
programmable time segments to compensate for the
propagation delay times and phase shifts (e.g. due to
oscillator drifts) and to define the sample point and the
number of samples to be taken within a bit time.
6.1.7 ERROR MANAGEMENT LOGIC (EML)
The EML is responsible for the error confinement of the
transfer-layer modules. It receives error announcements
from the BSP and then informs the BSP and IML about
error statistics.
6.2 Detailed description of the CAN controller
The SJA1000 is designed to be software and
pin-compatible to its predecessor, the PCA82C200
stand-alone CAN controller. Additionally, a lot of new
functions are implemented. To achieve the software
compatibility, two different modes of operation are
implemented: BasicCAN mode; PCA82C200 compatible PeliCAN mode; extended features.
The modeof operationis selected with the CAN-modebit
located within the clock divider register. Default mode
upon reset is the BasicCAN mode.
6.2.1 PCA82C200 COMPATIBILITY
In BasicCAN mode the SJA1000 emulates all known
registers from the PCA82C200 stand-alone CAN
controller. The characteristics, as described in Sections
6.2.1.1to 6.2.1.4 are different from the PCA82C200
design with respect to software compatibility.
6.2.1.1 Synchronization mode
The SYNC bit in the control register is removed (CR.6 in
the PCA82C200). Synchronization is only possible by a
recessive-to-dominant transitionon the CAN-bus. Writing thisbit hasno effect.To achieve compatibilityto existing
application software, a read access to this bit will reflect
the previously written value (flip-flop without effect).
6.2.1.2 Clock divider register
The clock divider registeris usedto select the CAN mode
of operation (BasicCAN/PeliCAN). Therefore one of the
reserved bits within the PCA82C200 is used. Writing a
value between0 and 7, as allowed for the PCA82C200,
will enter the BasicCAN mode. The default state is divide 12 for Motorola mode and divide by 2 for Intel mode. additional functionis implemented within anotherof the
reserved bits. Setting of bit CBP (see Table 49) enables
the internal RX input comparator to be bypassed thereby
reducing the internal delays if an external transceiver
circuit is used.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.2.1.3 Receive buffer
The dual receive buffer concept of the PCA82C200 is
replacedby the receive FIFO from the PeliCAN controller.
This has noeffectto the application software exceptfor the
data overrun probability. Now more than two messages
may be received (up to 64 bytes) until a data overrun
occurs.
6.2.1.4 CAN 2.0B
The SJA1000 is designed to support the full CAN 2.0B
protocol specification, which means that the extended
oscillator tolerance is implemented as well as the
processing of extended frame messages. In BasicCAN
modeitis possibleto transmit and receive standard frame
messages only (11-bit identifier). If extended frame
messages (29-bit identifier) are detectedon the CAN-bus,
they are tolerated and an acknowledge is given if the
message was correct, but there is no receive interrupt
generated.
6.2.2 DIFFERENCES BETWEEN BASICCAN AND PELICAN
MODE
In the PeliCAN mode the SJA1000 appears with a
re-organized register mapping with a lot of new features.
All known bits from the PCA82C200 design are available
as well as several new ones. In the PeliCAN mode the
complete CAN 2.0B functionality is supported (29-bit
identifier).
Main new features of the SJA1000 are: Reception and transmission of standard and extended
frame format messages Receive FIFO (64-byte) Single/dual acceptance filter with mask and code
register for standard and extended frame Error counters with read/write access Programmable error warning limit Last error code register Error interrupt for each CAN-bus error Arbitration lost interrupt with detailed bit position Single-shot transmission (no re-transmissionon erroror
arbitration lost) Listen only mode (monitoring of the CAN-bus, no
acknowledge, no error flags) Hot plugging supported (disturbance-free software
driven bit rate detection) Disable CLKOUT by hardware.
6.3 BasicCAN mode
6.3.1 BASICCAN ADDRESS LAYOUT
The SJA1000 appears to a microcontroller as a
memory-mappedI/O device.An independent operationof
both devicesis guaranteedbya RAM-like implementation
of the on-chip registers.
The address area of the SJA1000 consists of the control
segment and the message buffers. The control segmentis
programmed during an initialization download in order to
configure communication parameters (e.g. bit timing).
Communication over the CAN-bus is also controlled via
this segment by the microcontroller. During initialization
the CLKOUT signal may be programmed to a value
determined by the microcontroller. message, which shouldbe transmitted, hastobe written
to the transmit buffer. After a successful reception the
microcontroller may read the received message from the
receive buffer and then release it for further use.
The exchange of status, control and command signals
between the microcontroller and the SJA1000 is
performed in the control segment. The layout of this
segmentis shownin Table3. Afteran initial download, the
contents of the registers acceptance code, acceptance
mask, bus timing registers0 and 1 and output control
should not be changed. Therefore these registers may
onlybe accessed when the reset requestbitin the control
register is set HIGH.
For register access, two different modes have to be
distinguished: Reset mode Operating mode.
The reset mode (see Table 3, control register, bit Reset
Request) is entered automatically after a hardware reset
or when the controller enters the bus-off state (see
Table 5, status register, bit Bus Status). The operating
mode isactivatedby resettingof the reset requestbitin the
control register.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Table 1 BasicCAN address allocation; note1
Notes It should be noted that the registers are repeated within higher CAN address areas (the most significant bits of the
8-bit CPU address are not decoded: CAN address 32 continues with CAN address 0 and so on). Test registeris usedfor production testing only. Using this register during normal operation may resultin undesired
behaviour of the device. Some bits are writeable in reset mode only (CAN mode and CBP).
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.3.2 RESET VALUES
Detectionofa ‘reset request’ resultsin aborting the current transmission/receptionofa message and entering the reset
mode. On the ‘1-to-0’ transition of the reset request bit, the CAN controller returns to the operating mode.
Table 2 Reset mode configuration; notes1 and2
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes X means that the value of these registers or bits is not influenced. Remarks in brackets explain functional meaning. Reading the command register will always reflect a binary ‘11111111’. On bus-off the error interrupt is set, if enabled. Internal read/write pointers of the RXFIFO are reset to their initial values. A subsequent read access to the RXB
would show undefined data values (parts of old messages). If a message is transmitted, this message is written in
parallelto the receive buffer butno receive interruptis generated and the receive buffer areais not locked. So, even the receive bufferis empty, the last transmitted message maybe read from the receive buffer untilitis overridden
by the next received or transmitted message.
Upona hardware reset, the RXFIFO pointers are resetto the physical RAM address‘0’. Setting CR.0by softwareor
due to the bus-off event will reset the RXFIFO pointers to the currently valid FIFO start address which is different
from the RAM address ‘0’ after the first release receive buffer command.
6.3.3 CONTROL REGISTER (CR)
The contentsof the control register are usedto change the behaviourof the CAN controller. Bits maybe setor resetby
the attached microcontroller which uses the control register as a read/write memory.
Table 3 Bit interpretation of the control register (CR); CAN address0
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes Any write access to the control register has to set this bit to logic 0 (reset value is logic0). In the PCA82C200 this bit was used to select the synchronization mode. Because this mode is not longer
implemented, setting thisbit hasno influenceon the microcontroller. Dueto software compatibility setting thisbitis
allowed. This bit will not change after hardware or software reset. In addition the value written by users software is
reflected. Reading this bit will always reflect a logic1. During a hardware reset or when the bus status bit is set to logic 1 (bus-off), the reset request bit is set to logic1
(present). If this bit is accessed by software, a value change will become visible and takes effect first with the next
positive edgeof the internalclock which operates with1⁄2of the external oscillator frequency. Duringan external reset
the microcontroller cannot set the reset requestbitto logic0 (absent). Therefore, after having set the reset request
bit to logic 0, the microcontroller must check this bit to ensure that the external reset pin is not being held LOW.
Changes of the reset request bit are synchronized with the internal divided clock. Reading the reset request bit
reflects the synchronized status.
After the reset request bit is set to logic 0 the SJA1000 will wait for: One occurrence of bus-free signal (11 recessive bits), if the preceding reset request has been caused by a
hardware reset or a CPU-initiated reset 128 occurrencesof bus-free,if thepreceding reset request has been causedbya CAN controller initiated bus-off,
before re-entering the bus-on mode;it shouldbe noted that several registers are modifiedif the reset requestbit
was set (see also Table2).
6.3.4 COMMAND REGISTER (CMR)
A command bit initiates an action within the transfer layer of the SJA1000. The command register appears to the
microcontroller as a write only memory. If a read access is performed to this address the byte ‘11111111’ is returned.
Between two commandsat least one internal clock cycleis neededto process. The internal clockis dividedby two from
the external oscillator frequency.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Table 4 Bit interpretation of the command register (CMR); CAN address1
Notes The SJA1000 will enter sleep modeif the sleepbitis setto logic1 (sleep); thereisno bus activity andno interruptis
pending. Setting of GTS with at least one of the previously mentioned exceptions valid will result in a wake-up
interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to allow a
host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW.
The SJA1000 will wakeup when oneof the three previously mentioned conditionsis negated: after ‘GoTo Sleep’is
set LOW (wake-up), there is bus activity or INT is driven LOW (active). On wake-up, the oscillator is started and a
wake-up interrupt is generated. A sleeping SJA1000 which wakes up due to bus activity will not be able to receive
thismessage untilit detects11 consecutiverecessive bits (bus-freesequence).It shouldbe noted that settingof GTS not possiblein reset mode. After clearingof reset request, settingof GTSis possible first, when bus-freeis detected
again. This commandbitis usedto clear the data overrun condition indicatedby the data overrun status bit.As longas the
data overrun statusbitissetno further data overrun interruptis generated.Itis allowedto give the clear data overrun
command at the same time as a release receive buffer command. After reading the contents of the receive buffer, the microcontroller can release this memory space of the RXFIFO
by setting the release receive buffer bit to logic 1. This may result in another message becoming immediately
available within the receive buffer. This event will force another receive interrupt, if enabled. If there is no other
message available no further receive interrupt is generated and the receive buffer status bit is cleared. The abort transmissionbitis used when the CPU requires the suspensionof the previously requested transmission,
e.g.to transmita more urgent message before.A transmission alreadyin progressis not stopped.In orderto seeif
the original message had been either transmitted successfully or aborted, the transmission complete status bit
should be checked. This should be done after the transmit buffer status bit has been set to logic 1 (released) or a
transmit interrupt has been generated. If the transmission request was set to logic 1 in a previous command, it cannot be cancelled by setting the
transmission request bit to logic 0. The requested transmission may be cancelled by setting the abort transmission
bit to logic1.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.3.5 STATUS REGISTER (SR)
The content of the status register reflects the status of the SJA1000. The status register appears to the microcontroller
as a read only memory.
Table 5 Bit interpretation of the status register (SR); CAN address2
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes When the transmit error counter exceeds the limit of 255 [the bus status bit is set to logic 1 (bus-off)] the
CAN controller will set the reset requestbitto logic1 (present) andan error interruptis generated,if enabled.It will
stay in this mode until the CPU clears the reset request bit. Once this is completed the CAN controller will wait the
minimum protocol-defined time (128 occurrences of the bus-free signal). After that the bus status bit is cleared
(bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error interrupt is generated, if
enabled. Errors detected during reception or transmission will affect the error counters according to the CAN 2.0B protocol
specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU
warning limit of 96. An error interrupt is generated, if enabled. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle. The transmission complete status bit is set to logic 0 (incomplete) whenever the transmission request bit is set to
logic 1. The transmission complete status bit will remain at logic 0 (incomplete) until a message is transmitted
successfully.If the CPU triesto writeto the transmit buffer when the transmit buffer statusbitisat logic0 (locked), the written byte
will not be accepted and will be lost without being indicated. When a message that shall be received has passed the acceptance filter successfully (i.e. earliest after arbitration
field), the CAN controller needs space in the RXFIFO to store the message descriptor. Accordingly there must be
enough spacefor each data byte which has been received.If thereis not enough spaceto store the message, that
message willbe dropped and the data overrun condition willbe indicatedto the CPU only,if this received message
has no errors until the last but one bit of end of frame (message becomes valid). After readinga message storedin the RXFIFO and releasing this memory space with the command release receive
buffer, this bit is cleared. If there is another message available within the FIFO this bit is set again with the next bit
quantum (tscl).
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.3.6 INTERRUPT REGISTER (IR)
The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, the
INT pin is activated (LOW). After this register is read by the microcontroller, all bits are reset what results in a floating
level at INT. The interrupt register appears to the microcontroller as a read only memory.
Table 6 Bit interpretation of the interrupt register (IR); CAN address3
Notes Reading this bit will always reflect a logic1. A wake-up interrupt is also generated if the CPU tries to set go to sleep while the CAN controller is involved in bus
activities or a CAN interrupt is pending. The overrun interrupt bit (if enabled) and the data overrun status bit are set at the same time. The receive interrupt bit (if enabled) and the receive buffer status bit are set at the same time.
It should be noted that the receive interrupt bit is cleared upon a read access, even if there is another message
available within the FIFO. The moment the release receive buffer commandis given and thereis another message
valid within the receive buffer, the receive interrupt is set again (if enabled) with the next tscl.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.3.7 TRANSMIT BUFFER LAYOUT
The global layout ofthe transmit bufferis shownin Table7. Thebuffer servesto storea message from the microcontroller
to be transmitted by the SJA1000. It is subdivided into a descriptor and data field. The transmit buffer can be written to
and read out by the microcontroller in operating mode only. In reset mode a ‘FFH’ is reflected for all bytes.
Table 7 Layout of transmit buffer
6.3.7.1 Identifier (ID)
The identifier consists of 11 bits (ID.10to ID.0). ID.10 is
the most significantbit, whichis transmittedfirston the bus
during the arbitration process. The identifier acts as the
message’s name. It is used in a receiver for acceptance
filtering and also determining the bus access priority
during the arbitration process. The lower the binary value
of the identifier the higher the priority. This is due to a
larger number of leading dominant bits during arbitration.
6.3.7.2 Remote Transmission Request (RTR)
If this bit is set, a remote frame will be transmitted via the
bus. This means thatno data bytes are included within this
frame. Nevertheless,itis necessaryto specify the correct
data length code which depends on the corresponding
data frame with the same identifier coding. the RTRbitis not set,a data frame willbe sent including
the number of data bytes as specified by the data length
code.
6.3.7.3 Data Length Code (DLC)
The number of bytes in the data field of a message is
coded by the data length code. At the start of a remote
frame transmission the data length codeis not considered
due to the RTR bit being at logic 1 (remote). This forces
the number of transmitted/received data bytes to be
logic 0. Nevertheless, the data length code must be
specified correctly to avoid bus errors if two
CAN controllers startaremote frame transmissionwith the
same identifier simultaneously.
The range of the data byte count is 0to8 bytes and is
coded as follows:
DataByteCount=8× DLC.3+4× DLC.2+2× DLC.1+
DLC.0
For reasonsof compatibilityno data length code>8 should used.Ifa value>8is selected,8 bytes are transmitted
in the data frame with the data length code specified in
DLC.
6.3.7.4 Data field
The numberof transferred data bytesis determinedby the
data length code. The first bit transmitted is the most
significant bit of data byte 1 at address 12.
6.3.8 RECEIVE BUFFER
The global layoutof the receive bufferis very similarto the
transmit buffer described in Section 6.3.7. The receive
bufferis the accessible partof the RXFIFO andis located
in the range between CAN address 20 and 29.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Identifier, remote transmission requestbit and data length
code have the same meaning and locationas describedin
the transmit buffer but within the address range20to 29.
As illustrated in Fig.4 the RXFIFO has space for message bytes in total. The number of messages that
can be stored in the FIFO at any particular moment
dependson the lengthof the individual messages.If there
is not enough space for a new message within the
RXFIFO, the CAN controller generates a data overrun
condition. A message which is partly written into the
RXFIFO, when the data overrun condition occurs, is
deleted. This situation is indicated to the microcontroller
via the status register and the data overrun interrupt, if
enabled and the frame was received without any errors
until the last but one bit of end of frame (RX message
becomes valid).
6.3.9 ACCEPTANCE FILTER
With the helpof the acceptance filter the CAN controlleris
ableto allow passingof received messages totheRXFIFO
only when the identifier bits of the received message are
equal to the predefined ones within the acceptance filter
registers. The acceptance filter is defined by the
acceptance code register (ACR; see Section 6.3.9.1) and
the acceptance mask register (AMR; see Section 6.3.9.2).
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.3.9.1 Acceptance Code Register (ACR)
Table 8 ACR bit allocation; can address4
This register can be accessed (read/write), if the reset
request bit is set HIGH (present). When a message is
received which passes the acceptance test and there is
receive buffer space left, then the respective descriptor
and data field are sequentially stored in the RXFIFO.
When the complete message has been correctly received
the following occurs: The receive status bit is set HIGH (full)If the receive interrupt enablebitis set HIGH (enabled),
the receive interrupt is set HIGH (set).
The acceptance code bits (AC.7to AC.0) and the eight
most significant bits of the message’s identifier
(ID.10to ID.3) must be equal to those bit positions which
are marked relevant by the acceptance mask bits
(AM.7to AM.0). If the conditions as described in the
following equation are fulfilled, acceptance is given:
(ID.10to ID.3)≡ (AC.7to AC.0)]∨ (AM.7to AM.0) 11111111
6.3.9.2 Acceptance Mask Register (AMR)
Table 9 AMR bit allocation; CAN address5
This register can be accessed (read/write), if the reset
request bit is set HIGH (present). The acceptance mask
register qualifies which of the corresponding bits of the
acceptance code are ‘relevant’ (AM.X= 0) or ‘don’t care’
(AM.X= 1) for acceptance filtering.
6.3.9.3 Other registers
The other registers are described in Section 6.5.
6.4 PeliCAN mode
6.4.1 PELICAN ADDRESS LAYOUT
The CAN controller’s internal registers appearto the CPU on-chip memory mapped peripheral registers. Because
the CAN controller can operate in different modes
(operating/reset; see also Section 6.4.3), one has to
distinguish between different internal address definitions.
Starting from CAN address32 the complete internal RAM
(80-byte) is mapped to the CPU interface.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Table 10 PeliCAN address allocation; note1
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes It should be noted that the registers are repeated within higher CAN address areas (the most significant bit of the
8-bit CPU address is not decoded: CAN address 128 continues with CAN address 0 and so on). Test registeris usedfor production testing only. Using this register during normal operation may resultin undesired
behaviour of the device. SFF= Standard Frame Format. EFF= Extended Frame Format. These address allocations reflect the FIFO RAM space behind the current message. The contents are random after
power-up and contain the beginning of the next message which is received after the current one. If no further
message is received, parts of old messages may occur here. Some bits are writeable in reset mode only (CAN mode, CBP, RXINTEN and clock off).
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.4.2 RESET VALUES
Detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the
reset mode. On the ‘1-to-0’ transition of the reset mode bit, the CAN controller returns to the mode defined within the
mode register.
Table 11 Reset mode configuration; notes1 and2
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes X means that the value of these registers or bits is not influenced. Remarks in brackets explain functional meaning. On bus-off the error warning interrupt is set, if enabled.If the reset mode was entered duetoa bus-off condition, the receive error counteris cleared and the transmit error
counter is initialized to 127 to count-down the CAN-defined bus-off recovery time consisting of 128 occurrences of consecutive recessive bits. Internal read/write pointers of the RXFIFO are reset to their initial values. A subsequent read access to the RXB
would show undefined data values (parts of old messages).a messageis transmitted, this messageis writtenin parallelto the receive buffer.A receive interruptis generated
only if this transmission was forced by the self reception request. So, even if the receive buffer is empty, the last
transmitted message may be read from the receive buffer until it is overwritten by the next received or transmitted
message.
Upona hardware reset, the RXFIFO pointers are resetto the physical RAM address‘0’. Setting CR.0by softwareor
due to the bus-off event will reset the RXFIFO pointers to the currently valid FIFO start address (RBSA register)
which is different from the RAM address ‘0’ after the first release receive buffer command.
6.4.3 MODE REGISTER (MOD)
The contents of the mode register are used to change the behaviour of the CAN controller. Bits may be set or reset by
the CPU which uses the control register as a read/write memory. Reserved bits are read as logic0.
Table 12 Bit interpretation of the mode register (MOD); CAN address‘0’
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes The SJA1000 will enter sleep modeif the sleep modebitis setto logic1 (sleep); then thereisno bus activity andno
interrupt is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a
wake-up interrupt. After sleep modeis set, the CLKOUT signal continues untilat least15bit times have passed,to
allow a host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW.
The SJA1000 will wakeup when oneof the three previously mentioned conditionsis negated: after SMis set LOW
(wake-up), there is bus activity or INT is driven LOW (active). On wake-up, the oscillator is started and a wake-up
interrupt is generated. A sleeping SJA1000 which wakes up due to bus activity will not be able to receive this
message untilit detects11 consecutive recessive bits (bus-free sequence).It shouldbe noted that settingof SMis
not possible in reset mode. After clearing of reset mode, setting of SM is possible first, when bus-free is detected
again. A write access to the bits MOD.1 to MOD.3 is only possible, if the reset mode is entered previously. This mode of operation forces the CAN controller to be error passive. Message transmission is not possible.
The listen only mode canbe used e.g.for software drivenbit rate detection and ‘hot plugging’.All other functions can
be used like in normal mode. Duringa hardware resetor when the bus statusbitis setto logic1 (bus-off), the reset modebitis also setto logic1
(present). If this bit is accessed by software, a value change will become visible and takes effect first with the next
positive edgeof the internal clock which operatesat halfof the external oscillator frequency. Duringan external reset
the microcontroller cannot set the reset modebitto logic0 (absent). Therefore, after having set the reset modebitto
logic1, the microcontroller must check thisbitto ensure that the external reset pinis not being held HIGH. Changes
of the reset request bit are synchronized with the internal divided clock. Reading the reset request bit reflects the
synchronized status. After the reset mode bit is set to logic 0 the CAN controller will wait for: One occurrenceof bus-free signal (11 recessive bits),if the preceding resethas beencausedbya hardware reset
or a CPU-initiated reset. 128 occurrencesof bus-free,if the preceding reset has been causedbya CAN controller initiated bus-off, before
re-entering the bus-on mode.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.4.4 COMMAND REGISTER (CMR)
A command bit initiates an action within the transfer layer of the CAN controller. This register is write only, all bits will
returna logic0 when being read. Between two commandsat least one internal clock cycleis neededin orderto proceed.
The internal clock is half of the external oscillator frequency.
Table 13 Bit interpretation of the command register (CMR); CAN address1
Notes Upon self reception request a message is transmitted and simultaneously received if the acceptance filter is set to
the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception (see also self test
mode in mode register). Setting the command bits CMR.0 and CMR.1 simultaneously results in sending the transmit message once. re-transmission will be performed in the event of an error or arbitration lost (single-shot transmission).
Setting the command bits CMR.4 and CMR.1 simultaneously resultsin sending the transmit message once using the
self reception feature. No re-transmission will be performed in the event of an error or arbitration lost.
Setting the command bits CMR.0, CMR.1 and CMR.4 simultaneously resultsin sending the transmit message once
as described for CMR.0 and CMR.1.
The moment the transmit status bit is set within the status register, the internal transmission request bit is cleared
automatically.
Setting CMR.0 and CMR.4 simultaneously will ignore the set CMR.4 bit. This commandbitis usedto clear the data overrun condition indicatedby the data overrun status bit.As longas the
data overrun status bit is set no further data overrun interrupt is generated. After reading the contents of the receive buffer, the CPU can release this memory space in the RXFIFO by setting
the release receive bufferbitto logic1. This may resultin another message becoming immediately available within
the receive buffer. If there is no other message available, the receive interrupt bit is reset.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000 The abort transmissionbitis used when the CPU requires the suspensionof the previously requested transmission,
e.g.to transmita more urgent message before.A transmission alreadyin progressis not stopped.In orderto seeif
the original message has been either transmitted successfully or aborted, the transmission complete status bit
should be checked. This should be done after the transmit buffer status bit has been set to logic 1 or a transmit
interrupt has been generated. shouldbe noted thata transmit interruptis generated evenif the message was aborted because the transmit buffer
status bit changes to ‘released’. If the transmission request was set to logic 1 in a previous command, it cannot be cancelled by setting the
transmission request bit to logic 0. The requested transmission may be cancelled by setting the abort transmission
bit to logic1.
6.4.5 STATUS REGISTER (SR)
The contentof the status register reflects the statusof the CAN controller. The status register appearsto the CPUasa
read only memory.
Table 14 Bit interpretation of the status register (SR); CAN address2
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes When the transmit error counter exceeds the limit of 255, the bus status bit is set to logic 1 (bus-off), the
CAN controller will set the reset modebitto logic1 (present) andan error warning interruptis generated,if enabled.
The transmit error counterissetto 127 and the receive error counteris cleared.It will stayin this mode until the CPU
clears the reset mode bit. Once this is completed the CAN controller will wait the minimum protocol-defined time
(128 occurrences of the bus-free signal) counting down the transmit error counter. After that the bus status bit is
cleared (bus-on), the error statusbitis setto logic0 (ok), the error counters are reset andan error warning interrupt
is generated, if enabled. Reading the TX error counter during this time gives information about the status of the
bus-off recovery. Errors detected during reception or transmission will effect the error counters according to the CAN 2.0B protocol
specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU
warning limit (EWLR).An error warning interruptis generated,if enabled. The default valueof EWLR after hardware
reset is 96. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle. If both bits are set the
controlleris waitingto become idle again. Aftera hardware reset11 consecutive recessive bits havetobe detected
until the idle status is reached. After bus-off this will take 128 of 11 consecutive recessive bits. The transmission complete statusbitis setto logic0 (incomplete) whenever the transmission requestbitor the self
reception request bit is set to logic 1. The transmission complete status bit will remain at logic 0 until a message is
transmitted successfully. If the CPU tries to write to the transmit buffer when the transmit buffer status bit is logic 0 (locked), the written byte
will not be accepted and will be lost without this being indicated. When a message that is to be received has passed the acceptance filter successfully, the CAN controller needs
spacein the RXFIFOto store the message descriptor andfor each data byte which has been received.If thereis not
enough spaceto store the message, that messageis dropped and the data overrun conditionis indicatedto the CPU the moment this message becomes valid.If this messageis not completed successfully (e.g. duetoan error),no
overrun condition is indicated. After readingall messages within the RXFIFO and releasing their memory space with the command release receive
buffer this bit is cleared.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
6.4.6 INTERRUPT REGISTER (IR)
The interrupt register allows the identificationofan interrupt source. When oneor more bitsof this register are set,a CAN
interrupt willbe indicatedto the CPU. After this registeris readby the CPU allbits are resetexceptfor the receiveinterrupt
bit.
The interrupt register appears to the CPU as a read only memory.
Table 15 Bit interpretation of the interrupt register (IR); CAN address3
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Notes A wake-up interruptis also generated,if the CPU triesto set the sleepbit while the CAN controlleris involvedin bus
activities or a CAN interrupt is pending. The behaviour of this bit is equivalent to that of the receive buffer status bit with the exception, that RI depends on
the corresponding interrupt enable bit (RIE). So the receive interrupt bit is not cleared upon a read access to the
interrupt register. Giving the command ‘release receive buffer’ will clearRI temporarily.If thereis another message
available within the FIFO after the release command, RI is set again. Otherwise RI remains cleared.
6.4.7 INTERRUPT ENABLE REGISTER (IER)
The register allows to enable different types of interrupt sources which are indicated to the CPU.
The interrupt enable register appears to the CPU as a read/write memory.
Table 16 Bit interpretation of the interrupt enable register (IER); CAN address4
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
Note The receive interrupt enablebit has direct influenceto the receive interruptbit and the external interrupt output INT.
If RIE is cleared, the external INT pin will become HIGH immediately, if there is no other interrupt pending.
6.4.8 ARBITRATION LOST CAPTURE REGISTER (ALC)
This register contains information about thebit positionof losing arbitration. The arbitration lost capture register appears
to the CPU as a read only memory. Reserved bits are read as logic0.
Table 17 Bit interpretation of the arbitration lost capture register (ALC); CAN address11
On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At the same time, the current bit
position of the bit stream processor is captured into the arbitration lost capture register. The content within this register
is fixed until the users software has read out its contents once. The capture mechanism is then activated again.
The corresponding interrupt flag locatedin the interrupt registeris cleared during the read accessto the interrupt register.
A new arbitration lost interrupt is not possible until the arbitration lost capture register is read out once.
Philips Semiconductors Product specification
Stand-alone CAN controller SJA1000
