SG3525AP013TR ,REGULATING PULSE WIDTH MODULATORSABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage 40 ViV Collector Supply Voltage ..
SG3526 ,REGULATING PULSE WIDTH MODULATOR
SG3526BN , REGULATING PULSE WIDTH MODULATOR
SG3526BN , REGULATING PULSE WIDTH MODULATOR
SG3526BN , REGULATING PULSE WIDTH MODULATOR
SG3526DW , REGULATING PULSE WIDTH MODULATOR
SI-8120S , Full-Mold, Separate Excitation Switching Type
SI-8120S , Full-Mold, Separate Excitation Switching Type
SI-8120S , Full-Mold, Separate Excitation Switching Type
SI-8153B , SWITCHING VOLTAGE REGULATOR
SI-8201L , Switching Type(Self Oscillation Type with Coil)
SI-8203L , Switching Type(Self Oscillation Type with Coil)
SG2525-SG2525AP013TR-SG3525-SG3525AP013TR
REGULATING PULSE WIDTH MODULATORS
SG252 5A
SG3525 AREGULATING PULSE WIDTH MODULATORS. 8 TO 35 V OPERATION. 5.1 V REFERENCE TRIMMED TO ± 1 %. 100 Hz TO 500 KHz OSCILLATOR RANGE. SEPARATE OSCILLATOR SYNC TERMINAL. ADJUSTABLE DEADTIME CONTROL. INTERNAL SOFT-START. PULSE-BY-PULSE SHUTDOWN. INPUT UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS. LATCHING PWM TO PREVENT MULTIPLE
PULSES. DUAL SOURCE/SINK OUTPUT DRIVERS
DESCRIPTIONThe SG3525A series of pulse width modulator inte-
grated circuits are designed to offer improved per-
formance and lowered external parts count when
used in designing all types of switching power sup-
plies. The on-chip + 5.1 V reference is trimmed to ±
1 % and the input common-mode range of the error
amplifier includes the reference voltage eliminating
external resistors. A sync input to the oscillator al-
lows multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor between the CT and the discharge terminals
provide a wide range of dead time ad- justment.
These devices also feature built-in soft-start circuitry
with only an external timing capacitor required. A
shutdown terminal controls both the soft-start circu-
ity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shut-
down commands. These functions are also control-
led by an undervoltage lockout which keeps the out-
puts off and the soft-start capacitor discharged for
sub-normal input voltages. This lockout circuitry in-
cludes approximately 500 mV of hysteresis for jitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason,
the outputs will remain off for the duration of the pe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG3525A output stage features NOR logic, giving a
LOW output for an OFF state.
PIN CONNECTIONS AND ORDERING NUMBERS (top view)June 2000 1/12
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 × 20 mm ; 0.65 mm
thickness with infinite heatsink.
BLOCK DIAGRAM
SG2525A-SG3525A2/12
ELECTRICAL CHARACTERISTICS (V# i = 20 V, and over operating temperature, unless otherwise specified)
SG2525A-SG3525A3/12
ELECTRICAL CHARACTERISTICS (continued) These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.• Tested at fosc = 40 KHz (RT = 3.6 KΩ, CT = 10nF, RD = 0 Ω). Approximate oscillator frequency is defined by :f =
CT (0.7 RT + 3 RD) DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : Gv = gM RL where RL is the resistance
from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded.
SG2525A-SG3525A4/12
TEST CIRCUIT
SG2525A-SG3525A5/12
