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SE95D-SE95DP
Ultra high accuracy digital temperature sensor and thermal watchdog
General descriptionThe SE95 is a temperature-to-digital converter using an on-chip band gap temperature
sensor and Sigma Delta analog-to-digital conversion technique. The device is also a
thermal detector providing an overtemperature detection output.
The SE95 contains a number of data registers accessed by a controller via the 2-wire
serial I2 C-bus interface:
Configuration register (Conf) to store the device settings such as sampling rate,
device operation mode, OS operation mode, OS polarity, and OS fault queue
Temperature register (Temp) to store the digital Temp reading
Set-point registers (Tos and Thyst)to store programmable overtemperature shutdown
and hysteresis limits
Identification register (ID) to store manufacturer numbers
The device includes an open-drain output (pin OS) which becomes active when the
temperature exceeds the programmed limits. There are three selectable logic address
pins (pins A2 to A0) so that eight devices can be connected on the same bus without
address conflict.
The SE95 can be configured for different operation conditions. It can be set in normal
mode to periodically monitor the ambient temperature, or in shutdown mode to minimize
power consumption. The OS output operates in either of two selectable modes: OS
comparator mode and OS interrupt mode.Its active state canbe selectedas either HIGH LOW. The fault queue that defines the numberof consecutive faultsin orderto activate
the OS output is programmable as well as the set-point limits.
The temperature register always stores a 13-bit two’s complement data giving a
temperature resolution of 0.03125 °C. This high temperature resolution is particularly
useful in applications of measuring precisely the thermal drift or runaway. For normal
operation and compatibility with the LM75A, only the11 MSBs are read, witha resolution 0.125°Cto provide the accuracies specified.Tobe compatible with the LM75, read only
the 9 MSBs.
The device is powered-up in normal operation mode with the OS in comparator mode,
temperature threshold of 80 °C and hysteresis of 75 °C, so that it can be used as a
stand-alone thermostat with those pre-defined temperature set points. The conversion
rate is programmable, with a default of 10 conversions/s.
SE95
Ultra high accuracy digital temperature sensor and thermal
watchdog
Rev. 07 — 2 September 2009 Product data sheet
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdog Features Pin-for-pin replacement for industry standard LM75/LM75A Specification of a single part over supply voltage from 2.8 V to 5.5V Small 8-pin package types: SO8 and TSSOP8 (MSOP8)I2 C-bus interface to 400 kHz with up to 8 devices on the same bus Supply voltage from 2.8 V to 5.5V Temperature range from −55 °C to +125°C 13-bit ADC that offers a temperature resolution of 0.03125°C Temperature accuracy of ± 1 °C from −25 °C to +100°C Programmable temperature threshold and hysteresis set points Supply current of 7.0 μA in shutdown mode for power conservation Stand-alone operation as thermostat at power-up ESD protection exceeds 1000Vfor Human Body Model (HBM) per JESD22-A114 and
150 V for Machine Model (MM) per JESD22-A115 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Applications System thermal management Personal computers Electronics equipment Industrial controllers
Ordering information
Table 1. Ordering informationSE95D −55 °C to +125°C SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
SE95DP −55 °C to +125°C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
SE95U −55 °C to +125 °C- wafer -
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdog Block diagram Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin descriptionSDA 1 I2 C-bus serial bidirectional data line digital I/O; open-drain
SCL 2 I2 C-bus serial clock digital input 3 overtemperature shutdown output; open-drain
GND 4 ground; to be connected to the system ground 5 user-defined address bit 2 digital input
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdog Functional description
7.1 General operationThe SE95 uses the on-chip band gap sensor to measure the device temperature with a
resolution of 0.03125 °C and stores the 13-bit two’s complement digital data, resulting
from 13-bit analogto digital conversion, into register Temp. Register Temp canbe readat
any time by a controller on the I2 C-bus. Reading temperature data does not affect the
conversion in progress during the read operation.
The device can be set to operate in either mode: normal or shutdown mode. In normal
operation mode, by default, the temperature-to-digital conversion is executed every
100 ms and register Temp is updated at the end of each conversion. In shutdown mode,
the device becomes idle, data conversion is disabled and register Temp holds the latest
result; however, the deviceI2 C-bus interfaceis still active and register write/read operation
can be performed. The device operation mode is controlled by programming bit
SHUTDOWN of register Conf. The temperature conversion is initiated when the device is
powered up or returned to normal mode from shutdown mode. addition,at the endof each conversionin normal mode, the temperature data (orT emp)
in register Temp is automatically compared with the overtemperature shutdown threshold
data (or Tos) stored in register Tos, and the hysteresis data (or Thyst) stored in register
Thyst,in orderto set the stateof the device OS output accordingly. The registers Tos and
Thyst are write/read capable, and both operate with 9-bit two’s complement digital data. match with this 9-bit operation, register Temp uses only the9 MSB bitsofits 13-bit data
for the comparison.
The device temperature conversion rateis programmable and canbe chosentobe oneof
the four values: 0.125, 1.0, 10, and 30 conversions/s. The default conversion rate is conversions/s. Furthermore, the conversion rate is selected by programming bits TEVAL[1:0] of register Conf as shown in Table 6. Note that the average supply current
as well as the device power consumption increase with the conversion rate.
The way that the OS output responds to the comparison operation depends upon the OS
operation mode selected by configuration bit OS_COMP_INT, and the user-defined fault
queue defined by configuration bits OS_F_QUE[1:0].
In OS comparator mode, the OS output behaves like a thermostat. It becomes active
when the temperature exceeds Tos, andis reset when the temperature drops below Thyst.
Reading the device registers or putting the device into shutdown mode does not change
the stateof the OS output. The OS outputin this case canbe usedto control cooling fans
or thermal switches. 6 user-defined address bit 1 digital input 7 user-defined address bit 0 digital input
VCC 8 supply voltage
Table 2. Pin description …continued
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdogIn OS interrupt mode, the OS output is used for thermal interruption. When the device is
powered-up, the OS outputis first activated only when Temp exceeds Tos; thenit remains
active indefinitely until being resetbya readof any register. Once the OS output has been
activatedby crossing Tos and then reset,it canbe activated again only when Temp drops
below Thyst; then again, it remains active indefinitely until being reset by a read of any
register. The OS interrupt operation would be continued in this sequence: Tos trip, reset,
Thyst trip, reset, Tos trip, reset, Thyst trip, reset, and etc. Putting the device into shutdown
mode also resets the OS output.
In both cases, comparator mode and interrupt mode, the OS output is activated only if a
number of consecutive faults, defined by the device fault queue, has been met. The fault
queueis programmable and storedin bits OS_F_QUE[1:0],of register Conf. Also, the OS
output active state is selectable as HIGH or LOW by setting accordingly the bit OS_POL
of register Conf.
At power-up, the device is put into normal operation mode, register Tos is set to 80 °C,
register Thystis setto75 °C, OS active stateis selected LOW and the fault queueis equal 1. The data reading of register T emp is not available until the first conversion is
completed in about33 ms.
The OS response to the temperature is illustrated in Figure4.
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
7.2 OS output and polarityThe OS output is an open-drain output and its state represents results of the device
watchdog operation as described in Section 7.1. In order to observe this output state, an
external pull-up resistor is needed. The resistor should be as large as possible, up to
200 kΩ,to minimize the Temp reading error dueto internal heatingby the high OS sinking
current.
The OS output active state can be selected as HIGH or LOW by programming bit
OS_POL of register Conf: setting bit OS_POL to logic 1 selects OS active HIGH and
settingto logic0 sets OS active LOW.At power-up,bit OS_POLis equalto logic0 and the
OS active state is LOW.
7.3 OS comparator and interrupt modesAs described in Section 7.1, the OS output responds to the result of the comparison
between register Temp data and the programmed limits, in registers Tos and Thyst, in
different ways depending on the selected OS mode: OS comparator or OS interrupt. The
OS mode is selected by programming bit OS_COMP_INT of register Conf: setting bit
OS_COMP_INTto logic1 selects the OS interrupt mode, and settingto logic0 selects the
OS comparator mode. At power-up, bit OS_COMP_INT is equal to logic 0 and the OS
comparator is selected.
The main difference between the two modes is that in OS comparator mode, the OS
output becomes active when Temp has exceeded Tos and reset when Temp has dropped
below Thyst, readinga registeror putting the device into shutdown mode does not change
the state of the OS output; while in OS interrupt mode, once it has been activated either exceeding Tosor dropping below Thyst, the OS output will remain active indefinitely until
readinga registeror putting the device into shutdown mode occurs, then the OS outputis
reset.
Temperature limits Tos and Thyst must be selected so that Tos > Thyst. Otherwise, the OS
output state will be undefined.
7.4 OS fault queueFault queue is defined as the number of faults that must occur consecutively to activate
the OS output. It is provided to avoid false tripping due to noise. Because faults are
determined at the end of data conversions, fault queue is also defined as the number of
consecutive conversions returning a temperature trip. The value of fault queue is
selectable by programming the two bits OS_F_QUE[1:0] in register Conf. Notice that the
programmed data and the fault queue value are not the same. Table 3 shows the
one-to-one relationship between them.At power-up, fault queue data=00 and fault queue
value=1.
Table 3. Fault queue table116
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
7.5 Shutdown modeThe device operation modeis selectedby programmingbit SHUTDOWNof register Conf.
Setting bit SHUTDOWN to logic 1 will put the device into shutdown mode. Resetting bit
SHUTDOWN to logic 0 will return the device to normal mode.
In shutdown mode, the device draws a small current of approximately 7.5 μA and the
power dissipation is minimized; the temperature conversion stops, but the I2 C-bus
interface remains active and register write/read operation can be performed. If the OS
output is in comparator mode, then it remains unchanged. In interrupt mode, the OS
output is reset.
7.6 Power-up default and power-on resetThe SE95 always powers-up in its default state with:
Normal operation mode
OS comparator mode
Tos = 80°C
Thyst = 75°C
OS output active state is LOW
Pointer value is logic 0
When the power supply voltage is dropped below the device power-on reset level of
approximately 1.9 V (POR) and then rises up again, the device will be reset to its default
condition as listed above.
I2 C-bus serial interfaceThe SE95 can be connected to a compatible 2-wire serial interface I2 C-bus as a slave
device under the controlofa controlleror master device, using two device terminals, SCL
and SDA. The controller must provide the SCL clock signal and write/read data to and
from the device through the SDA terminal. Note that if the I2 C-bus common pull-up
resistors have not been installedas requiredforI2 C-bus, thenan external pull-up resistor,
approximately 10 kΩ, is needed for each of these two terminals. The bus communication
protocols are described in Section 8.7 “Protocols for writing and reading the registers”.
8.1 Slave addressThe SE95 slave address on the I2 C-bus is partially defined by the logic applied to the
device address pins A2, A1 and A0. Each pin is typically connected either to GND for
logic 0, or to VCC for logic 1. These pins represent the three LSB bits of the device 7-bit
address. The other four MSB bits of the address data are preset to 1001 by hard wiring
inside the SE95. Table 4 shows the device's complete address and indicates that up to devices can be connected to the same bus without address conflict. Because the input
pins SCL, SDA and A2to A0, are not internally biased,itis important that they should not
be left floating in any application.
0Chisa reserved addressfor SMBus Alert Response Address (ARA). Thisisan optional
command from the SMBus specificationto allow SMBus devicesto respondtoan SMBus
master with their slave device if they are generating an interrupt. The SE95 will send a
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdogfalse alertif the address 0Chis sent and cannotbe activeon theI2 C-busif this addressis
used. Consider using the SE98 sinceit supports SMBus ARAas wellas time-out features
and provides±1 °C accuracy.
8.2 Register listThe SE95 contains 7 data registers. The registers can be 1 byte or 2 bytes wide, and are
defined in Table 5. The registers are accessed by the value in the content of the pointer
register during I2 C-bus communication. The types of registers are: read only, read/write,
and reserved for manufacturer use. Note that when reading a two-byte register, the host
must provide enough clock pulses as required by the I2 C-bus protocol (see Section 8.7)
for the device to completely return both data bytes. Otherwise the device may hold the
SDA line in LOW state, resulting in a bus hang condition.
8.3 Register pointerThe register pointer or pointer byte is an 8-bit data byte that is equivalent to the register
command in the I2 C-bus definitions and is used to identify the device register to be
accessed for a write or read operation. Its values are listed as pointer values in Table5.
For the device register I2 C-bus communication, the pointer byte may or may not need to
be included within the command as illustrated in the I2 C-bus protocol figures in
Section 8.7.
The command statements for writing data to a register must always include the pointer
byte; while the command statements for reading data from a register may or may not
includeit.To reada register thatis different from the one that has been recently read, the
pointer byte mustbe included. However,to re-reada register that has been recently read,
the pointer byte may not have to be included in the reading.
Table 4. Address table1001 A2 A1 A0
Table 5. Register tableConf 01h R/W 00h configuration register: containsa single 8-bit data byte;
to set an operating condition
Temp 00h read
only
N/A temperature register: contains two 8-bit data bytes; to
store the measured Temp
Tos 03h R/W 5000h overtemperature shutdown threshold register: contains
two 8-bit data bytes; to store the overtemperature
shutdown limit; default Tos =80°C
Thyst 02h R/W 4B00h hysteresis register: contains two 8-bit data bytes; to
store the hysteresis limit; bit 7 to bit 0 are also used in
OTP (One Time Programmable) test mode to supply
OTP write data; default Thyst =75°C 05h read
only
A1h identification register: contains a single 8-bit data byte
for the manufacturer ID code
Reserved 04h N/A N/A reserved
Reserved 06h N/A N/A reserved
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdogAt power-up, the pointer value is preset to logic 0 for register Temp; users can then read
the temperature without specifying the pointer byte.
8.4 Configuration registerThe Configuration (Conf) register is a read/write register and contains an 8-bit
non-complement data byte that is used to configure the device for different operating
conditions. Table 6 shows the bit assignments of this register.
8.5 Temperature registerThe Temperature (Temp) register holds the digital result of temperature measurement or
monitor at the end of each analog to digital conversion. This register is read only and
contains two 8-bit data bytes consisting of one Most Significant Byte (MSByte) and one
Least Significant Byte (LSByte). However, only13 bitsof those two bytes are usedto store
the Temp data in two’s complement format with the resolution of 0.03125 °C.T able7
shows the bit arrangement of the Temp data in the data bytes.
Table 6. Conf registerLegend: * = default value. reserved R/W 0* reserved for manufacturer’s use
6 and 5 RATEVAL[1:0] R/W sets the conversion rate
00* 10 conversion/s 0.125 conversion/s 1 conversion/s 30 conversion/s
4 and 3 OS_F_QUE[1:0] R/W OS fault queue programming
00* queue value = 1 queue value = 2 queue value = 4 queue value = 6 OS_POL R/W OS polarity selection OS active LOW OS active HIGH OS_COMP_INT R/W OS operation mode selection OS comparator OS interrupt SHUTDOWN R/W 0 operation mode normal shutdown
Table 7. Temp register
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdogWhen reading register Temp, all 16 bits of the two data bytes (MSByte and LSByte) must collected and then the two’s complement data value accordingto the desired resolution
must be selected for the temperature calculation. Table 8 shows the example for 11-bit
two’s complement data value, Table 9 shows the example for 13-bit two’s complement
data value.
When converting into the temperature the proper resolution must be used as listed in
Table 10 using either one of these two formulae: If the Temp data MSB= 0, then: Temp (°C) = +(Temp data)× value resolutionIf theT emp data MSB=1, then:T emp (°C)= −(two’s complementT emp data)× value
resolution
Table 11 shows some examples of the results for the 11-bit calculations.
Table 8. Example 11-bit two’s complement Temp register
Table 9. Example 13-bit two’s complement register
Table 10. Temp data and Temp value resolution8 bit 1.0°C
9 bit 0.5°C
10 bit 0.25°C
11 bit 0.125°C
12 bit 0.0625°C
13 bit 0.03125°C
Table 11. Temp register value011 1111 1000 3F8 1016 +127.000°C
011 1111 0111 3F7 1015 +126.875°C
011 1111 0001 3F1 1009 +126.125°C
011 1110 1000 3E8 1000 +125.000°C
000 1100 1000 0C8 200 +25.000°C
000 0000 0001 001 1 +0.125°C
000 0000 0000 000 0 0.000°C
111 1111 1111 7FF −1 −0.125°C
111 0011 1000 738 −200 −25.000°C
110 0100 1001 649 −439 −54.875°C
110 0100 1000 648 −440 −55.000°C
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdogObviously, for 9-bit Temp data application in replacing the industry standard LM75, just
use only 9 MSB bits of the two bytes and disregard 7 LSB of the LSByte. The 9-bit Temp
data with 0.5 °C resolution of the SE95 is defined exactly in the same way as for the
standard LM75 and it is here similar to the Tos and Thyst registers.
8.6 Overtemperature shutdown threshold and hysteresis registersThese two registers, are write/read registers, and also called set-point registers. They are
used to store the user-defined temperature limits, called overtemperature shutdown
threshold (Tos) and hysteresis temperature (Thyst),for the device watchdog operation.At
the end of each conversion the Temp data will be compared with the data stored in these
two registers in order to set the state of the device OS output; see Section 7.1.
Eachof the set-point registers contains two 8-bit data bytes consistingof one MSByte and
one LSByte the same as register T emp. However, only 9 bits of the two bytes are used to
store the set-point datain two’s complement format with the resolutionof 0.5 °C.T able12
and Table 13 show the bit arrangement of the T os data and Thyst data in the data bytes.
Notice that because only 9-bit data are used in the set-point registers, the device uses
only the 9 MSB of the Temp data for data comparison.
Whena set-point registeris read,all16 bits are providedto the bus and mustbe collected
by the controller to complete the bus operation. However, only the 9 most significant bits
should be used and the 7 LSB of the LSByte are equal to zero and should be ignored.
Table 14 shows examples of the limit data and value.
Table 12. Tos register
Table 13. Thyst register
Table 14. Tos and Thyst register0 1111 1010 0FA 250 125.0°C
0 0011 0010 032 50 25.0°C
0 0000 0001 001 1 0.5°C
0 0000 0000 000 0 0.0°C
1 1111 1111 1FF −1 −0.5°C
1 1100 1110 1CE −50 −25.0°C
1 1001 0010 192 −110 −55.0°C
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
8.7 Protocols for writing and reading the registersThe communication between the host and the SE95 must follow the rules strictly as
defined by the I2 C-bus management. The protocols for SE95 register read/write
operations are illustrated in Figure 5 to Figure 10 together with the following definitions: Beforea communication, theI2 C-bus mustbe freeor not busy.It means that the SCL
and SDA lines must both be released by all devices on the bus, and they become
HIGH by the bus pull-up resistors. The host must provide SCL clock pulses necessary for the communication. Data is
transferred in a sequence of 9 SCL clock pulses for every 8-bit data byte followed by
1-bit status of the acknowledgement. During data transfer, except the START and STOP signals, the SDA signal must be
stable while the SCL signal is HIGH. It means that the SDA signal can be changed
only during the LOW duration of the SCL line. S: ST ART signal, initiated by the host to start a communication, the SDA goes from
HIGH-to-LOW while the SCL is HIGH. RS: RE-START signal, same as the START signal, to start a read command that
follows a write command. P: STOP signal, generated by the host to stop a communication, the SDA goes from
LOW-to-HIGH while the SCL is HIGH. The bus becomes free thereafter. W: write bit, when the write/read bit is in a write command. R: read bit, when the write/read bit is logic 1 in a read command. A: device acknowledge bit, returned by the SE95. It is logic 0 if the device works
properly and logic 1 if not. The host must release the SDA line during this period in
order to give the device the control on the SDA line.
10. A’: master acknowledge bit, not returned by the device, but set by the master or host
in reading 2-byte data. During this clock period, the host must set the SDA line to
LOW in order to notify the device that the first byte has been read for the device to
provide the second byte onto the bus.
11. NA: not-acknowledge bit. During this clock period, both the device and host release
the SDA line at the end of a data transfer, the host is then enabled to generate the
stop signal.
12. In a write protocol, data is sent from the host to the device and the host controls the
SDA line, except during the clock period when the device sends the device
acknowledgement signal to the bus.
13.Ina read protocol, datais sentto the busby the device and the host must release the
SDA line during the time that the deviceis providing data onto the bus and controlling
the SDA line, except during the clock period when the master sends the master
acknowledgement signal to the bus.
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
NXP Semiconductors SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
