SDA9290-5 ,Picture Processorblock diagram) is formed of the Image-lmproving Processor(IIP) and the Multi-Picture Processor (MPP ..
SDA9290-5 ,Picture ProcessorFeaturebox (3 TV-SAMs) can therefore be operated with 4:2:2 input signals as well.Semiconductor Gro ..
SDA9290-5GEG ,Picture ProcessorFeaturesl Noise and cross color reduction by field - or framerecursive filteringl 3 adjustments: 4- ..
SDA9290-6 ,Picture Processorblock diagram) is formed of the Image-lmprovingProcessor (IIP) and the Multi-Picture Processor (MPP ..
SDA9361 ,SDDC plusICs for Consumer ElectronicsDDC-PLUS-Deflection ControllerSDA 9361Data Sheet 1998-02-01Edition 1998 ..
SDA9361GEG ,SDDC plusCharacteristicsThe listed
SHA2410 , Very High Accuracy, Low Noise, Sample-and-Hold Amplifier
SHB105 , Supports unbuffered-ECC memory
SHC298JP ,Brown Corporation - Monolithic SAMPLE/HOLD AMPLIFIER
SHC298JP ,Brown Corporation - Monolithic SAMPLE/HOLD AMPLIFIER
SHC298JU ,Monolithic SAMPLE/HOLD AMPLIFIER
SHF-0186 , DC-12 GHz, 0.5 Watt AlGaAs/GaAs HFET
SDA9290-5-SDA9290-5GEG
Picture Processor
SIEMENS
Picture Processor SDA 9290-5
Preliminary Data NMOS IC
Features
o Noise and cross color reduction by field - or frame
recursive filtering
3 adjustments: 4-dB-, 7-dB- or 12-dB reduction
Automatic adaption to signal quality during vertical
blanking
Pixel adaptive movement detection
Split screen modes for demonstration purposes
Multi-picture facilities
Picture decimation using vertical filtering
8 programmable grey levels for framing
4:1 :1 and 4:2:2 (Y:U:V) compatibility
8-bit word size for all components
P-LCC-68-1
Type Ordering Code Package
SDA 9290-5 Q67100-H5088 P-LCC-68-1 (SMD)
Functional Description
The NMOS device SDA 9290-5 is a picture processor and belongs to a family of devices forming
an extended third-generation digital TV signal-processing system for enhanced picture quality with
special functions (Featurebox). Besides the Picture Processor (PP) that is described here, the
system consists of a field memory (at least three triple-port, I-Mbit generation TV Sequential-
Access Memory devices (SDA 9251 X), a Memory Sync Controller (MSC SDA 9220-5) and a Video
DIA converter (SDA 9094-5). A block diagram of the Featurebox is shown in figure 1.
The Picture Processor SDA 9290-5 is a follow-on development of the Picture Processor SDA 9090
from the second-generation Featurebox and permits further picture improvement by reducing the
video noise and cross-color interference. The SDA 9290-5 can be set independently at the picture-
signal input and output via the two pins FSBQ/FSI to the 4:1 :1 and 4:2:2 formats. A 4:1:1
Featurebox (3 TV-SAMs) can therefore be operated with 4:2:2 input signals as well.
Semiconductor Group 259 01.94
SIEMENS SDA 9290-5
The necessary decimation and interpolation operations are activated automatically when the format
is set. Together with a corresponding Memory Sync Controller (SDA 9220) it enables functions like
multi-picture, tuner scanning, picture-in-still and still-in-picture. The different modes can be
activated by a microcontroller on the PC Bus interface (slave receiver). The PC Bus address for
accessing the device is
0 0 1 0 1 0 1 0
Circuit Description
The core of the picture processor (see block diagram) is formed of the Image-Improving Processor
(HP) and the Multi-Picture Processor (MPP). The HP is responsible for noise and cross-color
reduction, while the MPP together with the new Memory Sync Controller implements the functions
multi-picture, tuner scanning, picture-in-still and still-in-picture.
Image-lmproving Processor
The signal inputs YIO-Yl7 and UVIO-UVI7 and the back-channel signal inputs YBO-YB7 and UVBO-
UVB7 picture data with 12 bits in quasi-parallel format (4:1:1) and with 16 bits in parallel format
(4:2:2). The clock rate for both signals is 13.5 MHz. For signal processing in the HP and MPP the
chrominance bit levels have to be separated in the case of the quasi parallel format by
demultiplexers DEMUXS and DEMUXR, these being largely identical in design.
A reduction in video noise is achieved by correlating the picture contents of two successive Mlds,
the non-correlated components (noise) being attenuated by the digital filter. To achieve this, the
instantaneous digital picture signal on the outputs of the demultiplexer DEMUXS and the picture
signal delayed by a field interval on the outputs of the back-channel demultiplexer DEMUXR are fed
to the HP and combined.
The signal-to-noise ratio (SW) unit detects the noise components of the input signals and the
movement detector uses this information to select an appropriate set of parameters with filter
coefficients and thresholds for the comparators. For this purpose the luminance signal is assigned
to one of three classes according to its S/N ratio, with each class defining a different degree of
maximum noise reduction. The limits between the middle class and the upper and lower classes
can be programmed by the PC Bus registers RI and R2 with the values for the thresholds SU and
SL. When the picture signals come from a video cassette recorder, the adaptation on the S/N ratio
of the input signal should be disabled by PL Bus register R0, VCR bit D2.
Measurement of the signal-to-noise ratio in the automatic mode has been advanced from line 7 to
line 6 in order to avoid conflicts with future text and data services.
The degree of noise reduction for the luminance and chrominance signals can be varied between
0 dB and 12 dB by selecting the appropriate filter coefficients.
A picture signal with reduced noise and cross-color appears on the output of the HP for further
processing. The signal will be forwarded via blocks MUXI and MUXO to the picture memories
through the outputs (YQO-YQ7 and UVQO-UVQ7 respectively).
The coefficients of the selected class are controlled by the movement detector as a function of
pixels to prevent artifacts (loss of focus) in moving parts of the picture.
Semiconductor Group 260
