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SDA9290-6
Picture Processor
SIEMENS
Picture Processor SDA 9290-6
Preliminary Data CMOS IC
Features
. Noise and cross color reduction by field - or frame
recursive filtering
q Adjustment of degree of noise reduction
. Automatic adaption to signal quality during vertical
blanking
q Pixel adaptive movement detection
. Split screen modes for demonstration purposes P-LCC-68-1
q Multi-picture facilities
q Picture decimation using vertical filtering
. 8 programmable grey levels for framing
q 4:1 :1 and 4:2:2 (Y:U:V) compatibility
q 8-bit word size for all components
. IIC-Bus programming of the video line for S/N
measurement in automatic adaption mode
q Optimized characteristics of the recursive filters
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Type Ordering Code Package
SDA 9290-6 Q67101-H5193 P-LCC-68-1 (SMD)
FunctionalDescription
The CMOS device SDA 9290-6 is a picture processor and belongs to a family of devices
forming an extended third-generation digital TV signal-processing system for enhanced
picture quality with special functions (Featurebox). Besides the Picture Processor (PP)
that is described here, the system consists of a field memory (at least three triple-port,
1-Mbit generation TV Sequential-Access Memory devices (SDA 9251 X), a Memory
Sync Controller (MSC SDA 9220-5) and a Display Prozessor (SDA 9280). A block
diagram of the Featurebox is shown in figure 4.
The Picture Processor SDA 9290-6 is a follow-on development of the Picture Processor
SDA 9290-5. Modifications of the movement detector and the recursive filters permits
further picture improvement by reducing the video noise and cross-color interference.
The SDA 9290-6 can be set independently at the picture-signal input and output via the
two pins FSBQ/FSI to the 4:1 :1 and 4:2:2 formats. A 4:1 :1 Featurebox (3 TV-SAMs) can
therefore be operated with 4:2:2 input signals as well.
Semiconductor Group 1 1997-07-22
SIEMENS SDA 9290-6
The necessary decimation and interpolation operations are activated automatically
when the format is set. Together with a corresponding Memory Sync Controller
(SDA 9220) it enables functions like multi-picture, tuner scanning, picture-in-still and
still-in-picture. The different modes can be activated by a microcontroller on the I2C-Bus
interface (slave receiver). The I2C-Bus address for accessing the device is
0 0 1 0 1 0 1 O
Circuit Description
The core of the picture processor (see block diagram) is formed of the lmage-lmproving
Processor (HP) and the Multi-Picture Processor (MPP). The HP is responsible for noise
and cross-color reduction, while the MPP together with the new Memory Sync Controller
implements the functions multi-picture, tuner scanning, picture-in-still and still-in-picture.
lmage-lmproving Processor
The signal inputs YlO-Yl7 and UVIO-UVI7 and the back-channel signal inputs YBO-YB7
and UVBO-UVB7 picture data with 12 bits in quasi-parallel format (4:1 :1) and with 16 bits
in parallel format (4:2:2). The clock rate for both signals is 13.5 MHz. For signal
processing in the HP and MPP the chrominance bit levels have to be separated in the
case of the quasi parallel format by demultiplexers DEMUXS and DEMUXR, these being
largely identical in design.
A reduction in video noise is achieved by correlating the picture contents of two
successive fields, the non-correlated components (noise) being attenuated by the digital
filter. To achieve this, the instantaneous digital picture signal on the outputs of the
demultiplexer DEMUXS and the picture signal delayed by a field interval on the outputs
of the back-channel demultiplexer DEMUXR are fed to the HP and combined.
The signal-to-noise ratio (Sh) unit detects the noise components of the input signals and
the movement detector uses this information to select an appropriate set of parameters
with filter coefficients and thresholds for the comparators. For this purpose the
luminance signal is assigned to one of three classes according to its S/N ratio, with each
class defining a different degree of maximum noise reduction. The limits between the
middle class and the upper and lower classes can be programmed by the IZC-Bus
registers RI and R2 with the values for the thresholds SU and SL. When the picture
signals come from a video cassette recorder, the adaptation on the S/N ratio of the input
signal should be disabled by ll-Bus register R0, VCR bit D2.
Measurement of the signal-to-noise ratio in the automatic mode has been advanced
from line 6 to line 4 in order to avoid conflicts with future text and data services.
The degree of noise reduction for the luminance and chrominance signals can be varied
between 0 dB and 12 dB by selecting the appropriate filter coefficients.
Semiconductor Group 2 1997-07-22
