SDA9253GEG ,2.6Mbit Dynamic Sequential Access Mem...Featuresl 212 · 64 · 16 · 12-bit organizationl Triple port architecturel One 16 · 12-bit input shif ..
SDA9254-2 ,Triple TV SAMFunctional DescriptionGeneralThe SDA 9254-2 is a combination of the TV-SAM SDA 9253 and an adaptive ..
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SDA9288X , Single Chip PIP System
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SH69P20 , SH69P20
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SDA9253-SDA9253GEG
2.6Mbit Dynamic Sequential Access Mem...
SIEMENS
2.6 MBit Dynamic Sequential Access Memory
for Television Applications (TV-SAM)
Preliminary Data
Features
00000 00000
212 M 64 x 16 M 12-bit organization
Triple port architecture
One 16 x 12-bit input shift register
Two 16 x 12-bit output shift registers
Shift registers independently and simultaneously
accessible
Continuous data flow even at maximum speed
40-MHz shift rate - 0.96-Gbit/s total data rate
All inputs and outputs TTL-compatible
Tristate outputs
Random access of groups of 16 M 12 bits for a wide range
of applications
Refresh-free operation possible
5 V i 10 % power supply
0 ... 70 °C operating temperature range
Low power dissipation: 700 mW active, 28 mW standby
Suitable for all common TV standards
Allows flicker and noise reduction simultaneously
with only one field memory
Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV
SDA 9253
CMOS IC
P-MQFP-64-1
Type Ordering Code
Package
SDA 9253 Q67101-H5171
P-MQFP-64-1
Semiconductor Group 1
SIEMENS SDA 9253
Functional Description
The SDA 9253 is a triple port 2605056 bit dynamic sequential-access memory for high-data-rate
video applications. It is organized as 212 rows by 64 columns by 16 arrays by 12 bit to allow for the
storage of 12-bit planes of a TV field (NTSC, PAL, SECAM, MAC) in standard or studio quality
(13.5-MHz basic sample rate) or 12-bit planes of parts of a HDTV field. The memory is fabricated
using the same CMOS technology used for 4-Mbit standard dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 12-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16 M 12-bit
input shift register C to an addressed location of the memory array and from the memory array to
one of the 16 M 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column
address (SAC) which contains the desired column address and an instruction code (mode bits) for
transfer and refresh.
Circuit Description
Memory Architecture
As shown in the block diagram, the TV-SAM comprises 192 memory arrays, which are accessed in
parallel. Each memory array has a size of 212 rows by 64 columns. The rows and columns of the
192 arrays can be randomly addressed, reading or writing 16 x 12 bits at a time. To obtain the
extremely high data rate at the 12-bit wide data input (SDC) and outputs (SQA, SQB), a parallel to
serial conversion is done using shift registers of 16-bit length and 12-bit width. In this way the
memory speed is increased by a factor of 16. (This is independent on the number of ports if the total
data rate is regarded.)
Independent operation of the serial input and the two serial outputs is guaranteed by using three
shift registers. The decoupling from the common 16 x 12-bit memory data bus is done by three
latches which allow a flexible memory timing and a flying real-time data transfer.
A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at
maximum clock speed.
To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row
address and a serial 8-bit column address which includes two mode control bits. The serial row and
column addresses are converted to parallel addresses internally, then latched and fed to the row
and column decoders. The internal memory controller is responsible for the timing of the memory
read/write access and the refresh operation.
Semiconductor Group 2 1998-01-30
