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SDA9220-5 |SDA92205InfineonN/a3100avaiMemory Sync Controller
SDA9220-5GEG |SDA92205GEGSIEMENSN/a1400avaiMemory Sync Controller


SDA9220-5 ,Memory Sync ControllerFeaturebox is possible in conjunction with the signal MUXsupplied by the MSC III.Other major output ..
SDA9220-5GEG ,Memory Sync ControllerFeatures● Large area flicker elimination through field doubling● Additional elimination of interlin ..
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SH69P20 , SH69P20
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SHB105 , Supports unbuffered-ECC memory


SDA9220-5-SDA9220-5GEG
Memory Sync Controller
SIEMENS
Memory Sync Controller Ill SDA 9220-5
Preliminary Data MOS IC
Features
0 Large area flicker elimination through field doubling
0 Additional elimination of interline flicker in field mode
o Field switching and selection in field mode
0 Noise and cross-color reduction
0 Stills
o 9-image display, still-in-picture, picture-in-still
with different frame versions
0 Zoom with selection of enlarged picture segment P-LCC-44-1
(8 x 12 positions)
o Pin-programmable operation without standard
conversion
Type Ordering Code Package
SDA 9220-5 Q67100-H5087 P-LCC-44-1 (SMD)
Functional Description
The MSC III is a component of the TV-SAM Featurebox and is responsible for driving the picture
memory devices (TV-SAMs) and generating sync signals (figure 6). Together with the other
devices of the Featurebox it enhances picture quality and offers a number of special operating
modes.
The MSC III is set via the PC Bus, it being possible to switch the PC Bus address by hardware so
that implementation of a simple frame Featurebox is possible in conjunction with the signal MUX
supplied by the MSC Ill.
Other major output signals of the SDA 9220-5, in addition to the clocks LL3X (13.5 MHz) and LL1.5X
(27 MHz), are the memory-driving signals (a, W, W, E, SCAD, SCA) and the sync signal CSY
for the teletext device. The horizontal sync signals (HS2, BLN2) and the vertical sync signals (V81,
VS2) are also generated.
Semiconductor Group 117 01.94
SIEMENS SDA 9220-5
Circuit Description
The MSC Ill can be divided into the following function blocks (figure 6):
- Sync-signalgenerator
- Memory controller
- Clock generator
- PC Bus receiver
The sync-signal generator uses signals VS and BLN to produce the horizontal and vertical sync
signals BLN2, HS2, VS1 and V82. It supplies the composite sync signal CSY for the 100-Hz
teletext, the control signal MUX for implementing a simple frame Featurebox and the frame signal
FRM for inserting a colored frame in multi-picture, still-in-picture and picture-in-still modes. Signal
CFH is output to prevent the bottom flutter effect in the video cassette recorder mode.
In operation without standard conversion (pin-programmable) signals BLN2, V82 and FRM are
switched from double to single line/field frequency. Outputs CSY and HS2 are not required in this
The memory controller produces the driving signals (m, E, W, E) and the addresses (SAR,
SAC) for the memory devices (TV-SAMs). In addition, it produces the DREQ pulses used for
requesting data from the picture processor during operation with reduced pictures. Two refresh
operations are performed in the memory for each TV line.
The clock generator consists essentially of a PLL which generates the internal and exported system
clocks from input clock LL3 or LL1.5 and synchronizes them with the horizontal blanking signal. The
MSC can be set to one of the two input frequencies via input LLSEL. For the possible use of the
Featurebox as a channel scanner, the PLL incorporates a crystal-controlled reference clock to
ensure an undisturbed clock supply for memory output (stills sequence) during channel-switching
phases.
All modes (except switching off the standard conversion) are set by appropriate programming of the
PC Bus data bytes. When the operating voltage is switched on, all bits of the associated control
registers are set to 0. The address of the 12C Bus is set with signal ADR (24H or 26H).
Semiconductor Group 118
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