SCX6206 ,Equivalent 2-input gate 600, microCMOS gate array family application guideElectrical Characteristics ..................... 4
3.0 Topology and Routing Resource Distributio ..
SCZH-002T-P0.5 , Crimping tools and machines
SD03H0K , Low Profile DIP Switches
SD05C , Single Line TVS Diode for ESD Protection in Portable Electronics
SD05C , Single Line TVS Diode for ESD Protection in Portable Electronics
SD05C , Single Line TVS Diode for ESD Protection in Portable Electronics
SG6516DZ , PC Power Supply Supervisors
SG6520DZ , PC Power Supply Supervisors
SG6741ASZ , Highly Integrated Green-Mode PWM Controller
SG6741ASZ , Highly Integrated Green-Mode PWM Controller
SG6741ASZ , Highly Integrated Green-Mode PWM Controller
SG6742HLSY , Highly Integrated Green-Mode PWM Controller
SCX6206
Equivalent 2-input gate 600, microCMOS gate array family application guide
National Jaws
SCX m icroCMOS Gate Array Family Application Guide
TABLE OF CONTENTS
1.0 General Description ............................ 2
2.0 Product Features ............................... 2
2.0.1 Enhanced Product Features .................... 2
2.1 microCMOS Process and Circuit Personalization. . . . 3
2.2 Gate Array Basic Cell ........................... 3
2.3 Power Dissipation .............................. 3
2.4 Absolute Maximum Ratings ...................... 4
2.5 Recommended Operating Conditions ............. 4
2.6 DC Electrical Characteristics ..................... 4
2.7 AC Electrical Characteristics ..................... 4
3.0 Topology and Routing Resource Distribution ....... 5
SCX6206 (600) ............................. 5
SCX6212 (1.2k) ............................. 5
SCX6218 (1 .8k) ............................. 5
SCX6225 (2.5K) ............................. 5
SCX6232 (3.2K) ............................. 6
SCX§244 (4.4k) ............................. 6
4.0 On-Chip Test Circuitry ........................... 6
b 5.0 Macros ....................................... 6
k 5.1 Hardware Macros .............................. 6
5.2 Peripheral Macros .............................. 8
L 6.0 Software Macros ............................... 8
6.1 Software Macros (User Generated) ............... 8
c, 7.0 Packaging ..................................... 10
8.0 Propagation Delays ............................. 11
9.0 Design Automation System ...................... 13
9.5 Workstation Support ............................ 14
10.0 Design Example ............................... 16
10.1 Text Mode .................................... 17
10.2 Workstation Mode ............................. 19
10.3 Pattern File ................................... 21
10.4 Simulator Output .............................. 21
1 1.0 Alternative Interfaces .......................... 22
12.0 Training and Technical Services ................. 22
13.0 Technology Centers ........................... 22
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1.0 General Description
National Semiconductor':; CMOS gate array Family utilizes a
dual layer metal technology (microCMOS) to achieve oper-
ating speeds similar to Schottky-TTL with the inherent lower
power consumption ot standard CMOS integrated circuits.
The SCX6200-Series Family is available in 2-micron drawn
geometry with a 1.4 micron effective channel length. The
range of complexity is currently from 600 to 6000 gates. The
gates are arranged in cells. Each cell has the equivalent of
three 2-input NAND or NOR gates. All outputs have the abil-
ity to drive 10 LSTTL loads. All inputs have high noise immu-
nity and are protected from static discharge.
National Semiconductor supports gate array designs with a
variety of user/vendor interfaces. This ranges from produc-
ing arrays from the user's schematic to accepting data-
bases for mask generation. A large dedicated staff of gate
array professionals is available to help the user determine
the most efficient and cost effective way to interface on any
given design.
The design automation tools include workstation or text file
entry (for schematic capture), logic and timing veritiers to
substantiate the actual design, fault grading analysis to
gauge testability and a large selection of macros (hardware
and software) to speed and simplify the design.
2.0 Product Features
I Latch-up proof, state-of-the-art 2-micron (drawn) dual-
metal silicon-gate microCMOS technology
I Ultra-high performance-l ns typical gate delays
I Available from 600 gates to 6000 gates
I CMOS power dissipation
I All inputs and IIOs protected from over-voltage and latch,
I Full design automation support
- Schematic capture
- Logic simulator with timing information
- Fault grading
I Multiple power rail pin connections
I Multiple packaging options in ceramic, plastic, leaded and
leadless
I Pin counts to 172
I Military performance
I Alternately sourced
I Complete hardware/software macrocell libraries
I On-chip self-test capability (6.0K only)
I 100% auto-place-and-route at 90% utilization
I Design automation system supported on mainframe and
workstations
2.0.1 Enhanced Product Features
The SCX6200-seritm gate array family is available in seven
device increments from 600 to 6000 gates. The initial mem-
bers of the 2-micron family consist of SCX6212, 6225 and
6260. Today it has been enhanced and expanded to include
the 6244, 6232, 6218 and 6206. These enhanced devices
contain several new features as follows:
. Flexible l/O Structure - The l/O buffer has been en-
hanced to handle multiple tunctions including:
--Low-drhm inputs compatible with TTL, CMOS or
Schmitt Trigger
- High-drive (Clock Driver) inputs compatible with TTL,
CMOS or Schmitt Trigger
- Output compatible with TTL and CMOS and configura-
ble as TRI-STATE? non TRI-STATE or Open Drain
- Outputs selectable for 1, 2 or 4 mA drive
- Bidirectional inputs/outputs
- Oscillator macros to drive I, 2 or 4 mA
--Separate power supply traces for output drivers im-
prove noise immunity
The input capacitance loading of the output drivers has also
been reduced to enhance the overall circuit performance.
. Selectable Output Drive Capability - The enhanced I/O
structure now makes it possible to offer a variety of output
drives for any given I/O location. Through implementation
of l/O macro options, users can select their output drives
in I, 2 or 4 mA for each output buffer.
Parallel I/O Butters for High Drives " By means ot spe-
cial I/O macros, output drive current in excess of 4 mA
can be achieved by paralleling l/O buffers without losing
the input functions. For example, to achieve 24 mA, six
4 mA I/O buffers need to be paralleled up; through use of
the special macros, one pin is needed to implement the
output which can be bidirectional while 5 pins can still be
used as inputs.
Dedicated Multiplexed D-FIip/Flops - Incorporated into
the internal array core is a number at dedicated multi-
plexed D-tlip/flops. These flip/flops have been designed
to achieve significant system speed improvement over a
logically eqivaient macro function while minimizing silicon
space to implement. They are ideal for scan path design
techniques as well as registers and counters.
Array Equivalent I up ut Cells l/O Signal Test VPD yss
Name 2-lnput Gateimotg) Cells Pins Pin Pins Pins
SCX6206 600 8 40 48 1 4 4
SCX6212 1260 17 42 59 1 4 4
SCX6218 1806 3 7O 73 1 8 8
SCX6225 2430 12 76 88 1 6 6
SCX6232 3162 3 101 104 1 8 B
SCX6244 4380 3 110 113 1 8 8
SCX6260 (Note 2) 6090 66 88 154 6 8 8
Note 1: Input and HG cells are not considered part of the internal cell count.
Note 2: Advanced Architecture with additional 2500 gates tor on-chip self-test capability.
METAL 1 EAPPED
ttt CONTACTS
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FIGURE 1. Cell
2.1 microCMOS PROCESS AND CIRCUIT
PERSONALIZATION
The microCMOS process developed by National is based
on P-type starting material, N-well technology and oxide iso-
lation. After the basic transistors are formed (in their respec-
tive cells), two separate layers of metalization (M1 and M2)
are placed on the wafers.
The processing steps and tooling requirements for all the
waters up to " metal layers are common and fixed. Circuit
patterns-called "options''-" defined by the two metal
layers and the VlAs. In this way, the user's design (or circuit
personality) is imposed on the water.
All SCX gate arrays in the family use the same basic internal
cell. There are eight pairs of N and P-type MOS transistors
in each cell (see Figure 1). The power and ground lines
(VDD and vss buses, respectively) run up and down the cell.
This cell is repeated in all four directions to form columns
and rows in the core of the array. The structure of the inter-
nal core is optimized to the size of each family member.
National Semiconductor maintains an inventory of gate ar-
ray wafers fabricated up to but before metalization. As the
customer's options are designed and the last three patterns
finalized, wafers are taken out of inventory and the fabrica-
tion process completed for the metal layers.
ln this way, National Semiconductor can provide gate array
users with quick tum-around cost effective designs while
maintaining the quality, reliability and production control of
an in-house (4 and 6-inch) water fab line.
2.2 GATE ARRAY BASIC CELL
Figure , shows the basic internal cell. The geometries are
not drawn to scale and the exact topology has been modi-
fied for illustration purposes.
2.3 POWER DISSIPATION
An outstanding feature of microCMOS circuits is their low
power dissipation. CMOS circuits draw electrical current for
basically two reasons:
(1) During transition from a logic "O" to a logic "I" or vice
versa, there exists a finite time when the P-channel and N-
channel devices associated with the logic element are both
conducting. The CMOS circuit consumes power during this
transition.
(2) When signals change state, the distributed capacitance
in the circuit (and its load) need to be either charged or
discharged. The electrical current required for this purpose
increases power consumption.
Thus, power dissipation is dependent on operating voltage,
nodal capacitance and the frequency of circuit operation.
Mathematically speaking:
Po = CV2F
For estimation purposes, the value of:
25 pW/gate/MHz per gate equivalent can be used for ele-
ments within the array.
700 pW/MHz/output butter at 15 pF load or 1500 pW/
MHz/output at 50 pF load, can be used for the output buff-
Power dissipation in a CMOS array is typically dominated by
output buffers driving large capacitive loads.
Figure 2will help in estimating power consumption in a par-
ticular design.
c=so " l/O
c=1s pr
N c=3 pF
g INTERNAL w:
d? -1 "
i1tll2030405060r0
MHI TL/U/5725-3
FIGURE 2. Power Consumption " Frequency
2.4 ABSOLUTE MAXIMUM RATINGS
2.5 RECOMMENDED OPERATING CONDWIONS
Exceeding the following absolute maximum ratings may re-
sult in permanent damage to the device.
VDD, Supply Voltage
Vi, vo, Input or Output Voltage vss
Supply Voltage _ 0.5V to 7V ks High or Low Level Output
Input or Output Voltage - 0.5V to VDD + 0.5V Current
Storage Temperature - 65°C to 150''C IDD, V00 or VSS Current per Pad 0
Power Dissipation (Package Dependent) 1W TA, Ambient Operating
Lead Temp. (Soldering, 10 seconds) 300°C Temperature
2.6 DC ELECTRICAL CHARACTERISTICS
Max Units
i 25 mA
i 50 mA
+ 85 ''C
VDD = 5V t 10%, min/max limits apply over recommended operating temperature range unless otherwise specified.
Symbol Parameter Conditions Min Max Units
" High Level InputVoltage vo = 0.5V or VDD - IV, Io = 1 PA 0.7 VDD V
" Low Level Input Voltage V0 = 0.5V or VDD - IV, IO = 1 ”A 0.3 I/ron V
VOH High Level outputVoltage V. = VDD or GND, Io = 1 pA VDD -0.05 V
VOL Low Level Output Voltage V. = VDD orGND, IO = t HA 0.05 V
IOH High Level OutputCurrent Vl = VDD or GND, Vo = VDD -- 0.8V - 4 mA
lot. Low Level OutputCurrent V. = VDD or GND, Vo = 0.4V 4 mA
VIHTTL Min. High Level TTL l/P Voltage vo = 0.5V or VDD - IV, Io = 1 pA 2 V
(for TTL Input Option)
VILTTL Max. Low Level TTL l/P Voltage Vo = 0.5V or VDD - IV, IO = 1 “A 0.8 V
(for TTL Input Option)
I, Input Current (Without Pull-Up Resistor) V. = VDD or GND i 1 pA
'00 Supply Current V. = VDD or GND, TA = 25°C 100 MA
2.7 AC ELECTRICAL CHARACTERISTICS VDD = 5V, TA = 25''C, 2,. process.
Symbol Parameter Min Max Units
tpLH Output Buffer 1.1 3.5 ns
tPHL (Non-Inverting, non-TRI-STATE) 1.2 4.2 ns
tr = tt = 5 ns,0V--5V
CL = 15 pF
tpLH Input Buffer 0.75 2.95 ns
tPHL (TTL Type, Non-lnverting) 1.10 3.2 ns
at tr = tf = 5 ns, OV-AW
CL = 1 pF
tpLH Input Buffer 0.55 1.75 ns
tPHL (CMOS Type, Inverting) 0.50 1.40 ns
attt = tf = 5 ns,0V-5V
CL = 1 pF
tpLH Output TRI-STATE 1.9 6.0 ns
tpHL (Non-lnverting) 2.5 6.8 ns
tPZL at tr = If = 5 ns 2.8 7.8 ns
tPZH OV-SV 1.9 6.0 ns
tpLz CL = 50 pF 7.2 8.3 ns
tsz RL = 1 kn. 7.0 8.2 ns
Delays Measured at 50 % ns
Point Between Start and
Target Voltage
tPLH Internal 2-lnpul NAND 0.4 1.55 ns
tpHL at tr = t, = 5 ns, ov-w 0.8 2.30 ns
tPHL Load Equivalent to Fan-Out of 0.20 0.75 ns
tpLH 3 and 100 mils of Interconnect 0.15 0.55 ns
As Above with CL = 0 pF
3.0 Topology and Routing
Resource Distribution
The specific topology and routing resource distribution have
been tailored for each family member. Architectural consid-
erations include the ratio of inputs and I/Os to total cell
count, power consumption and package inductance to pow-
6206 Die Structure
LL 4.]
10 l/O’S
vss: q F vss
VDDE 'r" 8 COLUMNS ----rel Wh)
II l c-s- - ="f, II
I/OS T - 10 F/F = I/O'S
MOD POWER sl. - - - VDDE
J b vss:
RESEI 8 l/O'S
TL/U/5725-4
6218 Die Structure
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l8 l/O'S
q l F van
(i---" COLUMNS -I 7 GND
V03 ='-10-r/r = = I/0'S
l A - -
GND POWER 0N tmo
V00 El MOD
I -tti I/O'S ------ RESET
m Ial In] UI
D a O O
Ch 2 2 D
> o to >
TL/U/5725-6
er pins (tor simultaneous switching outputs) and routing re-
sources consistant with automatic place and route software.
Internal cell utilizations of greater than 85% can be expected.
Individual topologies and a family summary follow.
6212 Die Structure
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6225 Die Structure
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6232 Die Structure
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vss l F van
I---17 COLUMNS --e) vss
t ','2
1- lo- F/F = =
25 I d 26
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T 10- F/F = r...-..
'A' m'
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25 we RESET
Lulu] Lag Lad
DUI VI 8
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TL/U/5725-8
4.0 On-Chip Test Circuitry
Each of the SCX gate arrays is provided with dedicated on-
chip test circuitry. This circuitry forces all the outputs to spe-
cific states to facilitate output parametric testing. These
parametric tests include leakage and current sourcing/sink-
ing measurements on all output pins.
The on-chip test circuitry is enabled by a dedicated test
mode control (TMC) pin. This pin is set aside for testing and
cannot be used for any other purpose on the 6212 and
6225. However, for the enhanced devices (6244, 6232,
6218 and 6206), the extra TMC pin can be avoided by
means of an internal TMC decoding circuit of the user's
design. In addition, an optional internal control signal de-
rived from the TMC pin is now available. This can be used,
for example, as a set or reset control signal to the internal
logic.
The self-test capability has been further expanded and en-
hanced on the 6k-gate 6260. It has an additional 2,500
gates dedicated to provide an on-chip maintenance system
that includes chip selt-test, system interconnect-test, logic
analyzer, and system check-sum modes. This self-test tea-
ture on the 6260 is unique from the rest of the SCX family as
well as in the industry. A low at this input will activate the on-
chip test circuitry. When the on-chip test circuitry is activat-
ed, the states of all outputs are determined by two other
inputs; these are TRI-STATE test control (TSTC) and data
test (DT). The TSTC and DT can share input pins with the
user's design. They are only active when the TMC is en-
abled. The TSTC input has precedence over the DT input.
The TMC input is active for the following discussion.
When the TSTC input is active, all the output buffers are put
into a high impedance mode. When TSTC is not active, the
states of the output buffers are determined by the DT input.
These two inputs can be assigned to any of the input pins.
6244 Die Strueture
UI tad ug L41
ca cu V) (DC)
0 o m (n o
> ' ' ' '
I I l _ I I
27 l/O‘S -----
VDD q l F van
vss I 20 egg MNS ---I vss
=--io-r/r : LT
27 'g 29
I/0'S 'd l/O'S
'i-IO-r/F = LT,
VSS - - 750m: 0N VSS
V00 D VDD
( ---27 I/O'S --- RESET
lad Lu ug LO
Q Mt m D
O Mt V) O
' ' ' >
TL/U/5725-9
On-Chip Test Circuitry Truth Table
TMC DT TSTC Output
0 X Active TRI-STATE
0 Non-Active Non-Active 1
0 Active Non-Active 0
Definition of Test Input States
Non-trwerting Inverting
Macros Macros
Non-Active 0 1
Active 1 0
5.0 Macros
Three types of macros are available for designers to use:
hardware macros, software macros (National Semiconduc-
tor standard library), and user generated software macros.
5.1 HARDWARE MACROS
The SCX family of gate arrays offers an extensive library of
hardware macros (Table l). Each macro has been fully char-
acterized and functionally proven. The designer can select
those macros that most efficiently implement the design.
The electrical performance of the macros is characterized
at two sets of conditions: best and worst-case. Under each
set of conditions, the output loading is specified at 0 pF and
1.0 pF. The 1.0 pF load is equivalent to a fan-out of 3 and
includes 100 mils length of metal interconnect. A single in-
put load is equivalent to 0.13 pF and is defined as a load
factor of 1.
National Semiconductor has very tight wafer fabrication
guidelines. However, process parameters still do vary from
water-to-water, lot-to-Iot. The electrical specifications of the
macros take into account such variations.
TABLE I. Table of Macros
Function Macro Name Function Macro Name
GATES LATCHES
Triple 2-Input NAND 0001 (S1) NAND R/S Latch with 2-lnput NAND C012 (S12)
Dual 3-input NAND C002 (S2) NOR R/S Latch with 2-lnput NOR C013 (S13)
Dual 2-Input NAND/AND C003 (S3) D-Latch with Set/Reset C062 (Di 1)
Triple 2-lnput NOR C004 (S4) (1:) -Bit Irazsgaregt D-Latch with C026 (D 1 2)
Dual 3-Input NOR C005 (S5) ese an na e
Dual 2-Input NOR/OR C006 (S6) Triple R/S NAND Latch C027 (07)
Single 2-lnput Exclusive-OR C053 (S53) Triple R/S NOR Latch C031 (D8)
2-lnput 2-Wide OR-NAND C014 ($1 4) FLIP-FLW'
with Complement D Flip-Flop C023 (D9)
2-Input 2-Wide AND-NOR D Flip-Flop with Set and Reset C024 (T1)
ithC I t C015 (S15)
WI Wtlp emen D Flip-Flop with Reset and Parallel Load C034 (04)
Triple 4-lnput NAND C017 (DI) D Flip-Flop with Set/Reset Master Slave C051 (T3)
Single 5-lnput NAND (2X) C01 8 (D2) D Flip-Flop with Set/Reset Buffered C060 (T60)
Triple 3-lnput NAND with Complement C019 (D3) D Flip-Flop with Reset (Q Output Only) C064 (064)
Triple 4-lnput NOR C020 (D4) Multiplexed D Flip-Flop with Reset C035 (035)
Single 5-lnput NOR (2X) C021 (D5) J-K Flip-Flop with Reset and Set 0037 (F37)
Triple 3-lnput NOR with Complement C022 (D6) J-K Flip-Flop with Set/Reset Master Slave 0052 (02)
4-lnput Exclusive-OR C046 (T2) T Flip-Flop with Inverter Reset C036 (06)
3-input Exclusive-OR C047 (D10) T Flip-Flop with Reset C861 (0861)
Single 2-Input Extgusive-NOR C048 (S21) REGISTERS AND COUNTERS
5-lnput NAND-AND C057 (D57) 2-Bit Serial In/Out and Parallel C039 (F1)
5-Input NOR-OR C058 (D58) Out Shift Register
3-Input Exclusive-NOR C800 (D800) 2-Bit Serial/Parallel Shift Register C042 (H4)
6-input AND/NAND C830 (D830) Universal Shift Register State C194 (F194)
8-Input OR/NOR C878 (D878) Up-Down Counter Stage with Parallel Load C038 (F2)
BUFFERS 4-Bit Binary Counter Control Logic C871 (0871)
Triple 2X Buffer COO? (S7) MULTIPLEXER & DEMULTIPLEXER
Quad Inverter C008 (S8) 'l/tl, Igultitplelfer Vizlth C056 (S5 6)
Dual THI-STATE Inverting Butter C009 (S9) Ing t) On ro npu
Single Non-lnverting TPI-STATE Buffer C010 (S10) tttl. TRI-STATE Multiplexer C028 (T4)
with Enable Low
Schmitt Trigger C025 (S24) . .
4-to-1 Multiplexer with C029 (T5)
Quad Inverter Buffer C043 (S20) Complement Output
Dual Triple Inverter Buffer C044 (S19) 1-to-4 Decoder with Active Low
C033 (03)
1-3 Buffer C045 (S22) Outputs and Enable Input
3-1 Buffer C061 (S23) 3-to-8 Decoder C138 (H138)
2-2 Buffer C049 (S18) 8-Channel Digital Multiplexer C151 (H151)
4-Input Exclusive-OR Buffer (2X) C801 (T801) Quad 2-Input Multiplexer C158 (0158)
Quad Pulldown with Common Enable C808 (S808) Quad 2-Channel TRI-STATE C257 (0257)
Quad Pulldown with
6-Input Enable Decode
C811 (D811)
Multiplexer
Quad Pullup with 6-lnput Enable Decode
C812 (D812)
Quad Pullup with Common Enable
C832 (S832)
TABLE L Table of Macros (Continued)
Function Macro Name Functlon Macro Name
ARITHMETIC FUNCTIONS INPUTS AND OUTPUTS
4-Bit Parity Checker C030 (T6) Inputs Only (36) See " Macro Table
1-Bit Full Adder C032 (T7) Outputs Only (9) See " Macro Table
1-Bit ALU with 7 Functions C040 (H2) Bidirectional (72) See IIO Macro Table
2-Bit Magnitude Comparator C041 (H3) Oscillator Macros (3) See IIO Macro Table
Notes on Macro Name
Note 1: Cell Count S = 1 cell (3 gates)
D _ 2 cells (6 gates)
T 2 3 cells (9 gates)
0 = 4 cells (12 gates)
F = 5 cells (15 gates)
H = 6 cells (18 gates)
Note 2; The 'C000' designator is a common reference used between National Semiconductor and its alternate source for the purpose ot consistency with users.
TABLE II. vo Macro Table
Input Drive Output Drive Each Capable of
I/O Macro Type Input Macro Output Macro
1X 7X 15X 1 mA 2 mA 4 mA V D
Input Only TTL X X X X X X
(36 Macros) CMOS (INV) X X X X X X
CMOS (NINV) X X X X X X
Schmitt X X X X X X
Output Only NINV X X X
(9 Macros) INV X X X
Open Drain X X X
Bidirectional TTL NINV X X X X X X X
(72 Macros) CMOS (INV) NINV X X X X X X X
CMOS (NINV) NINV X X X X X X X
Schmitt NINV X X X X X X X
TTL INV X X X X X X X
CMOS (INV) INV X X X X X X X
CMOS (NINV) INV X X X X X X X
Schmitt lNV X X X x X X X
Oscillator (3 Macros) X X X
V = PutI-Up; D = Pull-Down; N = Neither Pull-Up nor Pull-Down
5.2 PERIPHERAL MACROS
Interfacing to the SCX gate arrays is done through the pe-
ripheral buffers. There are two types of peripheral cells; in-
put only and bi-directional I/O cells (Table II). The peripheral
macros are not included in the count of internally available
cells.
The buffers are located around the periphery of the die and
the exact configuration is dependent on the particular family
member under consideration. Reference section 3 for spe-
cific tocations of input and (lo cells.
6.0 Software Macros
In addition to the pre-designed hardware macros, National
Semiconductor offers a library of software macros. These
software macros emulate the functions of the popular 7400
and 4000 logic families. From the designer's vantage point,
these software macros are utilized as though they were
hardware macros. The actual implementation of these high-
er order functions is handled by the design automation tools
in a process that virtually expands the software macro into
its hardware macro primitives.
Since the software macros reside in the design automation
system, a designer may copy a software macro into his de-
sign, modify it to meet some special consideration, rename
it, then reference it as a special or new software macro. This
procedure is coordinated with National's Technology Cen-
National Semiconductor adds popular software macros to
the existing library as required to meet user needs.
A representative list is shown in Table III. The cell count is a
'will not exceed' number, unused portions of cells are avail-
able for use in unrelated portions of the design.
6.1 SOFTWARE MACROS (USER GENERATED)
The user always has the option ot generating higher order
software macros. This is true regardless of where the user
decides to interface with the design automation system.
At the workstation level, the user simply creates the desired
function from existing hardware macros, stores the function
under a unique identifier name, then recalls it as a block of
logic as required.
In the text file mode of schematic capture the user defines
the higher order function in terms of the basic hardware
macros. These higher order (custom) functions are then
'called' in the same manner as any other software macro.
Device Count
7400 1.3
7402 1.3
7403 1.3
7404 1.5
7405 1.5
7406 2.0
7407 6.0
7408 2.0
7409 2.0
7410 IS
7411 2.0
7412 1.5
7414 6.0
7415 1.5
7416 2.0
7417 4.il
7420 1.3
7421 1.3
7422 1.3
7425 3.3
7426 1.33
7427 1.5
7428 33
7430 2.0
7432 1.3
7433 3.3
7437 3.3
7438 33
7440 2.0
7442 7.6
7443 7.6
7444 7.6
7445 7.6
7446 17,0
7447 17.0
7448 17.0
7451 2.0
7458 2.0
7464 3.3
7465 3.3
7470 6.0
7471 6.7
7472 6.8
7473 8.0
7474 6.0
7475 4.5
7476 8.0
7477 4.5
7478 8.0
7483 12.0
7485 120
7486 4.0
7489 84.0
7490 13.0
7491 17.0
7492 139
7493 13.0
7494 13.0
Dmtlee
TABLE III. Software Macros
Count Deelee
Deglce
7.0 Packaging
The SCX family of microCMOS gate arrays is offered in a
very wide variety of packages. The user is provided with
many choices in terms of both package type and lead count.
The package types offered include ceramic pin grid arrays
(PGA), leaded ceramic chip carriers (LDCC), leadless ce-
ramic chip carriers (LCC), plastic leaded chip carriers (PCC),
ceramic DIPs, and plastic DIPs.
The availability of such a large variety of packages gives the
user flexibility in making the following choices:
--Ceramic versus plastic
-Through-hole mount versus surface mount
The specific packages offered are listed in Table lVa.
Surface mounting of multi-lead components is rapidly gain-
ing popularity. To provide the user flexibility, National Semi-
conductor offers its CMOS gate arrays in several surface
mount package options: leaded and leadless ceramic chip
carrier and the plastic leaded chip carrier.
Surface mounting refers to component attachment, where-
by the component leads or pads rest on the surface of the
PCB instead of the traditional approach of inserting the
leads into through-holes which go through the board. With
surface mounting there are solder pads on the PCB which
align with the leads or pads on the component. The result-
ing solder joint forms both the mechanical and electrical
connections.
The primary reason for surface mounting is to allow leads to
be placed closer together than the 0.100 inch standard tor
DlPs with through-hole mounting. Through-hole mounting
on smaller than 0.100 inch space is difficult to achieve in
production and is generally avoided. The move to 0.050
inch lead spacing offered with the current generation of sur-
tace mounted components, along with a switch from a dual-
in-line format to a quad format, has achieved a threefold
increase in component mounting density. A need to achieve
greater density is a major driving force in today's market-
Learning how to surface mount components to printed cir-
cuit boards requires the user to implement an assembly
process not typically associated with through-hole inser-
tion/wave soldering assembly methods.
Surface mounting involves three basic process steps:
1) Application of solder or solder paste to the printed circuit
2) Positioning of the component onto the printed circuit
3) Retlowing of the solder or solder paste.
Table lVb lists the manufacturers currently offering sockets
for each of the advanced package options listed in this data
sheet. A matrix of which manufacturers to contact for each
socket option is provided. The listing is divided into test/
burn-in and production categories. There may be some indi-
vidual sockets that will cover both requirements.
TABLE lVa. Gate Array Package Options
Package Type Pins 6206 6212 6218 6225 6232 6244 6260
Plastic DIP, N 20 X
28 X X X X
40 X X X X X X
48 X X X X X X
Ceramic DIP, D 20 X
(Side Braze) 28 X X X X
40 X X X X X X
48 X X X X X X
Plastic Leaded 28 X X X X
Chip Carrier, PCC 44 X X X X X X
68 X X X X X
84 X X X X
124 X X X
Ceramic Leaded 124 X X X X
Chip Carrier, LDCC
Ceramic Leadless 28 X X X X
Chip Carrier, LCC 44 X X X X X
68 X X X X X
84 X X X X
124 X X X X
Ceramic Pin 68 X X X X X
Grid Array, PGA 84 X X X X
124 X X X X
TABLE lVb. Socket Vendors
Vendor Location and Telephone
_ Amp Inc. Textool
Package Type Test/Burn-ln Production Harrisburg, PA Irving, TX
Ceramic Pin Grid Array Amp, Textool, Amp, Yamaichi (715) 564-0100 (214) 259-2678
Yamaichi, Thomas Thomas & Betts Plaslrogics ghomas S'"
Irving, X aritan.
8 Betts (214) 258-1906 (210) 469-4000
Leaded Ceramic Chip Carrier Yamaichi Yamaichi Robinson/Nugent Yamaicm
. . . . . New Albany, IN c/o Napenthe Dist,
Leadless Ceramic Chip Carrier Amp, Plastronics, Amp, Plastronics (812) 945-021 1 Palo Alto, CA
Textool (415) 856-9332
Burndy
Plastic Chip Carrier Textool Amp, Burndy, Norwalk, CT
Robi nson I Nugent (203) 333-4444
8.0 Propagation Delays
Propagation delays in CMOS arrays are a function of sever-
al factors:
. Supply voltage
q Junction temperature
. Process tolerance
q Fan-out loading
. Interconnection routing
q Input signal direction
To assist the designer in evaluating circuit performance un-
der all operating conditions, National Semiconductor guar-
antees DC and AC parametrics over the full voltage and
temperature range, as well as best-case and worst-case
propagation delays. Process tolerance is included in the
specifications.
Delays other than three for fan-out loading may be extrapo-
lated for loads other than shown.
For example: a 2-input NAND (SI) drives six loads. What is
the worst-case LO to HI delay?
From Table V
tpLH for 0 pF = 0.75 ns (0 loads)
tpLH for1 pF = 2.40 ns (3 loads)
The delay perload = 2.40 - 0.75)/3 = 0.55 ns
Total delay = base delay(0 load) + sixloads
4.05 ns = 0.75 ns + 6 (0.55 ns)
What is the delay if the power supply is maintained at 5V
and junction temperature is 80''C (approximately 65''C ambi-
PROPAGATION DELAY RELATIVE TO TEMPERATURE
-40 025
TO as 100
IEMPERATURE Ctl TL/U/5725-10
FIGURE 3. CMOS Propagation Delays
as a Function of Temperature
From scaling factors (Table N note):
Worst-case junction temperature = 100''C
New junction temperature = 80''C
"C (100°C - 80°C) = 6%
Worst-case voltage ' 4.5V
New voltage = 5.0V
Improvement factor =
Improvement factor = 07:! (5.0V - 4.5V) = 10%
Derating factor = (1 _ 0.06)(1 - 0.1) = O.846
Totaldelay(scaled) = 4.05(D.846) = 3.43 ns
This form of calculation is handy for making estimates of
critical paths during the initial design phase and can be used
as a guide to determine estimated performance of NSC's
2p. process. The actual AC performance prediction will be
provided by the design automation system after the design-
er has functionally verified his design in the logic simulator.
Propagation delays as a function of temperature and supply
voltage are shown in Figures 3 and 4 respectively. Utiliza-
tion of these curves will speed the estimation of perform-
ance at other than specified values.
Representative macro types for the 20 process (Table V)
are presented for comparison. Reference SCX family macro
library book for complete specifications.
PROPAGATION DELAY flEu‘flVE TO SUPPLY VOLTAGE
" 4.75 " 5.25 "
Ytgy TU/UMi725-11
FIGURE 4. CMOS Propagation Delays
as a Function ot Supply Voltage
Best-Case
Worst-Case
Temperature = -40''C
Supply Voltage = 5.5V
Extreme Process
Temperature = 100°C
Supply Voltage = 4.5V
Extreme Process
Parameters Parameters
TABLE v. 2,.
Best-Case Worst-Case
Symbol Function LF CLOAD (pF)
tPLH tPHL tPLH tPHL
S1 2-NAND 1 0.095 0.19 0.75 0.95 0
0.39 0.67 2.40 4.05 1
S2 3-NAND 1 0.09 0.27 0.95 1.65 0
0.37 0.92 2.65 5.75 1
S4 2-NOR 1 0.16 0.15 1.1 0.95 o
0.62 0.51 4.15 2.85 1
S5 3-NOR 1 0.23 0.16 1.65 1.13 o
0.85 0.52 6.1 3.05 1
S7 Clock Buffer 2 0.07 0.13 0.45 0.55 0
0.24 0.33 1.45 1.65 1
S8 Inverter 1 0.095 0.16 0.6 0.75 0
0.36 0.52 2.35 2.6 1
S11 2-XOR 2 0.11 0.16 2.6 2.5 0
0.54 0.53 5.8 5.65 1
D9 D Flip-Flop 1
CLK to Q 3 0.71 0.59 5.12 4.38 0
1.02 0.94 7.0 6.25 1
CLK to 03 0.35 0.54 2.38 3.3 0
0.64 0.98 5.37 6.62 1
S9 TRI-STATE Inverter 1 0.18 0.18 1.2 1.35 0
0.60 0.70 4.25 4.15 1
S10 TRI-STATE Buffer 2 0.30 0.27 1.9 1.8 0
0.53 0.53 3.4 3.4 1
u Inverting Input Buffer CMOS 0.23 0.19 0.85 0.70 0
0.45 0.39 2.30 1.80 1
l1 input Buffer TTL 0.33 0.39 2.0 2.45 0
0.60 0.78 3.70 4.80 1
Is Short Circuit Input CMOS 0.04 0.04 0.07 0.07 0
0.15 0.15 0.50 0.50 1
101 Input TTL 0.33 0.39 2.0 2.45 0
0.60 0.78 3.7 4.8 1
Output' 7 0.62 0.78 4.4 5.75 15
1.15 1.55 7.0 9.75 50
kh Input (lrwarting) CMOS 0.23 0.19 0.85 0.70 O
0.45 0.39 2.30 1.80 1
Output' 7 0.62 0.78 4.40 5.75 15
1.15 1.55 7.0 9.75 50
103 Short Circuit Input CMOS 0.04 0.04 0.07 0.07 0
0.15 0.15 0.50 0.50 1
Output' 0.62 0.78 4.40 5.75 15
1.15 1.55 7.0 9.75 50
I04 Output 7 0.65 0.63 4.75 4.5 15
1.17 1.45 8.25 8.25 50
Note: All delays in nanoseconds. tr = t, = 2.5 ns 10' 2-micron. LF = Load Factor.
'TRI-STATE active mode. Voltage Derate = 2.0%l100 mV tram 4.5V. 1LF = 0.1:! pF.
Temperature Derate --- 0.3%l'C from 10trc.
9.0 Design Automation System
The design automation system offers the end user a variety
of interface points and techniques.
Figure 6 shows the standard gate array development flow
and responsibilities. Alternative flows are available and are
presented in Section 11.
The standard flow consists of four major quadrants. They
are the user's site, user's responsibilities, National Semicon-
ductor's technology center, National Semiconductor: re-
sponsibility. These represent the 'where' and 'who' aspects
of task responsibility and location.
User Site
Logic design and definition are the user's responsibility and
are completed at his/het site.
The design file consists of the netlist (wiring diagram) and
the test vectors (pattern file). Each can be generated in a
text file or as the output from a 'workstation'. The syntax of
these files is in the 'hardware design language'.
The evaJuation and acceptance of the completed proto-
types are done by the user at his/her facilities. National
Semiconductor offers technical assistance it necessary.
USER'S SITE --I-w NSC TECHNOLOGY CENTER
TRAINING
DESIGN
USEH'S
RESPONSIBILITY
__._ -...-______-...._ +--
PRDTIITYPES
HETLISY AND TEST VECTORS
FUNCTIONAL
VEHI FICATI on
LOGIC " _
SIMULATION
PERFORMANCE
ESTIMATION
PERFORM”! CE
VEEI FICATION
RESPONSIBILITY
GEN EMTION
ASSEMBLY A
- Whulhntm q
ACCEPTANCE
AND TEST ,
-te PRODUCTION 1
TLIU15725-12
FIGURE 6. Standard Gate Array Development Process and Responslbllltles
National Semiconductor Technology Center
Training includes actual interaction with the design automa-
tion system and, depending on the level of user experience,
requires from three to five days to complete. All of the con-
siderations necessary for the successful completion of the
design are covered during the training. Topics such as,
hardware (i.e., speed, power, pinouts) and software consid-
erations (i.e., logic simulation, fault grading, critical path
analysis) are tailored to meet the user's needs. Training is
provided at the closest technology center. Contact the local
sales representative for the location nearest you.
Functional verification of the logic is accomplished by sub-
mitting the netlist and pattern files to the logic simulator.
The simulator will predict the output results of the specified
logic for the applied vectors. The designer can then deter-
mine if the specified logic meets the design objectives. Sim-
ulation under actual 'loaded' conditions occurs after func-
tional verification and fault grading. Functional verification is
the responsibility of the user.
Fault grading is a measure of the ability of the supplied vec-
tors to detect induced logic errors (i.e., on-chip shorts). The
vectors supplied eventually become the functional portion
of the final production test tape. It is important that the fault
grading figure of merit reach 85%. Fault grading is the re-
sponsibility of the user.
Performance estimation is the prediction that the logic simu-
lator makes by considering actual macro loading and a pro-
jection of the interconnect lengths. This projection is based
on an algorithm which relates fan-out to probable trace
length. Performance estimation is the responsibility of the
Place and route are the actual implementation of the user's
design FIle. Two pieces of design automation software are
used to complete the routing.
Automatic place and route software completes the majority
of interconnects and in most cases completes the entire
array.
Interactive graphics software is used to complete any un-
routed interconnects.
Place and route are the responsibility of National Semicon-
ductor.
Performance verification is the rerunning of the 'perform.
ance estimation' software with the actual cell placements
and associated trace lengths. Performance verification is
the responsibility of the user.
Mask generation, wafer fab, assembly and test are complet-
ed by National Semiconductor.
Prototype evaluation and acceptance are the responsibility
of the user.
National Semiconductor has a large staff of applications
and consulting engineers available to assist users at any
point in the array development process.
9.5 WORKSTATION SUPPORT
The above capabilities, specifically the front-end design
functions (such as schematic capture, netlist entry, logic
simulation and timing estimation), are also available on the
Valid, Daisy, and Mentor workstations. Such capabilities will
be extended to other popular CAE design stations such as
CAE Systems and the IBM PC.
To allow workstation users to properly interface with the
SCX-series gate arrays, National provides a workstation
software design kit. It consists of a set of floppy discs con-
taining the logic symbols of all the macros, a netlist extrair
tor and model timing data for pre-layout simulation and tim-
ing estimation. This design kit is developed, distributed.
maintained and updated solely by National.
Some of the more tirmrconsuming tasks such as fault grad-
ing, auto-place-and-route and post-layout logic verification
are performed on the mainframe computer. A typical design
flow between the workstation and mainframe is illustrated in
Figure 7. Generally, there are three design paths as follows:
. Path A-schematic capture on user's workstation; then
transfer of unsimulated design files (netlist and test vec-
tors) to NSC's mainframe for logic simulation, fault grading
and place-and-route.
- Path B-schematic capture, logic simulation and timing
verification on user's workstation; then transfer of simulat-
ed design files to NSC's mainframe for resimulation (one
pass), fault grading and place-and-route.
q Path C-schematic capture, logic simulation, timing verifi-
cation and place-and-route on user's workstation; then
transfer of database file to NSC's mainframe for resimula-
tion (one pass), fault grading and PG tape generation.
(This is a future capability.)
WORKSTATION
NSC MAINFRAME
I‘ll L1 GIADIIG
[FHIUKEI
IMIIIIG
AUXIIJIEIHZ
It'll”
“I(IATIHI
DESIGN
SIIULIYIOI
[UPYIUIAU
VIIIFICHIDI
rut! Alli
VIIIIMi
Inc“: SEKKIIYIC
$MlltM0t U'YUIE
"II I 5 C' um I
mun: "run
vmnwmu mmm-
FUCK AND
TEST THE
mmnnn - - 3:33;?
mun: PAW
' Pam c Is A DUALJ'IYH APPROACH wutnt ‘IDLI' DIADINO a
DONE ON NAYIONAL'S nulmluui
"wiloum
VIII FICAYIOI
EEIIIAYIIII
‘EIEIATIOI
"ttOtt
AID IEST
PIMDYVHS
FIGURE 7. National's Workstation-to-Malnframe Semi-Custom Design Flow
TL/U/5725-15
10.0 Design Example
The two most popular ways of interfacing to the design au-
tomation system are 1) alphanumeric text entry and 2) work-
station output. A different example will be given for each. In
either case the design automation system requires two ba-
sics files to operate.
Network (File): The network file is the 'wiring diagram' of
the design. It represents how the array is to be 'wired'. More
specifically. it is the manner in which the hardware macros
are interconnected. The syntax of the network file is speci-
Md by a hardware design language (HDL).
Pattern (File): The pattern file represents the stimuli or se-
quence of signals used to exercise the design specified by
the network file. The pattern file ultimately becomes the
functional portion of the final test tape used to screen pro-
duction devices.
The logic simulator operates on the network and pattern
files and predicts the logic output as a function of the pat-
tem file.
Data Entry
NETWORK FILE PATTERN FILE
comm: cmcut cormms INPUT
DESCRIPTION IN uni. stmuu Hm
cmcun' smuuno»
Lomc smuunnu
PREDICTED ouwut
TL/U/5725-13
The simulator has two modes of operation. The first mode is
used to verify the logical integrity of the design. The second
mode considers capacitive circuit loading and anticipated
wire lengths. The result of the second mode is the perform-
ance that can be expected after the circuit has been placed
and routed.
The basic form of a network file is as follows:
SNETWORK (’BEGIN A NETWORK FILE")
, INF INA INB ETC. ('LIST ALL INPUT NAMES‘)
, OUT OUTA OUTB ETC. (‘LIST ALL OUTPUT NAMES‘)
MACRO CALLS (‘SPECIFY MACROS AND
INTERCONNECTS‘)
"' COMMENTS ('MAKE COMMENTS‘)
The macro call syntax for the following circuit fragment is as
specified.
"-iu-tro-i- oca
CLEAR 9c cuts
,.. - - .l I
cmcx ¢an cut
L - - - - - EEJ
TL/lJCm?5-14
$SUBU S8
L--, SPECIFIES A PARTICULAR
MACRO TYPE "
(o SPECIFIES A HARDWARE MACRO "
ssANo (- CIRCUIT NAME ASSOCIATED WITH
ABOVE MACRO "
(. DELIMITER "
CLKB CLK CLRB OGBI CLOCK CLKB CLEAR OG
(' INPUTS TO MACRO ELEMENTS "
e OUTPUTS FROM MACRO ELEMENTS "
TL/U/5725-18
If the designer were using the alphanumeric text mode of
data entry, each unique macro and macro type would be
specified in the above manner until the entire network had
been specified.
in the workstation mode of schematic capture the designer
would call and name each desired macro, then graphically
interconnect each macro in the required fashion. The work-
station would then 'compile' the schematic into the network
10.1 TEXT MODE
rc-CC-"'"-,,,-'",, r--_l
[ H c, 2'
IM-- I Inasal
L. -.-.-..---- 'el _"__l
l" -----.B-- ‘I F'""""''"""? I'_1m
- Ill” :1 1B!
I ",, " 1 outs
Iti8 . l .1 ll 14 rt-ttrt
L _______ el L..."_._l L_EI
I- ------.-. 'l r""'"'-"") |___l c
ar', '1'; 2' 113°:
m1: I I lassl :?c:omn
L -------- .1 'i2rdLI-'' ”1-21
1r--_--;ns-- on |____I
- I l" 'li
mo t- ' _ I Clue $11u I
L ------- el -T1_ cum
czztryo-sf-i9P,tm
L. - s.'d I L,
P" - -lua; L,
135° DE
TL/U/5725-16
FIGURE 8. The Design ot a Four-Blt Latch with TRi-STATE Output is Presented.
Listing 1
$s***W**WAA*W**A*A*****AAA*****A*
$NETWORK
SINPUT INA INB INC ID1 ID2 ODI 002 CLOCK CLEAR
$OUTPUT OUTA OUTB OUTC OUTD
ss* DM74173 MACRO
SSUBU SB
CLKB CLK CLRB OGB / CLOCK CLKB CLEAR OG
$SUBU S4
IG IGB OG / IDI ID? IG CONO OD1 002
SSUBU S15
DAB DA / INA IG IGB 0A
SSUBU s15
DBB DB I INB IG IGB QB
SSUBU s15
DCB DC I INC K3 IGB QC
$SUBU / S15
DDB DD I IND IG IGB QD
$SUBU T1
QA OAB I CON1 DA CLK CLRB
$SUBU T1
QB 088 I CON1 DB CLK CLRB
$SUBU T1
QC QCB I CON1 DC CLK CLRB
$SUBU T1
OD 008 I CON1 DD CLK CLRB
$SUBU S9
$8AN10
OUTA OUTB I OAB 0GB OBB OGB
$SUBU S9
$$AN11
OUTC OUTD I 008 0GB 008 OGB
$SA****A*A******A*A***A***W****A*
10.2 WORKSTATION MODE
FIGURE 9
TLfU/5725-17
$NETWORK
SNPUT CLEAR
Listing 2
CLOCK IDI ID2 INA INB INC IND ODI ODI?
SOUTPUT OUTA OUTB OUTC OUTD
$SUBU S4
$$XCMP 1
XSIG29 XSIG27
$SUBU T1
$$XCMP 10
XSIG33 XSlG41
$SUBU S9
$$XCMP 1 1
OUTA OUTB /
$SUBU S9
$$XCMP 12
OUTC OUTD /
$SUBU S8
$$XCMP 2
XSIG22 XSIG20
$SUBU S15
$$XCMP 3
OPEN-1 XSIGS7
SSUBU S15
$$XCMP 4
OPEN-2 XSIGSS
$SUBU S15
$$XCMP 5
OPEN-3 XSIGSS
SSUBU S15
SSXCMP 6
OPEN-4 XSIG34
$SUBU T1
$$XCMP 7
XSIGSO XSIGSB
$SUBU T1
$$XCMP 8
XSIG31 XSIG39
$SUBU T1
SSXCMP 9
XSlG32 XSIG4O
XSIG18 / XSIG27 GND IDI ID2 OD1 OD2
/ VCC XSIG34 XSIG20 XSIG21
XSIG41 XSIG22 XSIG40 XSIG22
XSIG39 XSIG22 XSIGSB X81622
XSIG21 XSIG19 l XSIG18 XSIG19 CLEAR CLOCK
/ XSIG30 XSIG29 IND XSIG27
/ XSIG31 XSIG29 INC XSIG27
I XSIG32 XSIG29 INB XSIG27
I XSIG33 XSIG29 INA XSIG27
/ VCC XSIGS? XSIGZO
XSIG21
/ VCC XSIGSB XSIG20
XSIG21
/ VCC XSIG35 XSIG20 XSIGZI
10.3 PATTERN FILE
INA HI
INB HI
INC HI
IND HI
IDI HI
ID2 L0
ODI HI
0D2 HI
l—s‘Ul—A-JAAAAI
oc'nc'nmmuuuu
10.4 SIMULATOR OUTPUT
$CYCLE = 1000 1000 REPRESENTS THE NUMBER OF INTERVALS PER CYCLE 1 INTERVAL = 100 PICOSECONDS
$$**************A*W****A*
$$i PATTERN FILE CODING FOLLOWS
$8**A**A*******AA********
$$t PATTERN FILE FOR TESTING DM74173
$$* TEST SHOULD SWEEP 16 CYCLES
INPUT SIGNALS USED TO SIMULATE THE NETWORK
1-16) SINGLE CLOCK REPEATING 01 THROUGH CYCLE 16
INPUTS AS SPECIFIED
BY PATTERN FILE
IIII ll 00
NNNN DD DD
ABCD 12 12
7 1111 00 01
8 0000 00 01
9 0000 01 00
"140 0000 01 00
10 0000 01 00
11 1111 01 00
12 1111 01 00
13 0000 01 10
"129 0000 01 10
14 0000 01 10
15 0000 01 01
16 0000 01 01
o—naoao—d
0‘40‘044
oaao—noaa
ooooooooooooooooouA—naznzbmr-
—AO-‘oo—tO—AOO—JOdoO—‘O—tOOXOOl—O
CIRCUIT INPUTS HI AT SPECIFIED CYCLE. LOW AT ALL OTH ER CYCLES
---ClRCUlTlNPUT LO AT SPECIFIED CYCLE. HI AT ALL OTHER CYCLES TL/U/S725-19
OUTPUTS
AS SPECIFIED
BY PATTERN FILE
lJEOUENTIAL NUMBERS REPRESENT TIME CYCLES
ZZZZ = HIGH IMPEDANCE STATE
1111 = HIGH STATE
0000 = LOW STATE
"Intermittent numbers represent settling time in hundred-plcoseconds that
occur between time cycles.
11.0 Alternative Interfaces
Flexibility in the design automation system allows a variety
of user/vendor interfaces. Options include:
. User supplies schematic, timing diagrams and parametric
specifications. National Semiconductor implements the ar-
ray (Turn-Key design).
. User 'captures' the design at his facility or at a National
Semiconductor technology center. National Semiconduc-
tor supports a wide range of communication protocols for
interfacing to industrial (mainframe) or personal comput-
ers. These are available with or without error control and
communication rates of 300 to 9600 baud.
0 User follows basic array development flow specified in
Figure 6.
. User generates logic simulator compatible files from his
workstation. Completes the array using National Semicon-
ductor's design automation system.
. User generates compatible design tiles and logic verifica-
tion in his/her simulator, then interfaces to design auto-
mation system at either fault grading, performance estima-
tion, or 'place and route'.
. User supplies completed design files from National Semi-
conductor's alternate source, effectively entering design
automation system just prior to digitizing.
0 User provides all design files necessary for mask genera-
tion, essentially a 'customer owned tooling' (COT) ap-
proach.
12.0 Training and Technical
Services
To facilitate users to design with National's CMOS gate ar-
rays, training is offered on a regular basis at National's
worldwide technology centers. At the new Santa Clara train-
ing/design center, multiple workstations are used to com-
plement the basic training. Additional workstations located
in private offices are also available for customers to enter,
capture and verity their designs. As part of the technical
services, experienced design consultants from National will
be available at the training/design center to provide onothe-
spot engineering assistance.
The training, workstation design kit and other technical serv-
ices are provided try National's Training, Layout, Consulting
(TLC) Group. Overall technical customer-support services
include the following:
. Customer training
q Technical documentation
0 Design assistance
. Simulation support
. Workstation support
q Turnkey design
q PIace-and-Route implementation
. Mainframe software qualification
q Workstation software qualification
For any technical assistance, contact National's AppliCa-
tions Group at (408) 721-4614.
13.0 Technology Centers
National Semiconductor Headquarters,
2900 Semiconductor Drive, Santa Clara, California 95051
(408) 721-4614, TWX: (910) 339-9240
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Telephone: (617) 273-0964
National Semiconductor S.A.
Expansion 1000
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Telephone: 33-1-660-8140
Telex: 842-250959
National Semiconductor GmbH
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Telephone: 49-8141 _103-1
Telex: 841-527649
Natlonal Semiconductor AB
Box 2016
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Telephone: 46-8-970190
Telex: 854-10731
National Semiconductor UK. Ltd
The Maples
Kembrey Park
Swindon SN 2 6UT
Wilts, England
Telephone: 44-793-614141
Telex: 851-444674
National Semiconductor SPA
Via Solferino 19
1-20121 Milan, Italy
Telephone: 39-2-3452046
Telex: 332835
SCX microCMOS Gate Array Family Application Guide
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the lite
support device or system, or to affect its safety or
effectiveness.
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Telex' 52996 NSSEA HX
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Tel: (55/11) 212-5066
Telex 3914131991 NSBR BR
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Tel: (03) 7296333
Tamc M32096
Nahmal does not assume any responsibility lor use ot any ctcuuy descnbed. no cram patenl hcanses are umle and Namnal resewo: Ibo ugh! at any urns wnhoul notice 10 change san cucudry and sptscrfttatons
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
SCX6206 - product/scx6206?HQS=T|-nu|l-null-dscatalog-df-pf-nulI-wwe
SCX6218 - product/scx6218?HQS=T|-nu||-nulI-dscatalog-df-pf-nulI-wwe
SCX6225 - product/scx6225?HQS=T|-nu|I-nulI-dscatalog-df-pf—nulI-wwe
SCX6232 - product/scx6232?HQS=T|-nu|I-null-dscataIog-df—pf-nuII-wwe
SCX6244 - product/scx6244?HQS=T|-nu|l-null-dscatalog-df-pf-nulI-wwe
SCX6260 - product/scx6260?HQS=T|-nu||-nulI-dscatalog-df-pf-nulI-wwe
