SCC68681C1A44 ,Dual asynchronous receiver/transmitterINTEGRATED CIRCUITSSCC68681Dual asynchronous receiver/transmitter(DUART)Product data 2004 Apr 06
SCC68681C1A44-SCC68681E1A44
Dual asynchronous receiver/transmitter
Product data 2004 Apr 06
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
DESCRIPTIONThe Philips Semiconductors SCC68681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. It is compatible with other S68000 family devices, and can
also interface easily with other microprocessors. The DUART can be
used in polled or interrupt driven systems. It is manufactured in a
CMOS process.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16× clock derived from a programmable counter/timer,
or an external 1× or 16× clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruply buffered to minimize the potential of
receiver overrun or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the buffer of the receiving device is
full.
Also provided on the SCC68681 are a multipurpose 6-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
FEATURES S68000 bus compatible Dual full-duplex asynchronous receiver/transmitter Quadruple buffered receiver data registers Programmable data format
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16-bit increments Programmable baud rate for each receiver and transmitter
selectable from:
22 fixed rates: 50 to 115.2 kbaud
Non-standard rates to 115.2 kb
Non-standard user-defined rate derived from programmable
counter/timer
External 1× or 16× clock 16-bit programmable Counter/Timer Parity, framing, and overrun error detection False start bit detection Line break detection and generation Programmable channel mode
Normal (full-duplex)
Automatic echo
Local loopback
Remote loopback Multi-function programmable 16-bit counter/timer Multi-function 6-bit input port
Can serve as clock or control inputs
Change-of-state detection on four inputs
100 kΩ typical pull-up resistors Multi-function 8-bit output port
Individual bit set/reset capability
Outputs can be programmed to be status/interrupt/DMA signals
Auto 485 turn-around Versatile interrupt system
Single interrupt output with eight maskable interrupting
conditions
Interrupt vector output on interrupt acknowledge
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs Maximum data transfer rates: 1× = 1 MB/sec; 16× = 125 kB/sec Automatic wake-up mode for multidrop applications Start-end break interrupt/status Detects break which originates in the middle of a character On-chip crystal oscillator Single +5 V power supply Commercial and industrial temperature ranges available DIP and PLCC packages
ORDERING INFORMATION
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
PIN CONFIGURATIONS
Figure 1. Pin Configurations
PIN DESCRIPTION
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAM
Figure 2. Block Diagram
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAMThe SCC68681 DUART consists of the following eight major
sections: data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port. Refer
to Figure 2, ‘Block Diagram’.
Data Bus BufferThe data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
Operation ControlThe operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer. The DTACKN output is asserted during write
and read cycles to indicate to the CPU that data has been latched
on a write cycle, or that valid data is present on the bus on a read
cycle.
Interrupt ControlA single active-LOW interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR), the Auditory Control
Register(ACR) and the Interrupt Vector Register (IVR). The IMR
may be programmed to select only certain conditions to cause
INTRN to be asserted. The ISR can be read by the CPU to
determine all currently active interrupting conditions. When IACKN is
asserted, and the DUART has an interrupt pending, the DUART
responds by placing the contents of the IVR register on the data bus
and asserting DTACKN.
Outputs OP3–OP7 can be programmed to provide discrete interrupt
outputs for the transmitter, receivers, and counter/timer.
Timing CircuitsThe timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and four clock
selectors. The crystal oscillator operates directly from a crystal
connected across the X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may be connected to
X1/CLK. The clock serves as the basic timing reference for the Baud
Rate Generator (BRG), the counter/timer, and other internal circuits.
A clock signal within the limits specified in the specifications section
of this data sheet must always be supplied to the DUART. If an
external is used instead of a crystal, X1 should be driven using a
configuration similar to the one in Figure 8.
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 18 commonly used data
communications baud rates ranging from 50 to 115.2 k baud. The
clock outputs from the BRG are at 16× the actual baud rate. The
counter/timer can be used as a timer to produce a 16× clock for any
other baud rate by counting down the crystal clock or an external
clock. The four clock selectors allow the independent selection, for
each receiver and transmitter, of any of these baud rates or external
timing signal.
Counter/Timer (C/T)The counter timer is a 16 bit programmable divider that operates
one of three modes: Counter, Timer or Time Out mode. In all three In the time out mode it monitors the receiver data flow and signals
data flow has paused. In the time out mode the receiver controls
the starting/stopping of the C/T.
The counter operates as a down counter and sets its output bit in
the ISR (Interrupt Status Register) each time it passes through 0.
The output of the counter/timer may be seen on one of the OP pins
or as an Rx or Tx clock.
The Timer/Counter is controlled with six (6) ‘commands’; Start C/T,
Stop C/T, write C/T, preset registers, read C/T value, set or reset
time out mode.
Please see the detail of the commands under the Counter/Timer
register descriptions.
Communications Channels A and BEach communications channel of the SCC68681 comprises a
full-duplex asynchronous receiver/transmitter (DUART). The
operating frequency for each receiver and transmitter can be
selected independently from the baud rate generator, the counter
timer, or from an external input.
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD
output pin. The receiver accepts serial data on the RxD pin,
converts this serial input to parallel format, checks for start bit, stop
bit, parity bit (if any), or break condition and sends an assembled
character to the CPU.
The input port pulse detection circuitry uses a 38.4 kHz sampling
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25 μs (assuming that the
clock input is 3.6864 MHz). The detection circuitry, in order to
guarantee a true change in level has occurred, requires that two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25 μs if
the transition occurs coincident with the first sample pulse. The
50 μs time refers to the situation in which the change of state is just
missed and the first change of state is not detected until 25 μs later.
Input PortThe inputs to this unlatched 6-bit port can be read by the CPU by
performing a read operation at address 0xD. A HIGH input results in
a logic ‘1’ while a LOW input results in a logic ‘0’. D7 will always
read as a logic ‘1’ and D6 will reflect the level of IACKN. The pins of
this port can also serve as auxiliary inputs to certain portions of the
DUART logic.
Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A HIGH-to-LOW or LOW-to-HIGH
transition of these inputs, lasting longer than 25 to 50 μs, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.
All the IP pins have a small pull-up device that will source 1 to 4 μA
of current from VCC. These pins do not require pull-up devices or
VCC connections if they are not used.
Output PortThe 8-bit multipurpose output port can be used as a general
purpose output port, in which case the outputs are the complements
of the Output Port Register (OPR). OPR[n] = 1 results in
OP[n] = LOW and vice versa. Bits of the OPR can be individually set
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
address 0xF with the accompanying data specifying the bits to be
reset (1 = reset, 0 = no change).
Outputs can be also individually assigned specific functions by
appropriate programming of the Channel A mode registers (MR1A,
MR2A), the Channel B mode registers (MR1B, MR2B), and the
Output Port Configuration Register (OPCR).
Please note that these pins drive both HIGH and LOW. However,
when they are programmed to represent interrupt type functions
(such as receiver ready, transmitter ready or counter/timer ready)
they will be switched to an open drain configuration in which case an
external pull-up device would be required.
OPERATION
TransmitterThe SCC68681 is conditioned to transmit data when the transmitter
is enabled through the command register. The SCC68681 indicates
to the CPU that it is ready to accept a character by setting the
TxRDY bit in the status register. This condition can be programmed
to generate an interrupt request at OP6 or OP7 and INTRN. When a
character is loaded into the Transmit Holding Register (THR), the
above conditions are negated. Data is transferred from the holding
register to transmit shift register when it is idle or has completed
transmission of the previous character. The TxRDY conditions are
then asserted again which means one full character time of buffering
is provided. Characters cannot be loaded into the THR while the
transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the THR, the TxD output remains HIGH
and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the THR.
If the transmitter is disabled, it continues operating until the
character currently being transmitted is completely sent out. The
transmitter can be forced to send a continuous LOW condition by
issuing a send break command.
The transmitter can be reset through a software command (0x30).
If it is reset, operation ceases immediately and the transmitter must
be enabled through the command register before resuming
operation. If CTS operation is enable, the CTSN input must be LOW
in order for the character to be transmitted. If it goes HIGH in the
middle of a transmission, the character in the shift register is
transmitted and TxDA then remains in the marking state until CTSN
goes LOW. The transmitter can also control the deactivation of the
RTSN output. If programmed, the RTSN output will be reset one bit
time after the character in the transmit shift register and transmit
holding register (if any) are completely transmitted, if the transmitter
has been disabled.
ReceiverThe SCC68681 is conditioned to receive data when enabled through
the command register. The receiver looks for a HIGH-to-LOW
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16×
to sample the input at one bit time intervals at the theoretical center
of the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
the Receive Holding Register (RHR) and the RxRDY bit in the SR is
set to a ‘1’. This condition can be programmed to generate an
interrupt at OP4 or OP5 and INTRN. If the character length is less
than 8 bits, the most significant unused bits in the RHR are set to
zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains LOW for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).
The parity error, framing error, and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected (RxD is LOW for the
entire character including the stop bit), a character consisting of all
zeros will be loaded into the RHR and the received break bit in the
SR is set to ‘1’. The RxD input must return to HIGH for two (2) clock
edges of the X1 crystal clock for the receiver to recognize the end of
the break condition and begin the search for a start bit. This will
usually require a HIGH time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to
the X1 clock.
Receiver FIFOThe RHR consists of a First-In-First-Out (FIFO) stack with a
capacity of three characters. Data is loaded from the receive shift
register into the top most empty position of the FIFO. The RxRDY bit
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all three stack
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.
Receiver Status BitsIn addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO.
In the ‘block’ mode, the status provided in the SR for these three bits
is the logical-OR of the status for all characters coming to the top of
the FIFO since the last ‘reset error’ command was issued. In either
mode reading the SR does not affect the FIFO. The FIFO is
‘popped’ only when the RHR is read. Therefore the status register
should be read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is
held in the receive shift register until a FIFO position is available. If
an additional character is received while this state exits, the
contents of the FIFO are not affected; the character previously in the
shift register is lost and the overrun error status bit (SR[4]) will be
set upon receipt of the start bit of the new (overrunning) character).
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
re-asserted (set to ‘0’) automatically. This feature can be used to
prevent an overrun, in the receiver, by connecting the RTSN output
to the CTSN input of the transmitting device.
Receiver Reset and DisableReceiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver after
a disable will cause the receiver to begin assembling characters at the
next start bit detected. A receiver reset will discard the present shift
register data, reset the receiver ready bit (RxRDY), clear the status of
the byte at the top of the FIFO and re-align the FIFO read/write
pointers. This has the appearance of ‘clearing or flushing’ the receiver
FIFO. In fact, the FIFO is NEVER cleared! The data in the FIFO
remains valid until overwritten by another received character. Because
of this, erroneous reading or extra reads of the receiver FIFO will
mis-align the FIFO pointers and result in the reading of previously
read data. A receiver reset will re-align the pointers.
Multidrop ModeThe DUART is equipped with a wake up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3] or
MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode of
operation, a ‘master’ station transmits an address character followed by
data characters for the addressed ‘slave’ station. The slave stations, with
receivers that are normally disabled, examine the received data stream
and ‘wake up’ the CPU (by setting RxRDY) only upon receipt of an
address character. The CPU compares the received address to its
station address and enables the receiver if it wishes to receive the
subsequent data characters. Upon receipt of another address character,
the CPU may disable the receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted A/D
bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which
identifies the corresponding data bits as data while
MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which
identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bits into the THR.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RHR FIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RHR. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
break detect operate normally whether or not the receive is enabled.
PROGRAMMINGThe operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESETN. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1x by RESET
or by issuing a ‘reset pointer’ command via the corresponding
command register. Any read or write of the mode register while the
pointer is at MR1x, switches the pointer to MR2x. The pointer then
remains at MR2x, so that subsequent accesses are always to MR2x
unless the pointer is reset to MR1x as described above.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
Table 1. SCC68681 Register Addressing
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
Table 2. Register Bit Formats
NOTE: In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset. Please see Receiver Reset note on page 19.
NOTE:*Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bits/char.
NOTE:* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
NOTE:*Access to the upper four bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter cannot
be loaded. For Rx and Tx performing a Disable and Enable at the same time results in Disable.
NOTE:*These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the
top of the FIFO together with bits (4:0). These bits are cleared by a ‘reset error status’ command. In character mode they are discarded when
the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using the error reset
command (command 4x) or a receiver reset.
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
Table 2. Register Bit Formats (Continued)
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
MR1A – Channel A Mode Register 1MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRA. After reading or writing MR1A, the pointer will point
to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send ControlThis bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full.
However, OPR[0] is not reset and RTSAN will be asserted again
when an empty FIFO position is available. This feature can be used
for flow control to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input of the transmitting
device.
MR1A[6] – Channel A Receiver Interrupt SelectThis bit selects either the Channel A receiver ready status (RxRDY)
or the Channel A FIFO full status (FFULL) to be used for CPU
interrupts. It also causes the selected bit to be output on OP4 if it is
programmed as an interrupt output via the OPCR.
MR1A[5] – Channel A Error Mode SelectThis bit select the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block’
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
MR1A[4:3| – Channel A Parity Mode SelectIf ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type SelectThis bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1A[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it selects
the polarity of the A/D bit.
MR1A[1:0] – Channel A Bits Per Character SelectThis field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
MR2A – Channel A Mode Register 2MR2A is accessed when the Channel A MR pointer points to MR2,
which occurs after any access to MR1A. Accesses to MR2A do not
change the pointer.
MR2A[7:6] – Channel A Mode SelectEach channel of the DUART can operate in one of four modes.
MR2A[7:6] = 00 is the normal mode, with the transmitter and
receiver operating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically
re-transmits the received data. The following conditions are true The receive clock is used for the transmitter. The receiver must be enabled, but the transmitter need not be
enabled. The Channel A TxRDY and TxEMT status bits are inactive. The received parity is checked, but is not regenerated for
transmission, i.e. transmitted parity bit is as received. Character framing is checked, but the stop bits are retransmitted
as received. A received break is echoed as received until the next valid start
bit is detected. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
Two diagnostic modes can also be configured. MR2A[7:6] = 10
selects local loopback mode. In this mode: The transmitter output is internally connected to the receiver
input. The transmit clock is used for the receiver. The TxDA output is held HIGH. The RxDA input is ignored. The transmitter must be enabled, but the receiver need not be
enabled. CPU to transmitter and receiver communications continue
normally.
The second diagnostic mode is the remote loopback mode, selected
by MR2A[7:6] = 11. In this mode: Received data is re-clocked and re-transmitted on the TxDA
output. The receive clock is used for the transmitter. Received data is not sent to the local CPU, and the error status
conditions are inactive. The received parity is not checked and is not regenerated for
transmission, i.e., transmitted parity is as received. The receiver must be enabled. Character framing is not checked, and the stop bits are
retransmitted as received. A received break is echoed as received until the next valid start
bit is detected.
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes: if the
de-selection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop has been re-transmitted.
MR2A[5] – Channel A Transmitter Request-to-Send ControlCAUTION: When the transmitter controls the OP pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
commands issued via the SOPR and ROPR registers. MR2[5] set to
1 caused the RTSN to be reset automatically one bit time after the
character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
bits) if a previously issued transmitter disable is pending. This
feature can be used to automatically terminate the transmission as
follows: Program the auto-reset mode: MR2[5]=1 Enable transmitter, if not already enabled Set OPR[0] or OPR[1] to ‘1’ via SOPR and ROPR. Send message After the last character of the message is loaded to the THR,
disable the transmitter. (If the transmitter is underrun, a special
case exists. See note below.) The last character will be transmitted and the RTSN will be reset
one bit time after the last stop bit is sent.
NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
immediately after the transmitter is enabled from the disabled or
reset state. When using the above procedure with the transmitter in
the underrun condition, the issuing of the transmitter disable must be
delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
MR2A[4] – Channel A Clear-to-Send ControlIf this bit is 0, CTSAN has no effect on the transmitter. If this bit is a
1, the transmitter checks the state of CTSAN (IP0) each time it is
ready to send a character. If IP0 is asserted (LOW), the character is
transmitted. If it is negated (HIGH), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes
LOW. Changes in CTSAN while a character is being transmitted do
not affect the transmission of that character.
MR2A[3:0] – Channel A Stop Bit Length SelectThis field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1-9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1-1/16 to
2 stop bits can be programmed in increments of 1/16 bit. The
receiver only checks for a ‘mark’ condition at the center of the first
stop bit position (one bit time after the last data bit, or after the parity
bit is enabled), in all cases.
If an external 1× clock is used for the transmitter, MR2A[3] = 0
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
transmitted.
MR1B – Channel B Mode Register 1MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will point
to MR2B.
The bit definitions for this register are identical to MR1A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs.
MR2B – Channel B Mode Register 2MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
CSRA – Channel A Clock Select Register
CSRA[7:4] – Channel A Receiver Clock SelectThis field selects the baud rate clock for the Channel A receiver. The
field definition is shown in Table 3.
CSRA[3:0] – Channel A Transmitter Clock SelectThis field selects the baud rate clock for the Channel A transmitter.
The field definition is as shown in Table 3, except as follows:
The transmitter and receiver clock is always a 16× clock except
for 1111 selection.
Table 3. X1 clock = 3.6864 MHz
See Table 6 for other rates to 115.2 k baud.
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock SelectThis field selects the baud rate clock for the Channel B receiver. The
field definition is as shown in Table 3, except as follows:
The receiver clock is always a 16× clock except for CSRB[7:4] = 1111.
CSRB[3:0] – Channel B Transmitter Clock SelectThis field selects the baud rate clock for the Channel B transmitter.
The field definition is as shown in Table 3, except as follows:
The transmitter clock is always a 16× clock except for
CSRB[3:0] = 1111.
CRA – Channel A Command RegisterCRA is a register used to supply commands to Channel A. Multiple
commands can be specified in a single write to CRA as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
CRA[7] – Not UsedShould be set to zero for upward compatibility with newer parts.
CRA[6:4] – Miscellaneous CommandsThe encoded value of this field may be used to specify a single
command as follows:
CRA[6:4] – COMMAND
NOTE: Access to the upper four bits of the command register should
be separated by three (3) edges of the X1 clock.
000 No command.
001 Reset MR pointer. Causes the Channel A MR pointer to point
to MR1.
010 Reset receiver. Resets the Channel A receiver as if a
hardware reset had been applied. The receiver is disabled
and the FIFO is flushed.
011 Reset transmitter. Resets the Channel A transmitter as if a
hardware reset had been applied.
100 Reset error status. Clears the Channel A Received Break,
Parity Error, and Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to clear OE status
(although RB, PE and FE bits will also be cleared) and in
block mode to clear all error status after a block of data has
been received.
101 Reset Channel A break change interrupt. Causes the
Channel A break detect change bit in the interrupt status
register (ISR[2]) to be cleared to zero.
110 Start break. Forces the TxDA output LOW (spacing). If the
transmitter is empty the start of the break condition will be
delayed up to two bit times. If the transmitter is active the
break begins when transmission of the character is
completed. If a character is in the THR, the start of the break
will be delayed until that character, or any other loaded
subsequently are transmitted. The transmitter must be
CRA[3] – Disable Channel A TransmitterThis command terminates transmitter operation and reset the
TxDRY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the THR when the transmitter is
disabled, the transmission of the character(s) is completed before
assuming the inactive state.
CRA[2] – Enable Channel A TransmitterEnables operation of the Channel A transmitter. The TxRDY status
bit will be asserted.
CRA[1] – Disable Channel A ReceiverThis command terminates operation of the receiver immediately – a
character being received will be lost. The command has no effect on
the receiver status bits or any other control registers. If the special
multidrop mode is programmed, the receiver operates even if it is
disabled. See Operation section.
CRA[0] – Enable Channel A ReceiverEnables operation of the Channel A receiver. If not in the special
wake-up mode, this also forces the receiver into the search for
start-bit state.
Note: Performing a Disable and Enable at the same time results inDisable.
CRB – Channel B Command RegisterCRB is a register used to supply commands to Channel B. Multiple
commands can be specified in a single write to CRB as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
The bit definitions for this register are identical to the bit definitions
for CRA, except that all control actions apply to the Channel B
receiver and transmitter and the corresponding inputs and outputs.,
SRA – Channel A Status Register
SRA[7] – Channel A Received BreakThis bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received further entries to the
FIFO are inhibited until the RxDA line to the marking state for at
least one-half a bit time two successive edges of the internal or
external 1× clock. This will usually require a HIGH time of one X1
clock period or 3 X1 edges since the clock of the controller is
not synchronous to the X1 clock.When this bit is set, the Channel A ‘change in break’ bit in the ISR
(ISR[2]) is set. ISR[2] is also set when the end of the break
condition, as defined above, is detected.
The break detect circuitry can detect breaks that originate in the
middle of a received character. However, if a break begins in the
middle of a character, it must persist until at least the end of the next
character time in order for it to be detected.
SRA[6] – Channel A Framing ErrorThis bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
SRA[5] – Channel A Parity ErrorThis bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity.
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
SRA[4] – Channel A Overrun ErrorThis bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost.
This bit is cleared by a ‘reset error status’ command.
SRA[3] – Channel A Transmitter Empty (TxEMTA)This bit will be set when the transmitter underruns, i.e., both the
TxEMT and TxRDY bits are set. This bit and TxRDY are set when
the transmitter is first enabled and at any time it is re-enabled after
either (a) reset, or (b) the transmitter has assumed the disabled
state. It is always set after transmission of the last stop bit of a
character if no character is in the THR awaiting transmission.
It is reset when the THR is loaded by the CPU, a pending
transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the underrun condition.
SRA[2] – Channel A Transmitter Ready (TxRDYA)This bit, when set, indicates that the THR is empty and ready to be
loaded with a character. This bit is cleared when the THR is loaded
by the CPU and is set when the character is transferred to the transmit
shift register. TxRDY is reset when the transmitter is disabled and is
set when the transmitter is first enabled, viz., characters loaded into
the THR while the transmitter is disabled will not be transmitted.
SRA[1] – Channel A FIFO Full (FFULLA)This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, FFULL will not be
reset when the CPU reads the RHR.
SRA[0] – Channel A Receiver Ready (RxRDYA)This bit indicates that a character has been received and is waiting
in the FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift to the FIFO and reset when the
CPU reads the RHR, if after this read there are not more characters
still in the FIFO.
SRB – Channel B Status RegisterThe bit definitions for this register are identical to the bit definitions
for SRA, except that all status applies to the Channel B receiver and
transmitter and the corresponding inputs and outputs.
Philips Semiconductors Product data
SCC68681Dual asynchronous receiver/transmitter (DUART)
OPCR – Output Port Configuration Register
OPCR[7] – OP7 Output SelectThis bit programs the OP7 output to provide one of the following: The complement of OPR[7]. The Channel B transmitter interrupt output which is the comple-
ment of TxRDYB. When in this mode OP7 acts as an open-
drain output. Note that this output is not masked by the contents
of the IMR.
OPCR[6] – OP6 Output SelectThis bit programs the OP6 output to provide one of the following: The complement of OPR[6]. The Channel A transmitter interrupt output which is the comple-
ment of TxRDYA. When in this mode OP6 acts as an open-
drain output. Note that this output is not masked by the contents
of the IMR.
OPCR[5] – OP5 Output SelectThis bit programs the OP5 output to provide one of the following: The complement of OPR[5]. The Channel B transmitter interrupt output which is the comple-
ment of ISR[5]. When in this mode OP5 acts as an open-drain
output. Note that this output is not masked by the contents of
the IMR.
OPCR[4] – OP4 Output SelectThis field programs the OP4 output to provide one of the following: The complement of OPR[4]. The Channel A receiver interrupt output which is the comple-
ment of ISR[1]. When in this mode OP4 acts as an open-drain
output. Note that this output is not masked by the contents of
the IMR.
OPCR[3:2] – OP3 Output SelectThis bit programs the OP3 output to provide one of the following:
00: The complement of OPR[3].
01: The counter/timer output, in which case OP3 acts as an open-
drain output. In the timer mode, this output is a square wave at
the programmed frequency. In the counter mode, the output
remains HIGH until terminal count is reached, at which time it
goes LOW. The output returns to the HIGH state when the
counter is stopped by a stop counter command. Note that this
output is not masked by the contents of the IMR.
10: The 1× clock for the Channel B transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted,
a free running 1× clock is output.
11: The 1× clock for the Channel B receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1× clock is output.
OPCR[1:0] – OP2 Output SelectThis field programs the OP2 output to provide one of the following:
00: The complement of OPR[2].
01: The 16× clock for the Channel A transmitter. This is the clock
selected by CSRA[3:0], and will be a 1× clock if CSRA[3:0] = 1111.
10: The 1× clock for the Channel A transmitter, which is the clock
that shifts the transmitted data. If data is not being transmitted,
a free running 1× clock is output.
11: The 1× clock for the Channel A receiver, which is the clock that
samples the received data. If data is not being received, a free
running 1× clock is output.
Table 4. Bit Rate Generator Characteristics
Crystal or Clock = 3.6864MHz
NOTE:Duty cycle of 16× clock is 50% ± 1%.
Rates will change in direct proportion to to the X1 rate of 3.6864 MHz.
Asynchronous UART communications can tolerate frequency error
of 4.1% to 6.7% in a ‘clean’ communications channel. The percent of
error changes as the character length changes. The above
percentages range from 5 bits not parity to 8 bits with parity and one
stop bit. The error with 8 bits not parity and one stop bit is 4.6%. If a
stop bit length of 9/16 is used, the error tolerance will approach 0
due to a variable error of up to 1/16 bit time in receiver clock phase
alignment to the start bit.
