SCC2698BE1A84 ,Enhanced octal universal asynchronous receiver/transmitter (Octal UART)INTEGRATED CIRCUITSSCC2698BEnhanced octal universal asynchronousreceiver/transmitter (Octal UART)Pr ..
SCC2698BE1A84 ,Enhanced octal universal asynchronous receiver/transmitter (Octal UART)FEATURESThe SCC2698B Enhanced Octal Universal Asynchronous• Eight full-duplex independent asynchron ..
SCC68070CCA84 ,15 MHz, 16/31-bit microprocessor
SCC68070CCA84 ,15 MHz, 16/31-bit microprocessor
SCC68681C1A44 ,Dual asynchronous receiver/transmitterINTEGRATED CIRCUITSSCC68681Dual asynchronous receiver/transmitter(DUART)Product data 2004 Apr 06
SCC2698BC1A84-SCC2698BE1A84
Enhanced octal universal asynchronous receiver/transmitter (Octal UART)
Product specification
Supersedes data of 1998 Sep 04
2000 Jan 31
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
DESCRIPTIONThe SCC2698B Enhanced Octal Universal Asynchronous
Receiver/Transmitter (Octal UART) is a single chip MOS-LSI
communications device that provides eight full-duplex asynchronous
receiver/transmitter channels in a single package. It is fabricated
with CMOS technology which combines the benefits of high density
and low power consumption.
The operating speed of each receiver and transmitter can be
selected independently as one of 26 fixed baud rates, a 16X clock
derived from a programmable counter/timer, or an external 1X or
16X clock. The baud rate generator and counter/timer can operate
directly from a crystal or from external clock inputs. The ability to
independently program the operating speed of the receiver and
transmitter make the Octal UART particularly attractive for
dual-speed channel applications such as clustered terminal
systems.
The receiver is quadruple buffered to minimize the potential of
receiver overrun or to reduce interrupt overhead in interrupt driven
systems. In addition, a handshaking (RTS/CTS) capability is
provided to disable a remote UART transmitter when the receiver
buffer is full.
The UART provides a power-down mode in which the oscillator is
frozen but the register contents are stored. This results in reduced
power consumption on the order of several magnitudes. The Octal
UART is fully TTL compatible and operates from a single +5V power
supply.
The SCC2698B is an upwardly compatible version of the 2698A
Octal UART. In PLCC packaging, it is enhanced by the addition of
receiver ready or FIFO full status outputs, and transmitter empty
status outputs for each channel on 16 multipurpose I/O pins. The
multipurpose pins of the 2698B RIO pins, thus DMA and modem
control is provided.
FEATURES Eight full-duplex independent asynchronous receiver/transmitters Quadruple buffered receiver data register Programmable data format: 5 to 8 data bits plus parity Odd, even, no parity or force parity 1, 1.5 or 2 stop bits programmable in 1/16-bit increments Baud rate for the receiver and transmitter selectable from: 26 fixed rates: 50 to 38.4K baud
Non-standard rates to 115.2K baud User-defined rates from the programmable counter/timer
associated with each of four blocks External 1x or 16x clock Parity, framing, and overrun error detection False start bit detection Line break detection and generation Programmable channel mode Normal (full-duplex), automatic echo, local loop back, remote
loopback Four multi-function programmable 16-bit counter/timers Four interrupt outputs with eight maskable interrupting conditions
for each output Receiver ready/FIFO full and transmitter ready status available on
16 multi-function pins in PLCC package On-chip crystal oscillator TTL compatible Single +5V power supply with low power mode Eight multi-purpose output pins Sixteen multi-purpose I/O pins Sixteen multi-purpose Input pins with pull-up resistors
ORDERING INFORMATION
NOTE: Pin Grid Array (PGA) package version is available from Philips Components Military Division.
ABSOLUTE MAXIMUM RATINGS1
NOTES: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
PIN CONFIGURATIONS
Figure 1. Pin Configurations
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
BLOCK DIAGRAM
Figure 2. Block Diagram
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
PIN DESCRIPTION
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
PIN DESCRIPTION (Continued)
BLOCK DIAGRAMAs shown in the block diagram, the Octal UART consists of: data
bus buffer, interrupt control, operation control, timing, and eight
receiver and transmitter channels. The eight channels are divided
into four different blocks, each block independent of each other (see
Figure 3). Figure 2 represents the DUART block.
Figure 3. Channel Architecture
Channel BlocksThere are four blocks (Figure 3), each containing two sets of
receiver/transmitters. In the following discussion, the description
applies to Block A which contains channels a and b. However, the
same information applies to all channel blocks.
Data Bus BufferThe data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the Octal UART.
Interrupt ControlA single interrupt output per DUART (INTRN) is provided which is
asserted on occurrence of any of the following internal events:
–Transmit holding register ready for each channel
–Receive holding register ready or FIFO full for each channel
–Change in break received status for each channel
Associated with the interrupt system are the interrupt mask register
(IMR) and the interrupt status register (ISR). The IMR can be
programmed to select only certain conditions, of the above, to cause
INTRN to be asserted. The ISR can be read by the CPU to
determine all currently active interrupting conditions. However, the
bits of the ISR are not masked by the IMR. The transmitter ready
status and the receiver ready or FIFO full status can be provided on
MPP1a, MPP1b, MPP2a, and MPP2b by setting OPCR[7]. these
outputs are not masked by IMR.
Operation ControlThe operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer. The functions performed by the CPU read and
write operations are shown in Table 1.
Mode registers 1 and 2 are accessed via an auxiliary pointer. The
pointer is set to MR1 by RESET or by issuing a reset pointer
command via the command register. Any read or write of the mode
register while the pointer is at MR1 switches the pointer to MR2 after
the read or write. The pointer then remains at MR2 so that
subsequent accesses are to MR2. To access MR1, the command
0001 of the command register must be executed.
Timing CircuitsThe timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer for each block, and
two clock selectors.
Crystal ClockThe crystal oscillator operates directly from a 3.6864MHz crystal
connected across the X1/ CLK and X2 inputs with a minimum of
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
clock is used instead of a crystal, X1 must be driven and X2 left
floating as shown in Figure 9. The clock serves as the basic timing
reference for the baud rate generator (BRG), the counter/timer, and
other internal circuits. A clock frequency, within the limits specified in
the electrical specifications, must be supplied even if the internal
BRG is not used.
Table 1. Register Addressing
NOTE: Reserved registers should never be read during normal operation since they are reserved for internal diagnostics.
ACR= Auxiliary control register SR = Status Register = Command register THR= Tx holding register
CSR= Clock select register RHR= Rx holding register
CTL= Counter/timer lower IPCR= Input port change register
CTPL= Counter/timer preset lower register ISR = Interrupt status register
CTU= Counter/timer upper IMR= Interrupt mask register
CTPU= Counter/timer preset upper register OPCR= Output port configuration register = Mode register See Table 5 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681
and SCC2698B” Philips Semiconductors ICs for Data Communications, IC-19, 1994.
BRGThe baud rate generator operates from the oscillator or external
clock input and is capable of generating 26 commonly used data
communications baud rates ranging from 50 to 115.2K baud.
used as a timer to produce a 16X clock for any other baud rate by
counting down the crystal clock or an external clock. The clock
selectors allow the independent selection, by the receiver and
transmitter, of any of these baud rates or an external timing signal.
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
periods. These clocks may be used by any or all of the receivers
and transmitters in the OCTART or may be directed to an I/O pin for
miscellaneous use.
Counter/Timer programmingThe counter timer is a 16–bit programmable divider that operates in
one of three modes: counter, timer, and time out. Timer mode generates a square wave. Counter mode generates a time delay. Time out mode counts time between received characters.
The C/T uses the numbers loaded into the Counter/Timer Lower
Register (CTPL) and the Counter/Timer Upper Register (CTPU) as
its divisor. The counter timer is controlled with six commands:
Start/Stop C/T, Read/Write Counter/Timer lower register and
Read/Write Counter/Timer upper register. These commands have
slight differences depending on the mode of operation. Please see
the detail of the commands under the CTPL/CTPU register
descriptions.
Baud Rate GenerationWhen these timers are selected as baud rates for receiver or trans-
mitter via the Clock Select register their output will be configured as
a 16x clock. Therefore one needs to program the timers to generate
a clock 16 times faster than the data rate. The formula for calculat-
ing ’n’, the number loaded to the CTPU and CTPL registers, based
on a particular input clock frequency is shown below.
For the timer mode the formula is as follows: Clockinputfrequency 16� Baudratedesired
NOTE: ‘n’ may not assume values of 0 and 1.
The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and receiv-
er state machines include divide by 16 circuits, which provide the
final frequency and provide various timing edges used in the qualify-
ing the serial data bit stream. Often this division will result in a non–
integer value: 26.3 for example. One may only program integer
numbers to a digital divider. There for 26 would be chosen. If 26.7
were the result of the division then 27 would be chosen. This gives
a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage
error of 1.14% or 1.12% respectively, well within the ability of the
asynchronous mode of operation. Higher input frequency to the
counter reduces the error effect of the fractional division
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is com-
municating may also have a small error in the precise baud rate. In
a ”clean” communications environment using one start bit, eight data
bits and one stop bit the total difference allowed between the trans-
mitter and receiver frequency is approximately 4.6%. Less than
eight data bits will increase this percentage.
Receiver and TransmitterThe Octal UART has eight full-duplex asynchronous
receiver/transmitters. The operating frequency for the receiver and
transmitter can be selected independently from the baud rate
generator, the counter/timer, or from an external input.
TransmitterThe SCC2698 is conditioned to transmit data when the transmitter is
enabled through the command register. The SCC2698 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to gen-
erate an interrupt request at MPO or MPP1 and INTRN. When the
transmitter is initially enabled the TxRDY and TxEMT bits will be set
in the status register. When a character is loaded to the transmit
FIFO the TxEMT bit will be reset. The TxEMT will not set until: 1)
the transmit FIFO is empty and the transmit shift register has fin-
ished transmitting the stop bit of the last character written to the
transmit FIFO, or 2) the transmitter is disabled and then re–enabled.
The TxRDY bit is set whenever the transmitter is enabled and the
TxFIFO is not full. Data is transferred from the holding register to
transmit shift register when it is idle or has completed transmission
of the previous character. Characters cannot be loaded into the
TxFIFO while the transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the TxFIFO.
If the transmitter is disabled, it continues operating until the charac-
ter currently being transmitted and any characters in the TxFIFO
including parity and stop bit(s) have been completed.
The transmitter can be forced to send a continuous Low condition by
issuing a send break command from the command register. The
transmitter output is returned to the normal high with a stop break
command.
The transmitter can be reset through a software command. If it is
reset, operation ceases immediately and the transmitter must be
enabled through the command register before resuming operation.
If CTS option is enabled (MR2[4] = 1), the CTSN input at MPI0 must
be Low in order for the character to be transmitted. The transmitter
will check the state of the CTS input at the beginning of each char-
acter transmitted. If it is found to be High, the transmitter will delay
the transmission of any following characters until the CTS has re-
turned to the low state. CTS going high during the serialization of a
character will not affect that character.
Transmitter “RS485 turnaround”The transmitter can also control the RTSN outputs, MPO via
MR2[5]. When this mode of operation is set, the meaning of the
MPO signal will usually be ‘end of message’. See description of the
MR2[5] bit for more detail.
Transmitter Flow controlThe transmitter may be controlled by the CTSN input when enabled
by MR2(4). The CTSN input would be connected to RTSN output of
the receiver to which it is communicating. See further description in
the MR 1 and MR2 register descriptions.
ReceiverThe SCC2698 is conditioned to receive data when enabled through
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
the bit time clock (1X clock mode). If RxD is sampled high, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still low, a valid start bit is assumed. The receiver then continues
to sample the input at one–bit time intervals at the theoretical center
of the bit. When the proper number of data bits and parity bit (if any)
have been assembled, with one half–stop bit the character will be
considered complete. The least significant bit is received first. The
data is then transferred to the Receive FIFO and the RxRDY bit in
the SR is set to a 1. This condition can be programmed to generate
an interrupt at MPO or MPP2 and INTRN. If the character length is
less than 8 bits, the most significant unused bits in the RxFIFO are
set to zero.
Receiver FIFOThe RxFIFO consists of a First–In–First–Out (FIFO) stack with a
capacity of 3 characters. Data is loaded from the receive shift regis-
ter into the topmost empty position of the FIFO. The RxRDY bit in
the status register is set whenever one or more characters are avail-
able to be read, and a FFULL status bit is set if all three (3) stack
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RxFIFO outputs the data at the top
of the FIFO. After the read cycle, the data FIFO and its associated
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.
Receiver Status BitsThere are five (5) status bits that are evaluated with each byte (or
character) received: received break, framing error, parity error, over-
run error, and change of break. The first three are appended to
each byte and stored in the RxFIFO. The last two are not necessar-
ily related to the byte being received or a byte that is in the RxFIFO.
They are however developed by the receiver state machine.
The received break, framing error, parity error and overrun error (if
any) are strobed into the RxFIFO at the received character bound-
ary, before the RxRDY status bit is set. For character mode (see
below) status reporting the SR (Status Register) indicates the condi-
tion of these bits for the character that is the next to be read from the
FIFO
The ”received break” will always be associated with a zero byte in
the RxFIFO. It means that zero character was a break character
and not a zero data byte. The reception of a break condition will
always set the ”change of break” (see below) status bit in the Inter-
rupt Status Register (ISR). The Change of break condition is reset
by a reset error status command in the command register
Break DetectionIf a break condition is detected (RxD is Low for the entire character
including the stop bit), a character consisting of all zeros will be
loaded into the RxFIFO and the received break bit in the SR is set to
1. The change of break bit also sets in the ISR The RxD input must
return to high for two (2) clock edges of the X1 crystal clock for the
receiver to recognize the end of the break condition and begin the
search for a start bit.
This will usually require a high time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to the X1
clock.
Framing ErrorA framing error occurs when a non–zero character whose parity bit
(if used) and stop; bit are zero. If RxD remains low for one half of
the bit period after the stop bit was sampled, then the receiver oper-
The framing, parity and received break status bits are reset when
the associated data byte is read from the RxFIFO since these “error”
conditions are attached to the byte that has the error
Overrun ErrorThe overrun error occurs when the RxFIFO is full, the receiver shift
register is full, and another start bit is detected. At this moment the
receiver has 4 valid characters and the start bit of the 5th has been
seen. At this point the host has approximately 6/16–bit time to read
a byte from the RxFIFO or the overrun condition will be set. The 5th
character then overruns the 4th and the 6th the 5th and so on until
an open position in the RxFIFO is seen. (“seen” meaning at least
one byte was read from the RxFIFO.)
Overrun is cleared by a use of the “error reset” command in the
command register.
The fundamental meaning of the overrun is that data has been lost.
Data in the RxFIFO remains valid. The receiver will begin placing
characters in the RxFIFO as soon as a position becomes vacant.
Note: Precaution must be taken when reading an overrun FIFO.
There will be 3 valid characters in the receiver FIFO. There will be
one character in the receiver shift register. However it will NOT be
known if more than one “over–running” character has been received
since the overrun bit was set. The 4th character is received and
read as valid but it will not be known how many characters were lost
between the two characters of the 3rd and 4th reads of the RxFIFO
The ”Change of break” means that either a break has been detected
or that the break condition has been cleared. This bit is available in
the ISR. The break change bit being set in the ISR and the received
break bit being set in the SR will signal the beginning of a break. At
the termination of the break condition only the change of break in
the ISR will be set. After the break condition is detected the ter-
mination of the break will only be recognized when the RxD input
has returned to the high state for two successive edges of the 1x
clock; 1/2 to 1 bit time (see above).
The receiver is disabled by reset or via CR commands. A disabled
receiver will not interrupt the host CPU under any circumstance in
the normal mode of operation. If the receiver is in the multi–drop or
special mode, it will be partially enabled and thus may cause an
interrupt. Refer to section on Wake–Up and the register description
for MR1 for more information.
Receiver Status Modes (block and character)In addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character–by–charac-
ter basis; the status applies only to the character at the top of the
FIFO. In the ‘block’ mode, the status provided in the SR for these
three bits is the logical–OR of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command was issued.
In either mode reading the SR does not affect the FIFO. The FIFO
is ‘popped’ only when the RxFIFO is read. Therefore the status
register should be read prior to reading the FIFO.
Receiver Flow ControlThe receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Note: The transmitter may also control the “RTSN” pin. When un-
der transmitter control the meaning is completely changed. The
meaning is the transmission has ended. This signal is usually used
to switch (turnaround) a bi–directional driver from transmit to re-
ceive.
If the receiver is disabled, the FIFO characters can be read. Howev-
er, no additional characters can be received until the receiver is
enabled again. If the receiver is reset, the FIFO and all of the re-
ceiver status, and the corresponding output ports and interrupt are
reset. No additional characters can be received until the receiver is
enabled again.
Receiver Time–out ModeThe time–out mode uses the received data stream to control the
counter. Each time a received character is transferred from the shift
register to the RxFIFO, the counter is restarted. If a new character
is not received before the counter reaches zero count, the counter
ready bit is set, and an interrupt can be generated. This mode can
be used to indicate when data has been left in the RxFIFO for more
than the programmed time limit. Otherwise, if the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU may not know
there is data left in the FIFO. The CTPU and CTPL value would be
programmed for just over one character time, so that the CPU would
be interrupted as soon as it has stopped receiving continuous data.
This mode can also be used to indicate when the serial line has
been marking for longer than the programmed time limit. In this
case, the CPU has read all of the characters from the FIFO, but the
last character received has started the count. If there is no new
data during the programmed time interval, the counter ready bit will
get set, and an interrupt can be generated.
The time–out mode is enabled by writing the appropriate command
to the command register. Writing an ‘Ax’ to CRA or CRB will invoke
the time–out mode for that channel. Writing a ‘Cx’ to CRA or CRB
will disable the time–out mode. The time–out mode should only be
used by one channel at once, since it uses the C/T. If, however, the
time–out mode is enabled from both receivers, the time–out will
occur only when both receivers have stopped receiving data for the
time–out period. CTPU and CTPL must be loaded with a value
greater than the normal receive character period. The time–out
mode disables the regular START/STOP Counter commands and
puts the ca/T into counter mode under the control of the received
data stream. Each time a received character is transferred from the
shift register to the RxFIFO, the C/T is stopped after 1 C/T clock,
reloaded with the value in CTPU and CTPL and then restarted on
the next C/T clock. If the C/T is allowed to end the count before a
new character has been received, the counter ready bit, ISR[3], will
be set. If IMR[3] is set, this will generate an interrupt. Receiving a
character after the C/T has timed out will clear the counter ready bit,
ISR[3], and the interrupt. Invoking the ‘Set Time–out Mode On’
command, CRx = ‘Ax’, will also clear the counter ready bit and stop
the counter until the next character is received.
This mode is cleared by issuing the “Disable Time–out Mode” com-
mand (C0) in the command register.
Time Out Mode CautionWhen operating in the special time out mode, it is possible to gener-
ate what appears to be a “false interrupt” – an interrupt without a
cause. This may result when a time–out interrupt occurs and then,
BEFORE the interrupt is serviced, another character is received,
the receiver, thereby withdrawing its interrupt. If, at this time, the
interrupt service begins for the previously seen interrupt, a read of
the ISR will show the “Counter Ready” bit not set. If nothing else is
interrupting, this read of the ISR will return a x’00 character.
Receiver Reset and DisableReceiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected. A receiver reset will discard
the present shift register data, reset the receiver ready bit (RxRDY),
clear the status of the byte at the top of the FIFO and re-align the
FIFO read/write pointers. This has the appearance of “clearing or
flushing” the receiver FIFO. In fact, the FIFO is NEVER cleared!
The data in the FIFO remains valid until overwritten by another
received character. Because of this, erroneous reading or extra
reads of the receiver FIFO will miss-align the FIFO pointers and
result in the reading of previously read data. A receiver reset will
re-align the pointers.
WAKE-UP MODEIn addition to the normal transmitter and receiver operation
described above, the Octal UART incorporates a special mode
which provides automatic wake-up of the receiver through address
frame recognition for multiprocessor communications. This mode is
selected by programming bits MR1[4:3] to ‘11’.
In this mode of operation, a ‘master’ station transmits an address
character followed by data characters for the addressed ‘slave’
station. The slave stations, whose receivers are normally disabled,
examine the received data stream and ‘wake-up’ the CPU [by
setting RxRDY) only upon receipt of an address character. The CPU
compares the received address to its station address and enables
the receiver if it wishes to receive the subsequent data characters.
Upon receipt of another address character, the CPU may disable the
receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, an address/data (A/D) bit, and the programmed
number of stop bits. The polarity of the transmitted A/D bit is
selected by the CPU by programming bit MR1[2]; MR1[2] = 0
transmits a zero in the A/D bit position which identifies the
corresponding data bits as data; MR1[2] = 1 transmits a one in the
A/D bit position which identifies the corresponding data bits as an
address. The CPU should program the mode register prior to
loading the corresponding data bits in the THR.
While in this mode, the receiver continuously looks at the received
data stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character in the RHR FIFO if the
received A/D bit is a one, but discards the received character if the
received A/D bit is a zero. If enabled, all received characters are
then transferred to the CPU via the RHR. In either case, the data
bits are loaded in the data FIFO while the A/D bit is loaded in the
status FIFO position normally used for parity error (SR[5]). Framing
error, overrun error, and break detect operate normally whether or
not the receiver is enabled.
The CTS, RTS, CTS Enable Tx signalsCTS (Clear To Send) is usually meant to be a signal to the transmit-
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
receiver indicating that the receiver is ready to receive data. It is
also active low and is, thus, called RTSN. RTSN is on pin MPO. A
receiver’s RTS output will usually be connected to the CTS input of
the associated transmitter. Therefore, one could say that RTS and
CTS are different ends of the same wire!
MR2(4) is the bit that allows the transmitter to be controlled by the
CTS pin ( MPI0). When this bit is set to one AND the CTS input is
driven high, the transmitter will stop sending data at the end of the
present character being serialized. It is usually the RTS output of
the receiver that will be connected to the transmitter’s CTS input.
The receiver will set RTS high when the receiver FIFO is full AND
the start bit of the fourth character is sensed. Transmission then
stops with four valid characters in the receiver. When MR2(4) is set
to one, CTSN must be at zero for the transmitter to operate. If
MR2(4) is set to zero, the MPI0 pin will have no effect on the opera-
tion of the transmitter.
MR1(7) is the bit that allows the receiver to control MPO. When
MPO is controlled by the receiver, the meaning of that pin will be
RTS. However, a point of confusion arises in that MPO may also be
controlled by the transmitter. When the transmitter is controlling this
pin, its meaning is not RTS at all. It is, rather, that the transmitter
has finished sending its last data byte. Programming the MPO pin
to be controlled by the receiver and the transmitter at the same time
is allowed, but would usually be incompatible.
RTS can also be controlled by the commands 1000 and 1001 in the
command register. RTS is expressed at the MP0 pin which is still an
output port. Therefore, the state of MP0 should be set low (either by
commands of the CR register or by writing to the Output Port Con-
figuration Register) for the receiver to generate the proper RTS sig-
nal. The logic at the output is basically a NAND of the MP0 bit
register and the RTS signal as generated by the receiver. When the
RTS flow control is selected via the MR1(7) bit the state of the MP0
register is not changed. Terminating the use of “Flow Control” (via
the MR registers) will return the MP0 pin to the control of the MP0
register.
Transmitter Disable NoteWhen the TxEMT bit is set the sequence of instructions: enable
transmitter — load transmit holding register — disable transmitter
will often result in nothing being sent. In the condition of the TxEMT
being set do not issue the disable until the TxRDY bit goes active
again after the character is loaded to the TxFIFO. The data is not
sent if the time between the end of loading the transmit holding reg-
ister and the disable command is less that 3/16 bit time in the 16x
mode. One bit time in the 1x mode.
This is sometimes the condition when the RS485 automatic “turn-
around” is enabled . It will also occur when only one character is to
be sent and it is desired to disable the transmitter immediately after
the character is loaded.
In general, when it is desired to disable the transmitter before the
last character is sent AND the TxEMT bit is set in the status register
be sure the TxRDY bit is active immediately before issuing the
transmitter disable instruction. (TxEMT is always set if the transmit-
ter has underrun or has just been enabled), TxRDY sets at the end
of the “start bit” time. It is during the start bit that the data in the
transmit holding register is transferred to the transmit shift register.
MULTI-PURPOSE INPUT PINThe inputs to this unlatched 8-bit port for each block can be read by
the CPU, by performing a read operation as shown in Table 1. A
High input results in a logic one, while a Low input results in a logic
zero. When the input port pins are read on the 84-pin LLCC, they
will appear on the data bus in alternating pairs (i.e., DB0 = MP10a,
DB1 = MPI1a, DB2 = MPI0b, DB3 = MPI1b, DB4 = MPP1a, DB5 =
MPP2a, DB6 = MPP1b, DB7 = MPP2b. Although this example is
shown for input port ‘A’, all ports will have a similar order).
The MPI pin can be programmed as an input to one of several Octal
UART circuits. The function of the pin is selected by programming
the appropriate control register. Change-of-state detectors are
provided for MPI0 and MPI1 for each channel in each block. A
High-to-Low or Low-to-High transition of the inputs lasting longer
than 25 to 50μs sets the MPI change-of-state bit in the interrupt
status register. The bit is cleared via a command. The
change-of-state can be programmed to generate an interrupt to the
CPU by setting the corresponding bit in the interrupt mask register.
The input port pulse detection circuitry uses a 38.4KHz sampling
clock, derived from one of the baud rate generator taps. This
produces a sampling period of slightly more than 25μs (assuming a
3.6864MHz oscillator input). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples be observed at the new logic level. As a
consequence, the minimum duration of the signal change is 25μs if
the transition occurs coincident with the first sample pulse. (The
50μs time refers to the condition where the change-of-state is just
missed and the first change of state is not detected until after an
additional 25μs.)
MULTI-PURPOSE I/O PINSThe multi-purpose pins (MPP) can be programmed as inputs or
outputs using OPCR[7]. When programmed as inputs, the functions
of the pins are selected by programming the appropriate control
registers. When programmed as outputs, the two MPP1 pins (per
block) will provide the transmitter ready (TxRDY) status for each
channel and the MPP2 pins will provide the receiver ready or FIFO
full (RxRDY/FFULL) status for each channel.
MULTI-PURPOSE OUTPUT PINThis pin can be programmed to serve as a request-to-send output,
the counter/timer output, the output for the 1X or 16X transmitter or
receiver clocks, the TxRDY output or the RxRDY/FFULL output (see
OPCR [2:0] and OPCR [6:4] – MPO Output Select).
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
REGISTERSThe operation of the Octal UART is programmed by writing control
words into the appropriate registers. Operational feedback is
provided via status registers which can be read by the CPU.
Addressing of the registers is described in Table 1.
The bit formats of the Octal UART registers are depicted in Table 2.
These are shown for block A. The bit format for the other blocks is
the same.
MR1 – Mode Register 1MR1 is accessed when the MR pointer points to MR1. The pointer is
set to MR1 by RESET or by a set pointer command applied via the
CR. After reading or writing MR1, the pointers are set at MR2.
MR1[7] – Receiver Request-to-Send ControlThis bit controls the deactivation of the RTSN output (MPO) by the
receiver. This output is manually asserted and negated by
commands applied via the command register. MR1[7] = 1 causes
RTSN to be automatically negated upon receipt of a valid start bit if
the receiver FIFO is full. RTSN is reasserted when an empty FIFO
position is available. This feature can be used to prevent overrun in
the receiver by using the RTSN output signal to control the CTS
input of the transmitting device.
MR1[6] – Receiver Interrupt SelectThis bit selects either the receiver ready status (RxRDY) or the FIFO
full status (FFULL) to be used for CPU interrupts.
MR1[5] – Error Mode SelectThis bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break). In the character mode, status is provided
on a character-by-character basis; the status applies only to the
character at the top of the FIFO. In the block mode, the status
provided in the SR for these bits is the accumulation (logical-OR) of
the status for all characters coming to the top of the FIFO since the
last reset error command was issued.
MR1[4:3] – Parity Mode SelectIf ‘with parity’ or ‘force parity’ is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the channel to operate in the
special wake-up mode.
MR1[2] – Parity Type SelectThis bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special ‘wake-up’ mode, it
selects the polarity of the transmitted A/D bit.
MR1[1:0] – Bits Per Character SelectThis field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
MR2 – Mode Register 2MR2 is accessed when the channel MR pointer points to MR2,
which occurs after any access to MR1. Accesses to MR2 do not
change the pointer.
MR2[7:6] – Mode SelectThe Octal UART can operate in one of four modes. MR2[7:6] = 00 is
the normal mode, with the transmitter and receiver operating
independently. MR2[7:6] = 01 places the channel in the automatic
echo mode, which automatically re-transmits the received data. The
following conditions are true while in automatic echo mode: Received data is re-clocked and retransmitted on the TxD output. The receive clock is used for the transmitter. The receiver must be enabled, but the transmitter need not be
enabled. The TxRDY and TxEMT status bits are inactive. The received parity is checked, but is not regenerated for
transmission, i.e., transmitted parity bit is as received. Character framing is checked, but the stop bits are retransmitted as
received. A received break is echoed as received until the next valid start bit
is detected. CPU-to-receiver communication continues normally, but the
CPU-to-transmitter link is disabled.
Two diagnostic modes can also be selected. MR2[7:6] = 10 selects
local loopback mode. In this mode: The transmitter output is internally connected to the receiver
input. The transmit clock is used for the receiver. The TxD output is held high. The RxD input is ignored. The transmitter must be enabled, but the receiver need not be
enabled. CPU to transmitter and receiver communications continue
normally.
The second diagnostic mode is the remote loopback mode, selected
by MR2[7:6] = 11. In this mode: Received data is re-clocked and retransmitted on the TXD
output. The receive clock is used for the transmitter. Received data is not sent to the local CPU, and the error status
conditions are inactive. The received parity is not checked and is not regenerated for
transmission, i.e., the transmitted parity bit is as received. The receiver must be enabled, but the transmitter need not be
enabled. Character framing is not checked, and the stop bits are
retransmitted as received. A received break is echoed as received until the next valid start
bit is detected.
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected, the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes; if the
deselection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop bit has been retransmitted.
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Table 2. Register Bit Formats
MR1 (Mode Register 1)
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR2 (Mode Register 2)
CR (Command Register)
SR (Status Register)
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Table 2. Register Bit Formats (Continued)
CSR (Clock Select Register)* See Table 5 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” Philips Semiconductors ICs for Data Communications, IC-19, 1994.
OPCR (Output Port Configuration Register) This register controls the MPP I/O pins and the MPO multi-purpose output pins.
ACR (Auxiliary Control Register)
IPCR (Input Port Change Register)
ISR (Interrupt Status Register)
IMR (Interrupt Mask Register)
CTPU (Counter/Timer Upper Register)
CTPU (Counter/Timer Lower Register)
IPR (Input Port Register) MPP and MPI Pins
Philips Semiconductors Product specification
SCC2698BEnhanced octal universal asynchronous
receiver/transmitter (Octal UART)
MR2[5] – Transmitter Request-to-Send ControlCAUTION: When the transmitter controls the OP pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
commands issued via the command register. MR2[5] set to 1
caused the RTSN to be reset automatically one bit time after the
character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
bits) if a previously issued transmitter disable is pending. This
feature can be used to automatically terminate the transmission as
follows: Program the auto-reset mode: MR2[5]=1 Enable transmitter, if not already enabled Assert RTSN via command Send message Disable the transmitter after the last byte of the message is
loaded to the TxFIFO. At the time the disable command is
issued, be sure that the transmitter ready bit is on and the
transmitter empty bit is off. If the transmitter empty bit is on
(indicating the transmitter is underrun) when the disable is
issued, the last byte will not be sent. The last character will be transmitted and the RTSN will be reset
one bit time after the last stop bit is sent.
NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
immediately after the transmitter is enabled from the disabled or
reset state. When using the above procedure with the transmitter in
the underrun condition, the issuing of the transmitter disable must be
delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
MR2[4] – Clear-to-Send ControlThe sate of this bit determines if the CTSN input (MPI) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the sate of CTSN
each time it is ready to send a character. If it is asserted (Low), the
character is transmitted. If it is negated (High), the TxD output
remains in the marking state and the transmission is delayed until
CTSN goes Low. Changes in CTSN, while a character is being
transmitted do not affect the transmission of that character. This
feature can be used to prevent overrun of a remote receiver.
MR2[3:0] – Stop Bit Length SelectThis field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character length of 5 bits, 1–1/16 to
2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a mark condition at the center of
the first stop bit position (one bit time after the last data bit, or after
the parity bit if parity is enabled). If an external 1X clock is used for
the transmitter, MR2[3] = 0 selects one stop bit and MR2[3] = 1
selects two stop bits to be transmitted.
CSR – Clock Select Register
Table 3. Baud RateThe receiver clock is always a 16X clock, except for CSR[7:4] =
1111. When MPP2 is selected as the input, MPP2a is for channel a
and MPP2b is for channel b. See Table 5.
CSR[7:4] – Receiver Clock SelectWhen using a 3.6864MHz crystal or external clock input, this field
selects the baud rate clock for the receiver as shown in Table 3.
CSR[3:0] – Transmitter Clock SelectThis field selects the baud rate clock for the transmitter. The field
definition is as shown in Table 3, except as follows:
CSR[3:0] ACR[7] = 0 ACR[7] = 11 1 1 0 MPP1 – 16X MPP1 – 16X
1 1 1 1 MPP1 – 1X MPP1 – 1X
When MPP1 is selected as the input, MPP1a is for channel a and
MPP1b is for channel b.
CR – Command RegisterCR is used to write commands to the Octal UART.
CR[7:4] – Miscellaneous CommandsThe encoded value of this field can be used to specify a single
command as follows:
NOTE: Access to the upper four bits of the command register
should be separated by three (3) edges of the X1 clock.
0000 No command.
0001 Reset MR pointer. Causes the MR pointer to point to
MR1.
0010 Reset receiver. Resets the receiver as if a hardware
reset had been applied. The receiver is disabled and the
FIFO pointer is reset to the first location.
0011 Reset transmitter. Resets the transmitter as if a hardware
reset had been applied.
0100 Reset error status. Clears the received break, parity
error, framing error, and overrun error bits in the status
register (SR[7:4]}. Used in character mode to clear OE
status (although RB, PE, and FE bits will also be
