SCC2692AE1A44 ,Dual asynchronous receiver/transmitter (DUART)FEATURES• Maximum data transfer rates: 1X – 1MB/sec, 16X – 125kB/sec• Dual full-duplex asynchronous ..
SCC2692AE1A44 ,Dual asynchronous receiver/transmitter (DUART)FEATURES• Maximum data transfer rates: 1X – 1MB/sec, 16X – 125kB/sec• Dual full-duplex asynchronous ..
SCC2692AE1A44 ,Dual asynchronous receiver/transmitter (DUART)applications• Quadruple buffered receiver data register• Start-end break interrupt/status• Programm ..
SCC2692AE1B44 ,Dual asynchronous receiver/transmitter (DUART)FEATURES• Maximum data transfer rates: 1X – 1MB/sec, 16X – 125kB/sec• Dual full-duplex asynchronous ..
SCC2692AE1N40 ,Dual asynchronous receiver/transmitter (DUART)INTEGRATED CIRCUITSSCC2692Dual asynchronous receiver/transmitter(DUART)Product specification 1998 S ..
SCC2698BC1A84 ,Enhanced octal universal asynchronous receiver/transmitter (Octal UART)PIN CONFIGURATIONSV 1 64 RxDaCC11 1 75X2 2 63 TxDa12 7462 RxDcX1/CLK 361 TxDcD0 460 RxDe PLCCD1 5D2 ..
SG105 , PHOTOINTERRUPTERS
SG-105 , Photointerrupters(Reflective)
SG105F , PHOTOINTERRUPTERS
SG-105F , Photointerrupters(Reflective)
SG107F3 , Reflective sensor combines a GaAs IRED with a high-sensitivity phototransistor
SG-107F3 , Photointerrupters(Reflective)
SCC2692AC1A44-SCC2692AC1N28.-SCC2692AC1N40-SCC2692AE1A44
Dual asynchronous receiver/transmitter (DUART)
Product specification
Supersedes data of 1998 Feb 19
IC19 Data Handbook
1998 Sep 04
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
DESCRIPTIONThe Philips Semiconductors SCC2692 Dual Universal
Asynchronous Receiver/Transmitter (DUART) which is compatible
with the SCN2681. It is a single-chip CMOS-LSI communications
device that provides two full-duplex asynchronous
receiver/transmitter channels in a single package. It interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the receiver buffer is full.
Also provided on the SCC2692 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
FEATURES Dual full-duplex asynchronous receiver/transmitters Quadruple buffered receiver data register Programmable data format
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16-bit increments 16-bit programmable Counter/Timer Programmable baud rate for each receiver and transmitter
selectable from:
22 fixed rates: 50 to 115.2k baud
Non-standard rates to 115.2Kb
Non-standard user-defined rate derived from programmable
counter/timer
External 1X or 16X clock Parity, framing, and overrun error detection False start bit detection Line break detection and generation Programmable channel mode
Normal (full-duplex)
Automatic echo
Local loopback
Remote loopback
Multidrop mode (also called ‘wake-up’ or ‘9-bit’) Multi-function 7-bit input port
Can serve as clock or control inputs
Change of state detection on four inputs
Inputs have typically >100k pull-up resistors Multi-function 8-bit output port
Individual bit set/reset capability
Outputs can be programmed to be status/interrupt signals Versatile interrupt system
Single interrupt output with eight maskable interrupting
conditions
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs Maximum data transfer rates: 1X – 1MB/sec, 16X – 125kB/sec Automatic wake-up mode for multidrop applications Start-end break interrupt/status Detects break which originates in the middle of a character On-chip crystal oscillator Power down mode Receiver timeout mode Commercial and industrial temperature range versions TTL compatible Single +5V power supply
ORDERING INFORMATION
NOTE:
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
Figure 1. Pin Configurations
ABSOLUTE MAXIMUM RATINGS1
NOTES: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAM
Figure 2. Block Diagram
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
PIN DESCRIPTION
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
DC ELECTRICAL CHARACTERISTICS1, 2, 3
NOTES: Parameters are valid over specified temperature range. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate. Typical values are at +25°C, typical supply voltages, and typical processing parameters. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7KΩ to VCC. All outputs are disconnected. Inputs are switching between CMOS levels of VCC -0.2V and VSS + 0.2V. TA > 0°C TA < 0°C See UART application note for 5μA.
AC CHARACTERISTICS1, 2, 4
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
AC CHARACTERISTICS (Continued)1, 2, 4
NOTES: Parameters are valid over specified temperature range. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate. Typical values are at +25°C, typical supply voltages, and typical processing parameters. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7KΩ to VCC. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ORed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid. Guaranteed by characterization of sample units. Minimum frequencies are not tested but are guaranteed by design. 325ns maximum for TA > 70°C.
10. Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz. Crystal frequencies 2 to 4 MHz.
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAMThe SCC2692 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port. Refer
to the Block Diagram.
Data Bus BufferThe data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
Operation ControlThe operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer.
Interrupt ControlA single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR). The IMR can be
programmed to select only certain conditions to cause INTRN to be
asserted. The ISR can be read by the CPU to determine all currently
active interrupting conditions.
Outputs OP3-OP7 can be programmed to provide discrete interrupt
outputs for the transmitter, receivers, and counter/timer.
TIMING CIRCUITS
Crystal ClockThe timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and four clock
selectors. The crystal oscillator operates directly from a crystal
connected across the X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may be connected to
X1/CLK. The clock serves as the basic timing reference for the Baud
Rate Generator (BRG), the counter/timer, and other internal circuits.
A clock signal within the limits specified in the specifications section
of this data sheet must always be supplied to the DUART.
If an external clock is used instead of a crystal, X1 should be driven
using a configuration similar to the one in Figure 7.
BRGThe baud rate generator operates from the oscillator or external
clock input and is capable of generating 23 commonly used data
communications baud rates ranging from 50 to 130.4K baud. A
3.6864MHz crystal or external clock must be used to get the
standard baud rate. The clock outputs from the BRG are at 16X the
actual baud rate. The counter/timer can be used as a timer to
produce a 16X clock for any other baud rate by counting down the
crystal clock or an external clock. The four clock selectors allow the
independent selection, for each receiver and transmitter, of any of
these baud rates or external timing signal.
Counter/Timer (C/T) In the timer mode it generates a square wave. In the counter mode it generates a time delay. In the time out mode it monitors the receiver data flow and signals
data flow has paused. In the time out mode the receiver controls
the starting/stopping of the C/T.
The counter operates as a down counter and sets its output bit in
the ISR (Interrupt Status Register) each time it passes through 0.
The output of the counter/timer may be seen on one of the OP pins
or as an Rx or Tx clock.
The Timer/Counter is controlled with six (6) “commands”; Start C/T,
Stop C/T, write C/T, preset registers, read C/T value, set or reset
time out mode.
Please see the detail of the commands under the Counter/Timer
register descriptions.
Communications Channels A and BEach communications channel of the SCC2692 comprises a
full-duplex asynchronous receiver/transmitter (UART). The operating
frequency for each receiver and transmitter can be selected
independently from the baud rate generator, the counter/timer, or
from an external input.
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD
output pin. The receiver accepts serial data on the RxD pin,
converts this serial input to parallel format, checks for start bit, stop
bit, parity bit (if any), or break condition and sends an assembled
character to the CPU.
Input PortThe inputs to this unlatched 7-bit port can be read by the CPU by
performing a read operation at address H’D’. A High input results in
a logic 1 while a Low input results in a logic 0. D7 will always read
as a logic 1. The pins of this port can also serve as auxiliary inputs
to certain portions of the DUART logic.
Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High
transition of these inputs, lasting longer than 25 - 50μs, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.
The input port pulse detection circuitry uses a 38.4KHz sampling
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25μs (this assumes that
the clock input is 3.6864MHz). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25μs if
the transition occurs “coincident with the first sample pulse”. The
50μs time refers to the situation in which the change-of-state is “just
missed” and the first change-of-state is not detected until 25μs later.
All the IP pins have a small pull-up device that will source 1 to 4 A
of current from VCC. These pins do not require pull-up devices or
VCC connections if they are not used.
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
conditions of the UART. When this 8-bit port is used as a general
purpose output, the pins so defined will assume the compliment of
the associated bit in the Output Port Register (OPR). OPR(n) = 1
results in OP(n) = Low and vice versa. Bits of the OPR can be
individually set and reset. A bit is set by performing a write operation
at address H’E’ with the accompanying data specifying the bits to be
reset (1 = set, 0 = no change). Likewise, a bit is reset by a write at
address H’F’ with the accompanying data specifying the bits to be
reset (1 = reset, 0 = no change).
Outputs can be also individually assigned specific functions by
appropriate programming of the Channel A mode registers (MR1A,
MR2A), the Channel B mode registers (MR1B, MR2B), and the
Output Port Configuration Register (OPCR).
Output ports are driven high on hardware reset. Please note that
these pins drive both high and low. HOWEVER when they are
programmed to represent interrupt type functions (such as receiver
ready, transmitter ready or counter/timer ready) they will be switched
to an open drain configuration in which case an external pull-up
device would be required.
OPERATION
TransmitterThe SCC2692 is conditioned to transmit data when the transmitter is
enabled through the command register. The SCC2692 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
generate an interrupt request at OP6 or OP7 and INTRN. When a
character is loaded into the Transmit Holding Register (THR), the
above conditions are negated. Data is transferred from the holding
register to transmit shift register when it is idle or has completed
transmission of the previous character. The TxRDY conditions are
then asserted again which means one full character time of buffering
is provided. Characters cannot be loaded into the THR while the
transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the THR, the TxD output remains High
and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the THR.
If the transmitter is disabled, it continues operating until the
character currently being transmitted is completely sent out. The
transmitter can be forced to send a continuous Low condition by
issuing a send break command.
The transmitter can be reset through a software command. If it is
reset, operation ceases immediately and the transmitter must be
enabled through the command register before resuming operation.
If CTS operation is enable, the CTSN input must be Low in order for
the character to be transmitted. If it goes High in the middle of a
transmission, the character in the shift register is transmitted and
TxDA then remains in the marking state until CTSN goes Low. The
transmitter can also control the deactivation of the RTSN output.
(if any) are completely transmitted, if the transmitter has been
disabled.
ReceiverThe SCC2692 is conditioned to receive data when enabled through
the command register. The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16X
clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of
the bit time clock (1X clock mode). If RxD is sampled High, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still Low, a valid start bit is assumed and the receiver continues to
sample the input at one bit time intervals at the theoretical center of
the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
the Receive Holding Register (RHR) and the RxRDY bit in the SR is
set to a 1. This condition can be programmed to generate an
interrupt at OP4 or OP5 and INTRN. If the character length is less
than 8 bits, the most significant unused bits in the RHR are set to
zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains Low for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).
The parity error, framing error, and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected (RxD is Low for the
entire character including the stop bit), a character consisting of all
zeros will be loaded into the RHR and the received break bit in the
SR is set to 1. The RxD input must return to high for two (2) clock
edges of the X1 crystal clock for the receiver to recognize the end of
the break condition and begin the search for a start bit. This will
usually require a high time of one X1 clock period or 3 X1
edges since the clock of the controller is not synchronous to
the X1 clock.
Receiver FIFOThe RHR consists of a First-In-First-Out (FIFO) stack with a
capacity of three characters. Data is loaded from the receive shift
register into the topmost empty position of the FIFO. The RxRDY bit
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all three stack
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.
Receiver Status BitsIn addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO.
In the ‘block’ mode, the status provided in the SR for these three bits
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
mode reading the SR does not affect the FIFO. The FIFO is
‘popped’ only when the RHR is read. Therefore the status register
should be read prior to reading the FIFO.
If the FIFO is full when a new character is received, that character is
held in the receive shift register until a FIFO position is available. If
an additional character is received while this state exits, the
contents of the FIFO are not affected; the character previously in the
shift register is lost and the overrun error status bit (SR[4] will be
set-upon receipt of the start bit of the new (overrunning) character.
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
becomes available, the RTSN output will be re-asserted
automatically. This feature can be used to prevent an overrun, in the
receiver, by connecting the RTSN output to the CTSN input of the
transmitting device.
Receiver Reset and DisableReceiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected. A receiver reset will discard
the present shift register data, reset the receiver ready bit (RxRDY),
clear the status of the byte at the top of the FIFO and re-align the
FIFO read/write pointers. This has the appearance of “clearing or
flushing” the receiver FIFO. In fact, the FIFO is NEVER cleared!
The data in the FIFO remains valid until overwritten by another
received character. Because of this, erroneous reading or extra
reads of the receiver FIFO will miss-align the FIFO pointers and
result in the reading of previously read data. A receiver reset will
re-align the pointers.
Receiver Timeout ModeThe timeout mode uses the received data stream to control the
counter/timer. Each time a received character is transferred from the
shift register to the RHR, the counter is restarted. If a new character
is not received before the counter reaches zero count, the counter
ready bit is set, and an interrupt can be generated. This mode can
be used to indicate when data has been left in the Rx FIFO for more
than the programmed time limit. Otherwise, if the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU may not know
there is data left in the FIFO. The CTU and CTL value would be
programmed for just over one character time, so that the CPU would
be interrupted as soon as it has stopped receiving continuous data.
This mode can also be used to indicate when the serial line has
been marking for longer than the programmed time limit. In this
case, the CPU has read all of the characters from the FIFO, but the
last character received has started the count. If there is no new data
during the programmed time interval, the counter ready bit will get
set, and an interrupt can be generated.
The timeout mode is enabled by writing the appropriate command to
the command register. Writing an ‘Ax’ to CRA or CRB will invoke the
timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will
disable the timeout mode. The timeout mode should only be used by
one channel at once, since it uses the C/T. CTU and CTL must be
loaded with a value greater than the normal receive character
period. The timeout mode disables the regular START/STOP
Counter commands and puts the C/T into counter mode under the
control of the received data stream. Each time a received character
is transferred from the shift register to the RHR, the C/T is stopped
after 1 C/T clock, reloaded with the value in CTU and CTL and then
restarted on the next C/T clock. If the C/T is allowed to end the
count before a new character has been received, the counter ready
bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt.
Since receiving a character after the C/T has timed out will clear the
counter ready bit, ISR[3], and the interrupt. Invoking the ‘Set
Timeout Mode On’ command, CRx = ‘Ax’, will also clear the counter
ready bit and stop the counter until the next character is received.
This mode is reset by the “Disable Time-out Mode” command (CR
x’C0) must be used.
Time Out Mode CautionWhen operating in the special time out mode, it is possible to
generate what appears to be a “false interrupt”, i.e., an interrupt
without a cause. This may result when a time-out interrupt occurs
and then, BEFORE the interrupt is serviced, another character is
received, i.e., the data stream has started again. (The interrupt
latency is longer than the pause in the data strea.) In this case,
when a new character has been receiver, the counter/timer will be
restarted by the receiver, thereby withdrawing its interrupt. If, at this
time, the interrupt service begins for the previously seen interrupt, a
read of the ISR will show the “Counter Ready” bit not set. If nothing
else is interrupting, this read of the ISR will return a x’00 character.
Multidrop ModeThe DUART is equipped with a receiver wake-up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3]
or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode
of operation, a ‘master’ station transmits an address character
followed by data characters for the addressed ‘slave’ station. The
slave stations, with receivers that are normally disabled, examine
the received data stream and ‘wake-up’ the CPU (by setting
RxRDY) only upon receipt of an address character. The CPU
compares the received address to its station address and enables
the receiver if it wishes to receive the subsequent data characters.
Upon receipt of another address character, the CPU may disable the
receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted A/D
bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which
identifies the corresponding data bits as data while
MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which
identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bits into the THR.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RHR FIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RHR. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
Table 1. SCC2692 Register Addressing* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
Table 2. Register Bit Formats
NOTE:*In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
* See Table 6 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” in application notes elsewhere in this publication
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
Table 2. Register Bit Formats (Continued)
NOTE:The level at the OP pin is the inverse of the bit in the OPR register.
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
PROGRAMMINGThe operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1X by
RESET or by issuing a ‘reset pointer’ command via the
corresponding command register. Any read or write of the mode
register while the pointer is at MR1X, switches the pointer to MR2X.
The pointer then remains at MR2X, so that subsequent accesses
are always to MR2X unless the pointer is reset to MR1X as
described above.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions. The reserved registers
at addresses H‘02’ and H‘OA’ should never be read during normal
operation since they are reserved for internal diagnostics.
MR1A – Channel A Mode Register 1MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRA. After reading or writing MR1A, the pointer will point
to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send ControlThis bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full.
However, OPR[0] is not reset and RTSAN will be asserted again
when an empty FIFO position is available. This feature can be used
for flow control to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input of the transmitting
device.
MR1A[6] – Channel A Receiver Interrupt SelectThis bit selects either the Channel A receiver ready status (RxRDY)
or the Channel A FIFO full status (FFULL) to be used for CPU
interrupts. It also causes the selected bit to be output on OP4 if it is
programmed as an interrupt output via the OPCR.
MR1A[5] – Channel A Error Mode SelectThis bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block’
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
MR1A[4:3| – Channel A Parity Mode SelectIf ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type SelectThis bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1A[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it selects
the polarity of the A/D bit.
MR1A[1:0] – Channel A Bits Per Character SelectThis field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
MR2A – Channel A Mode Register 2MR2A is accessed when the Channel A MR pointer points to MR2,
which occurs after any access to MR1A. Accesses to MR2A do not
change the pointer.
MR2A[7:6] – Channel A Mode SelectEach channel of the DUART can operate in one of four modes.
MR2A[7:6] = 00 is the normal mode, with the transmitter and
receiver operating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically
re-transmits the received data. The following conditions are true
while in automatic echo mode: Received data is re-clocked and retransmitted on the TxDA out-
put. The receive clock is used for the transmitter. The receiver must be enabled, but the transmitter need not be
enabled. The Channel A TxRDY and TxEMT status bits are inactive. The received parity is checked, but is not regenerated for trans-
mission, i.e., transmitted parity bit is as received. Character framing is checked, but the stop bits are retransmitted
as received. A received break is echoed as received until the next valid start
bit is detected. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
Two diagnostic modes can also be configured. MR2A[7:6] = 10
selects local loopback mode. In this mode: The transmitter output is internally connected to the receiver
input. The transmit clock is used for the receiver. The TxDA output is held High. The RxDA input is ignored. The transmitter must be enabled, but the receiver need not be
enabled. CPU to transmitter and receiver communications continue nor-
mally.
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART) Received data is re-clocked and retransmitted on the TxDA out-
put. The receive clock is used for the transmitter. Received data is not sent to the local CPU, and the error status
conditions are inactive. The received parity is not checked and is not regenerated for
transmission, i.e., transmitted parity is as received. The receiver must be enabled. Character framing is not checked, and the stop bits are retrans-
mitted as received. A received break is echoed as received until the next valid start
bit is detected.
The user must exercise care when switching into and out of the
various modes. The selected mode will be activated immediately
upon mode selection, even if this occurs in the middle of a received
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes: if the
de-selection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop has been re-transmitted.
MR2A[5] – Channel A Transmitter Request-to-Send ControlCAUTION: When the transmitter controls the OP pin (usually used
for the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
commands issued via the command register. MR2[5] set to 1
caused the RTSN to be reset automatically one bit time after the
character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
bits) if a previously issued transmitter disable is pending. This
feature can be used to automatically terminate the transmission as
follows: Program the auto-reset mode: MR2[5]=1 Enable transmitter, if not already enabled Assert RTSN via command Send message After the last character of the message is loaded to the THR,
disable the transmitter. (If the transmitter is underrun, a special
case exists. See note below.) The last character will be transmitted and the RTSN will be reset
one bit time after the last stop bit is sent.
NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
immediately after the transmitter is enabled from the disabled or
reset state. When using the above procedure with the transmitter in
the underrun condition, the issuing of the transmitter disable must be
delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
MR2A[4] – Channel A Clear-to-Send ControlIf this bit is 0, CTSAN has no effect on the transmitter. If this bit is a
1, the transmitter checks the state of CTSAN (IPO) each time it is
ready to send a character. If IPO is asserted (Low), the character is
transmitted. If it is negated (High), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes
low. Changes in CTSAN while a character is being transmitted do
not affect the transmission of that character..
MR2A[3:0] – Channel A Stop Bit Length SelectThis field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1-9/16 to 2
bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1-1/16 to
2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a ‘mark’ condition at the center
of the first stop bit position (one bit time after the last data bit, or
after the parity bit is enabled).
If an external 1X clock is used for the transmitter, MR2A[3] = 0
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
transmitted.
Philips Semiconductors Product specification
SCC2692Dual asynchronous receiver/transmitter (DUART)
MR1B – Channel B Mode Register 1MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will point
to MR2B.
The bit definitions for this register are identical to MR1A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs.
MR2B – Channel B Mode Register 2MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
The bit definitions for mode register are identical to the bit
definitions for MR2A, except that all control actions apply to the
Channel B receiver and transmitter and the corresponding inputs
and outputs.
CSRA – Channel A Clock Select Register
CSRA[7:4] – Channel A Receiver Clock SelectThis field selects the baud rate clock for the Channel A transmitter.
The field definition is shown in Table 3.
CSRA[3:0] – Channel A Transmitter Clock SelectThis field selects the baud rate clock for the Channel A transmitter.
The field definition is as shown in Table 3, except as follows:
The transmitter clock is always a 16X clock except for CSRA[3:0] =
Table 3. Baud Rate
NOTE: The receiver clock is always a 16X clock except for CSRA[7:4]
= 1111. Also, see Table 6 for baud rates available in BRG Test.
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock SelectThis field selects the baud rate clock for the Channel B receiver.
The field definition is as shown in Table 3, except as follows:
CSRB[3:0] – Channel B Transmitter Clock SelectThis field selects the baud rate clock for the Channel B transmitter.
The field definition is as shown in Table 3, except as follows:
The transmitter clock is always a 16X clock except for CSRB[3:0] =
CRA – Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple
commands can be specified in a single write to CRA as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
CRA[7:4] – Miscellaneous CommandsSequential writes to CR(7:4) should be separated by three edges of
the X1 clock.
The encoded value of this field may be used to specify a single
command as follows:
0000 No command.
0001 Reset MR pointer. Causes the Channel A MR pointer to point
to MR1.
0010 Reset receiver. Resets the Channel A receiver as if a hard-
ware reset had been applied. The receiver is disabled and the
FIFO is flushed.
0011 Reset transmitter. Resets the Channel A transmitter as if a
hardware reset had been applied.
0100 Reset error status. Clears the Channel A Received Break,
Parity Error, and Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to clear OE status (al-
though RB, PE and FE bits will also be cleared) and in block
mode to clear all error status after a block of data has been
received.
0101 Reset Channel A break change interrupt. Causes the Chan-
nel A break detect change bit in the interrupt status register
(ISR[2]) to be cleared to zero.
0110 Start break. Forces the TxDA output Low (spacing). If the
transmitter is empty the start of the break condition will be
delayed up to two bit times. If the transmitter is active the
break begins when transmission of the character is com-
pleted. If a character is in the THR, the start of the break will
be delayed until that character, or any other loaded subse-
quently are transmitted. The transmitter must be enabled for
this command to be accepted.
0111 Stop break. The TxDA line will go High (marking) within two
bit times. TxDA will remain High for one bit time before the
next character, if any, is transmitted.
1000 Assert RTSN. Causes the RTSN output to be asserted (Low).
1001 Negate RTSN. Causes the RTSN output to be negated
(High).
1010 Set Timeout Mode On. The receiver in this channel will restart
the C/T as each receive character is transferred from the shift
register to the RHR. The C/T is placed in the counter mode,
the START/STOP counter commands are disabled, the
counter is stopped, and the Counter Ready Bit, ISR[3], is
reset. The counter will not start until the first character is re-
ceived after the command is issued.
1011 Not used.
1100 Disable Timeout Mode. This command returns control of the
