SCC2681AC1A44 ,Dual asynchronous receiver/transmitter (DUART)INTEGRATED CIRCUITSSCC2681Dual asynchronous receiver/transmitter(DUART)Product data 2004 Apr 06
SCC2681AC1A44
Dual asynchronous receiver/transmitter (DUART)
Product data 2004 Apr 06
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
DESCRIPTIONThe Philips Semiconductors SCC2681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. It interfaces directly with microprocessors and may be
used in a polled or interrupt driven system. It is manufactured in a
CMOS process.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16× clock derived from a programmable counter/timer,
or an external 1× or 16× clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the buffer of the receiving device is
full.
Also provided on the SCC2681 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
The SCC2681 is available in three package versions: 40-pin and
28-pin DIPs (both 0.6” wide); and a 44-pin PLCC.
FEATURES Dual full-duplex asynchronous receiver/transmitter Quadruple buffered receiver data registers Programmable data format
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16-bit increments Programmable baud rate for each receiver and transmitter
selectable from:
22 fixed rates: 50 to 115.2 k baud 16-bit programmable Counter/Timer
Non-standard rates to 115.2 kb
One user-defined rate derived from programmable
timer/counter
External 1× or 16× clock Parity, framing, and overrun error detection False start bit detection Line break detection and generation Programmable channel mode
Normal (full-duplex)
Automatic echo
Local loopback
Remote loopback Multi-function programmable 16-bit counter/timer Multi-function 7-bit input port
Can serve as clock or control inputs
Change of state detection on four inputs
100 kΩ typical pull-up resistor Multi-function 8-bit output port
Individual bit set/reset capability
Outputs can be programmed to be status/interrupt signals
DMA signals
Auto 485 turn-around Versatile interrupt system
Single interrupt output with eight maskable interrupting
conditions
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs Maximum data transfer: 1× – 1 MB/sec; 16× – 125 kB/sec Automatic wake-up mode for multidrop applications Start-end break interrupt/status Detects break which originates in the middle of a character On-chip crystal oscillator Single +5 V power supply Commercial and industrial temperature ranges available DIP and PLCC packages
ORDERING INFORMATION
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
PIN CONFIGURATIONS
Figure 1. Pin configurations
PIN DESCRIPTION
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
ABSOLUTE MAXIMUM RATINGS1
NOTES: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied. For operating at elevated temperatures, the device must be derated based on +150 °C maximum junction temperature. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
supply range.
DC ELECTRICAL CHARACTERISTICS1, 2, 3 Tamb = –40 °C to +85 °C; VCC = +5.0 V ± 10%
NOTES: Parameters are valid over specified temperature range. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate. Typical values are at +25 °C, typical supply voltages, and typical processing parameters. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7 kΩ to VCC. All outputs are disconnected. Inputs are switching between CMOS levels of VCC – 0.2 V and VSS + 0.2 V.
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
AC CHARACTERISTICSTamb = –40 °C to +85 °C1; VCC = +5.0 V ± 10% 2, 3, 4, 5
NOTES: For operating at elevated temperatures, the device must be derated based on +150 °C maximum junction temperature. Parameters are valid over specified temperature range. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a
transition time of ≤ 20 ns. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of
0.8 V and 2.0 V as appropriate. Typical values are at +25 °C, typical supply voltages, and typical processing parameters. Test condition for outputs: CL = 150 pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50 pF, RL = 2.7 kΩ to VCC. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART) Consecutive write operations to the same command register require at least three edges of the X1 clock between writes. This parameter is not applicable to the 28-pin device.
10. Operation to 0 MHz is assured by design. However, operation at low frequencies is not tested and has not been characterized.
BLOCK DIAGRAM
Figure 2. Block Diagram
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAMThe SCC2681 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port. Refer
to the block diagram.
Data Bus BufferThe data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
Operation ControlThe operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer.
Interrupt ControlA single active-LOW interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR). The IMR may be
programmed to select only certain conditions to cause INTRN to be
asserted. The ISR can be read by the CPU to determine all currently
active interrupting conditions.
Specific Change of State (COS) bits interrupts are controlled in the
ACR and IPCR registers. The ISR indicates a COS has occurred,
but not the particular pins causing the interrupt.
Outputs OP3-OP7 can be programmed to provide discrete interrupt
outputs for the transmitter, receivers, and counter/timer. The OP
pins associated with the receiver and transmitter may be used for
DMA interface.
Timing CircuitsThe timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and four clock
selectors. The crystal oscillator operates directly from a 3.6864MHz
crystal connected across the X1/CLK and X2 inputs. If an external
clock of the appropriate frequency is available, it may be connected
to X1/CLK. The clock serves as the basic timing reference for the
Baud Rate Generator (BRG), the counter/timer, and other internal
circuits. A clock signal within the limits specified in the specifications
section of this data sheet must always be supplied to the DUART.
If an external clock is used instead of a crystal, both X1 and X2
should use a configuration similar to the one in Figure 7.
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 18 commonly used data
communications baud rates ranging from 50 to 115.2 k baud. The
clock outputs from the BRG are at 16× the actual baud rate. The
counter/timer can be used as a timer to produce a 16× clock for any
other baud rate by counting down the crystal clock or an external
clock. The four clock selectors allow the independent selection, for
each receiver and transmitter, of any of these baud rates or external
timing signal.
Counter/Timer (C/T)The counter timer is a 16 bit programmable divider that operates
one of three modes: Counter, Timer or Time Out mode. In all three
modes it uses the 16-bit value loaded to the CTUR and CTLR
registers. (Counter timer upper and lower preset registers). In the timer mode it generates a square wave. In the counter mode it generates a time delay. In the time out mode it monitors the receiver data flow and signals
data flow has paused. In the time out mode the receiver controls
the starting/stopping of the C/T.
The counter operates as a down counter and sets its output bit in
the ISR (Interrupt Status Register) each time it passes through 0.
The output of the counter/timer may be seen on one of the OP pins
or as an Rx or Tx clock.
The Timer/Counter is controlled with six (6) “commands”; Start C/T,
Stop C/T, write C/T, preset registers, read C/T value, set or reset
time out mode.
Please see the detail of the commands under the Counter/Timer
register descriptions.
Communications Channels A and BEach communications channel of the SCC2681 comprises a
full-duplex asynchronous receiver/transmitter (UART). The operating
frequency for each receiver and transmitter can be selected
independently from the baud rate generator, the counter timer, or
from an external input.
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD
output pin. The receiver accepts serial data on the RxD pin,
converts this serial input to parallel format, checks for start bit, stop
bit, parity bit (if any), or break condition and sends an assembled
character to the CPU.
Input PortThe inputs to this unlatched 7-bit port can be read by the CPU by
performing a read operation at address 0xD. A HIGH input results in
a logic 1 while a LOW input results in a logic 0. D7 will always read
as a logic 1. The pins of this port can also serve as auxiliary inputs
to certain portions of the DUART logic.
Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A HIGH-to-LOW or LOW-to-HIGH
transition of these inputs lasting longer than 25 – 50μs, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.
All the IP pins have a small pull-up device that will source 1 to 4 μA
of current from VCC. These pins do not require pull-up devices or
VCC connections if they are not used.
The input port pulse detection circuitry uses a 38.4 kHz sampling
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25 μs (this assumes that
the clock input is 3.6864 MHz). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
Output PortThe output port pins may be controlled by the OPR, OPCR, MR and
CR registers. Via appropriate programming they may be just another
parallel port to external circuits, or they may represent many internal
conditions of the UART. When this 8-bit port is used as a general
purpose output port, the output port pins drive a state which is the
complement of the Output Port Register (OPR). OPR(n) = 1 results
in OP(n) = LOW and vice versa. Bits of the OPR can be individually
set and reset. A bit is set by performing a write operation at address
0xE with the accompanying data specifying the bits to be set
(1 = set, 0 = no change).
Likewise, a bit is reset by a write at address 0xF with the
accompanying data specifying the bits to be reset (1 = reset,
0 = no change).
Outputs can be also individually assigned specific functions by
appropriate programming of the Channel A mode registers (MR1A,
MR2A), the Channel B mode registers (MR1B, MR2B), and the
Output Port Configuration Register (OPCR).
Please note that these pins drive both HIGH and LOW. However
when they are programmed to represent interrupt type functions
(such as receiver ready, transmitter ready, DMA signals or
counter/timer ready) they will be switched to an open drain
configuration in which case an external pull-up device would be
required.
TRANSMITTER OPERATIONThe SCC2681 is conditioned to transmit data when the transmitter is
enabled through the command register. The SCC2681 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
generate an interrupt request at OP6 or OP7 and INTRN. When a
character is loaded into the Transmit Holding Register (THR), the
above conditions are negated. Data is transferred from the holding
register to transmit shift register when it is idle or has completed
transmission of the previous character. The TxRDY conditions are
then asserted again which means one full character time of buffering
is provided. Characters cannot be loaded into the THR while the
transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the THR, the TxD output remains HIGH
and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the THR.
If the transmitter is disabled, it continues operating until the
character currently being transmitted is completely sent out. The
transmitter can be forced to send a continuous LOW condition by
issuing a send break command.
The transmitter can be reset through a software command (0x30). If
it is reset, operation ceases immediately and the transmitter must be
enabled through the command register before resuming operation. If
CTS operation is enable, the CTSN input must be LOW in order for
the character to be transmitted. If it goes HIGH in the middle of a
transmission, the character in the shift register is transmitted and
TxDA then remains in the marking state until CTSN goes LOW. The
ReceiverThe SCC2681 is conditioned to receive data when enabled through
the command register. The receiver looks for a HIGH-to-LOW
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16×
clock for 7 1/2 clocks (16× clock mode) or at the next rising edge of
the bit time clock (1× clock mode). If RxD is sampled HIGH, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still LOW, a valid start bit is assumed and the receiver continues
to sample the input at one bit time intervals at the theoretical center
of the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to the
Receive Holding Register (RHR) and the RxRDY bit in the SR is set
to a 1. This condition can be programmed to generate an interrupt at
OP4 or OP5 and INTRN. If the character length is less than eight
bits, the most significant unused bits in the RHR are set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains LOW for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).
The parity error, framing error, overrun error and received break
state (if any) are strobed into the SR at the received character
boundary, before the RxRDY status bit is set. If a break condition is
detected (RxD is LOW for the entire character including the stop bit),
a character consisting of all zeros will be loaded into the RHR and
the received break bit in the SR is set to 1. The RxD input must
return to HIGH for two (2) clock edges of the X1 crystal clock for the
receiver to recognize the end of the break condition and begin the
search for a start bit. This will usually require a HIGH time of one
X1 clock period or 3 X1 edges since the clock of the controller
is not synchronous to the X1 clock.
Receiver FIFOThe RHR consists of a First-In-First-Out (FIFO) stack with a capacity
of three characters. Data is loaded from the receive shift register
into the top most empty position of the FIFO. The RxRDY bit in the
status register is set whenever one or more characters are available
to be read, and a FFULL status bit is set if all three stack positions
are filled with data. Either of these bits can be selected to cause an
interrupt. A read of the RHR outputs the data at the top of the FIFO.
After the read cycle, the data FIFO and its associated status bits
(see below) are ‘popped’ thus emptying a FIFO position for new data.
Receiver Status BitsIn addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO.
In the ‘block’ mode, the status provided in the SR for these three bits
is the logical-OR of the status for all characters coming to the top of
the FIFO since the last ‘reset error’ command was issued. In either
mode reading the SR does not affect the FIFO. The FIFO is
‘popped’ only when the RHR is read. Therefore the status register
should be read prior to reading the FIFO.
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SCC2681Dual asynchronous receiver/transmitter (DUART)
shift register is lost and the overrun error status bit (SR[4] will be
set-upon receipt of the start bit of the new (overrunning) character).
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated (set to ‘1’)
when a valid start bit was received and the FIFO is full. When a
FIFO position becomes available, the RTSN output will be
re-asserted (set to ‘0’) automatically. This feature can be used to
prevent an overrun, in the receiver, by connecting the RTSN output
to the CTSN input of the transmitting device.
Receiver Reset and DisableReceiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected.
A receiver reset will discard the present shift register data, reset the
receiver ready bit (RxRDY), clear the status of the byte at the top of
the FIFO and re-align the FIFO read/write pointers. This has the
appearance of “clearing or flushing” the receiver FIFO. In fact, the
FIFO is NEVER cleared! The data in the FIFO remains valid until
overwritten by another received character. Because of this,
erroneous reading or extra reads of the receiver FIFO will miss-align
the FIFO pointers and result in the reading of previously read data.
A receiver reset will re-align the pointers.
Multidrop Mode
Note: Please see Application Note AN10251 for more informationon this feature.
The DUART is equipped with a wake up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3]
or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this mode
of operation, a ‘master’ station transmits an address character
followed by data characters for the addressed ‘slave’ station. The
slave stations, with receivers that are normally disabled, examine
the received data stream and ‘wake up’ the CPU (by setting RxRDY)
only upon receipt of an address character. The CPU compares the
received address to its station address and enables the receiver if it
wishes to receive the subsequent data characters. Upon receipt of
another address character, the CPU may disable the receiver to
initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted A/D
bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].
MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which
identifies the corresponding data bits as data while
MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which
identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bits into the THR.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RHR FIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RHR. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
break detect operate normally whether or not the receive is enabled.
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
PROGRAMMINGThe operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1x by
RESET or by issuing a ‘reset pointer’ command via the
corresponding command register. Any read or write of the mode
register while the pointer is at MR1x, switches the pointer to MR2x.
The pointer then remains at MR2x, so that subsequent accesses are
always to MR2x unless the pointer is reset to MR1x as described
above.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
Table 1. SCC2681 Register Addressing* See Table 5 for BRG Extended frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68692 and SCC2698B” in application notes elsewhere in this publication.
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
Table 2. Register Bit Formats
NOTE: In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset. Please see Receiver Reset note on page 21.
NOTE:*Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
NOTE:* See Table 5 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68692 and SCC2698B” in application notes elsewhere in this publication.
NOTE:*Access to the upper three bits of the command register should be separated by three (3) edges of the X1 clock. A disabled transmitter cannot
be loaded.
NOTE: These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from
the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are discarded
when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using the error
reset command (command 4x) or a receiver reset.
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
Table 2. Register Bit Formats (Continued)
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
MR1A – Channel A Mode Register 1MR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRA. After reading or writing MR1A, the pointer will point
to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send Flow ControlThis bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR1A[7] = 1 causes RTSAN to be
negated upon receipt of a valid start bit if the Channel A FIFO is full.
However, OPR[0] is not reset and RTSAN will be asserted again
when an empty FIFO position is available. This feature can be used
for flow control to prevent overrun in the receiver by using the
RTSAN output signal to control the CTSN input of the transmitting
device.
MR1A[6] – Channel A Receiver Interrupt SelectThis bit selects either the Channel A receiver ready status (RxRDY)
or the Channel A FIFO full status (FFULL) to be used for CPU
interrupts. It also causes the selected bit to be output on OP4 if it is
programmed as an interrupt output via the OPCR.
MR1A[5] – Channel A Error Mode SelectThis bit select the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block”
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
MR1A[4:3| – Channel A Parity Mode SelectIf ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] + 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type Select
Note: Setting these bits to ‘11’ causes a partial enabling of thereceiver. Set these bits to other than ‘11’ if a software or hardware
reset is required for some type of error recovery.
This bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1A[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it selects
the polarity of the A/D bit.
MR1A[1:0] – Channel A Bits Per Character SelectThis field selects the number of data bits per character to be
transmitted and received. The character length does not include the
start, parity, and stop bits.
MR2A – Channel A Mode Register 2MR2A is accessed when the Channel A MR pointer points to MR2,
which occurs after any access to MR1A. Accesses to MR2A do not
change the pointer.
MR2A[7:6] – Channel A Mode SelectEach channel of the DUART can operate in one of four modes.
MR2A[7:6] = 00 is the normal mode, with the transmitter and
receiver operating independently. MR2A[7:6] = 01 places the
channel in the automatic echo mode, which automatically
re-transmits the received data. The following conditions are true
while in automatic echo mode: Received data is re-clocked and retransmitted on the TxDA
output. The receive clock is used for the transmitter. The receiver must be enabled, but the transmitter need not be
enabled. The Channel A TxRDY and TxEMT status bits are inactive. The received parity is checked, but is not regenerated for
transmission, i.e. transmitted parity bit is as received. Character framing is checked, but the stop bits are retransmitted
as received. A received break is echoed as received until the next valid start
bit is detected. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
Two diagnostic modes can also be configured. MR2A[7:6] = 10
selects local loopback mode. In this mode: The transmitter output is internally connected to the receiver
input. The transmit clock is used for the receiver. The TxDA output is held HIGH. The RxDA input is ignored. The transmitter must be enabled, but the receiver need not be
enabled. CPU to transmitter and receiver communications continue
normally.
The second diagnostic mode is the remote loopback mode, selected
by MR2A[7:6] = 11. In this mode: Received data is re-clocked and re-transmitted on the TxDA
output. The receive clock is used for the transmitter. Received data is not sent to the local CPU, and the error status
conditions are inactive. The received parity is not checked and is not regenerated for
transmission, i.e., transmitted parity is as received. The receiver must be enabled. Character framing is not checked and the stop bits are
retransmitted as received. A received break is echoed as received until the next valid start
bit is detected.
Philips Semiconductors Product data
SCC2681Dual asynchronous receiver/transmitter (DUART)
or transmitted character. Likewise, if a mode is deselected the
device will switch out of the mode immediately. An exception to this
is switching out of autoecho or remote loopback modes: if the
deselection occurs just after the receiver has sampled the stop bit
(indicated in autoecho by assertion of RxRDY), and the transmitter
is enabled, the transmitter will remain in autoecho mode until the
entire stop has been retransmitted.
MR2A[5] – Channel A Transmitter Request-to-Send Control
CAUTION: When the transmitter controls the OP pin (usually usedfor the RTSN signal) the meaning of the pin is not RTSN at all!
Rather, it signals that the transmitter has finished the transmission
(i.e., end of block).
Note: Please see Application Note AN10251 for more informationon this subject.
This bit allows deactivation of the RTSN output by the transmitter.
This output is manually asserted and negated by the appropriate
commands issued via the SOPR and ROPR registers. MR2[5] set to
1 caused the RTSN to be reset automatically one bit time after the
character(s) in the transmit shift register and in the THR (if any) are
completely transmitted (including the programmed number of stop
bits) if a previously issued transmitter disable is pending. This
feature can be used to automatically terminate the transmission as
follows: Program the auto-reset mode: MR2[5]=1 Enable transmitter, if not already enabled Set OPR[0] or OPR[1] to ‘1’ via the SOPR and ROPR registers Send message After the last character of the message is loaded to the THR,
disable the transmitter. (If the transmitter is underrun, a special
case exists. See note below.) The last character will be transmitted and the RTSN will be reset
one bit time after the last stop bit is sent.
NOTE: The transmitter is in an underrun condition when both the
TxRDY and the TxEMT bits are set. This condition also exists
immediately after the transmitter is enabled from the disabled or
reset state. When using the above procedure with the transmitter in
the underrun condition, the issuing of the transmitter disable must be
delayed from the loading of a single, or last, character until the
TxRDY becomes active again after the character is loaded.
MR2A[4] – Channel A Clear-to-Send ControlIf this bit is 0, CTSAN has no effect on the transmitter. If this bit is a
1, the transmitter checks the state of CTSAN (IPO) each time it is
ready to send a character. If IPO is asserted (LOW), the character is
transmitted. If it is negated (HIGH), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes
LOW. Changes in CTSAN while a character is being transmitted do
not affect the transmission of that character..
MR2A[3:0] – Channel A Stop Bit Length SelectThis field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of .563 TO 1 AND .563 to 2
bits. In increments of 0.625 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1.0625
to 2 stop bits can be programmed in increments of .0625 bit.
The receiver only checks for a ‘mark’ condition at the center of the
first stop bit position (one bit time after the last data bit, or after the
parity bit is enabled) in all cases.
MR1B – Channel B Mode Register 1MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will point
to MR2B.
MR2B – Channel B Mode Register 2MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
The bit definitions for mode registers 1 and 2 are identical to the bit
definitions for MRA and MR2A except that all control actions apply
to the Channel B receiver and transmitter and the corresponding
inputs and outputs.
CSRA – Channel A Clock Select RegisterSTandard baud rates are shown below. A read at address 0x2
changes the baud rate generator to give higher speed baud rates.
(See Table 5 on page 21.) A subsequent read at address 0x2
changes the baud rate generator back to standard rates. In other
words, each read at 0x2 toggles the controlling flip-flop.
Table 3. Bit Rate Generator Characteristics
Crystal or Clock = 3.6864MHz
NOTE: Duty cycle of 16× clock is 50% ± 1%.Asynchronous UART communications can tolerate frequency error
of 4.1% to 6.7% in a “clean” communications channel. The percent
of error changes as the character length changes. The above
percentages range from 5 bits not parity to 8 bits with parity and one
stop bit. The error with 8 bits not parity and one stop bit is 4.6%. If a
stop bit length of 9/16 is used, the error tolerance will approach 0
