SCANPSC100FSC ,Embedded Boundary Scan ControllerFeaturesThe SCANPSC100F is designed to interface a generic par-
SCANPSC100FSC-SCANPSC100FSCX
Embedded Boundary Scan Controller
SCANPSC100F Embedded Boundary Scan Controller (IEEE 1149.1 Support) December 1991 Revised May 2000 SCANPSC100F Embedded Boundary Scan Controller (IEEE 1149.1 Support) General Description Features The SCANPSC100F is designed to interface a generic par-Compatible with IEEE Std. 1149.1 (JTAG) Test Access allel processor bus to a serial scan test bus. It is useful in Port and Boundary Scan Architecture improving scan throughput when applying serial vectors toSupported by Fairchild’s SCAN Ease (Embedded Appli- system test circuitry and reduces the software overhead cation Software Enabler) Software that is associated with applying serial patterns with a paral- Uses generic, asynchronous processor interface; com- lel processor. The SCANPSC100F operates by serializing patible with a wide range of processors and PCLK fre- data from the parallel bus for shifting through the chain of quencies 1149.1 compliant components (i.e., scan chain). Scan data Directly supports up to two 1149.1 scan chains returning from the scan chain is placed on the parallel port 16-bit Serial Signature Compaction (SSC) at the Test to be read by the host processor. Up to two scan chains can be directly controlled with the SCANPSC100F via two Data In (TDI) port independent TMS pins. Scan control is supplied with userAutomatically produces pseudo-random patterns at the specific patterns which makes the SCANPSC100F proto- Test Data Out (TDO) port col-independent. Overflow and underflow conditions are Fabricated on FACT 1.5 μm CMOS process prevented by stopping the test clock. A 32-bit counter is Supports 1149.1 test clock (TCK) frequencies up to used to program the number of TCK cycles required to 25 MHz complete a scan operation within the boundary scan chain TTL-compatible inputs; full-swing CMOS outputs with or to complete a SCANPSC100F Built-In Self Test (BIST) 24 mA source/sink capability operation. SCANPSC100F device drivers and 1149.1 embedded test application code are available with Fair- child’s SCAN Ease software tools. Ordering Code: Order Number Package Number Package Description SCANPSC100FSC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram FACT is a trademark of . © 2000 DS010968
