SCANPSC100F ,Embedded Boundary Scan ControllerFeaturesYCompatible with IEEE Std. 1149.1 (JTAG) Test AccessThe SCANPSC100F is designed to interfac ..
SCANPSC100FSC ,Embedded Boundary Scan ControllerFeaturesThe SCANPSC100F is designed to interface a generic par-
SCANPSC100F
Embedded Boundary Scan Controller
TL/F/10968
SCANPSC100F
Embedded
Boundary
Scan
Controller
(IEEE
Support)
February 1996
SCANPSC100F
Embedded Boundary Scan Controller
(IEEE 1149.1 Support)
General Description
The SCANPSC100Fis designedto interfacea genericpar-
allel processorbustoa serial scantest bus.Itis usefulin
improving scan throughput when applying serial vectorsto
system test circuitry and reducesthe software overhead
thatis associated with applying serial patternswitha paral-
lel processor. The ’PSC100F operatesby serializing data
fromthe parallelbusfor shifting throughthe chainof 1149.1
compliant components (i.e., scan chain). Scan data return-
ing fromthe scan chainis placedonthe parallel porttobe
readbythe host processor.Uptotwo scan chainscanbe
directly controlled withthe ’PSC100Fviatwo independent
TMS pins. Scan controlis supplied with user specific pat-
terns which makesthe ’PSC100F protocol-independent.
Overflowand underflow conditionsare preventedby stop-
pingthetest clock.A 32-bit counteris usedto programthe
numberof TCK cycles requiredto completea scan opera-
tion withinthe boundary scan chainorto completea
’PSC100F Built-In Self Test (BIST) operation.
SCANPSC100F device drivers and 1149.1 embeddedtest
application codeare available with National’s SCAN Ease
software tools.
Features Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Portand Boundary Scan Architecture Supportedby National’s SCAN Ease (Embedded Appli-
cation Software Enabler) Software Uses generic, asynchronous processor interface; com-
patible witha wide rangeof processorsand PCLK
frequencies Directly supportsuptotwo 1149.1 scan chains 16-bit Serial Signature Compaction (SSC)atthe Test
DataIn (TDI) port Automatically produces pseudo-random patternsatthe
Test DataOut (TDO)port Fabricatedon FACTTM1.5mm CMOS process Supports 1149.1 test clock (TCK) frequenciesupto MHz TTL-compatible inputs; full-swing CMOS outputs withmA source/sink capability
Connection Diagrams
28-Pin SOIC,DIPand Flatpak
TL/F/10968–1
PinAssignment
for LCC
TL/F/10968–18
Order Number Description
SCANPSC100FSC SOICin Tubes
SCANPSC100FSCX SOICin Tapeand Reel
SCANPSC100FFMQB Military Flatpak
SCANPSC100FDMQB Military CeramicDIP
SCANPSC100FLMQB Military Leadless Chip Carrier
5962-9475001QYA Military SMDÝ, Flatpak
5962-9475001QXA Military SMDÝ, CDIP
5962-9475001Q3A Military SMDÝ, LCCTRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
FACTTMisa trademarkof NationalSemiconductor Corporation.
C1996National SemiconductorCorporation RRD-B30M36/Printed inU.S.A. http://
