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SCAN921023SLCNSN/a18avai20 MHz-66MHz 10-Bit Serializer with IEEE 1149.1 Test Access
SCAN921224SLCNSCN/a4avai20 MHz-66MHz 10-Bit Deserializer with IEEE 1149.1 Test Access


SCAN921023SLC ,20 MHz-66MHz 10-Bit Serializer with IEEE 1149.1 Test AccessGeneral Descriptionthesynchronizationmode,theDeserializerwillestablishlockThe SCAN921023 transforms ..
SCAN921224SLC ,20 MHz-66MHz 10-Bit Deserializer with IEEE 1149.1 Test Accessfeatures an at-speed BISTSCAN921260UJB ,six 1 to 10 deserializers with IEEE 1149.1 and at-speed BISTPin Description table with type Bus LVDS InputsDifferential Threshold HighV VCM = 1.1V (V -V ) +3 + ..
SCAN921260UJB/NOPB ,six 1 to 10 deserializers with IEEE 1149.1 and at-speed BIST 196-NFBGA -40 to 85ELECTRICAL CHARACTERISTICSOver recommended operating supply and temperature ranges unless otherwise ..
SCAN921821TSM ,Dual 18-Bit Serializer with Pre-Emphasis, IEEE 1149.1 (JTAG), and At-Speed BISTFeaturesn 15-66 MHz Dual 18:1 Serializer with 2.376 Gbps totalThe SCAN921821 is a dual channel 18-b ..
SCAN926260TUF ,Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BISTfeatures an At-Speed Built-In Self Testn On chip filtering for PLL(BIST).Formoredetails,pleaseseeth ..
SFR9220 ,P-CHANNEL POWER MOSFETFEATURESBV = -200 VDSS Avalanche Rugged TechnologyR = 1.5 ΩDS(on) Rugged Gate Oxide T ..
SFR9220TF ,200V P-Channel A-FET / Substitute of IRFR9220SFR/U9220Advanced Power MOSFET
SFR9224 ,P-CHANNEL POWER MOSFETFEATURESBV = -250 VDSS Avalanche Rugged TechnologyR = 2.4 ΩDS(on) Rugged Gate Oxide T ..
SFR9224TF ,250V P-Channel A-FETSFR/U9224Advanced Power MOSFET
SFR9224TM ,250V P-Channel A-FETFEATURESBV = -250 VDSS Avalanche Rugged TechnologyR = 2.4 ΩDS(on) Rugged Gate Oxide T ..
SFR9224TM ,250V P-Channel A-FETFEATURESBV = -250 VDSS Avalanche Rugged TechnologyR = 2.4 ΩDS(on) Rugged Gate Oxide T ..


SCAN921023SLC-SCAN921224SLC
20 MHz-66MHz 10-Bit Serializer with IEEE 1149.1 Test Access
SCAN921023 and SCAN921224
20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
with IEEE 1149.1 (JTAG) and at-speed BIST
General Description

The SCAN921023 transformsa 10-bit wide parallel
LVCMOS/LVTTL data bus intoa single high speed Bus
LVDS serial data stream with embedded clock. The
SCAN921224 receivesthe Bus LVDS serial data stream and
transformsit back intoa 10-bit wide parallel data bus and
recovers parallel clock. Both devices are compliant with
IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture with the incorporationofthe defined boundary-
scan test logic and test access port consistingof Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select (TMS),
Test Clock (TCK), andthe optional Test Reset (TRST). IEEE
1149.1 features providethe designeror test engineer access the backplaneor cable interconnects and the abilityto
verify differential signal integrityto enhance their system test
strategy. The pairof devices also featuresan at-speed BIST
mode which allowsthe interconnects betweenthe Serializer
and Deserializertobe verified at-speed.
The SCAN921023 transmits data over backplanesor cable.
The single differential pair data path makes PCB design
easier.In addition,the reduced cable, PCB trace count, and
connector size tremendously reduce cost. Since one output
transmits clock and data bits serially,it eliminates clock-to-
data and data-to-data skew. The powerdown pin saves
powerby reducing supply current when not using either
device. Upon powerupofthe Serializer, you can chooseto
activate synchronization modeor allow the Deserializerto
use the synchronization-to-random-data feature.By using
the synchronization mode,the Deserializerwill establish locka signal within specified lock times.In addition, the em-
bedded clock guaranteesa transitiononthe bus every 12-bit
cycle. This eliminates transmission errors dueto charged
cable conditions. Furthermore, you may put the
SCAN921023 output pins into TRI-STATEto achievea high
impedance state. The PLL can lockto frequencies between MHz and66 MHz.
Features
IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test
mode. Clock recovery from PLL lockto random data patterns. Guaranteed transition every data transfer cycle Chipset (Tx+ Rx) power consumption< 500 mW (typ)66 MHz Single differential pair eliminates multi-channel skew Flow-through pinoutfor easy PCB layout 660 Mbps serial Bus LVDS data rate(at66 MHz clock) 10-bit parallel interfacefor1 byte data plus2 control bits Synchronization mode and LOCK indicator Programmable edge triggeron clock High impedanceon receiver inputs when powerisoff Bus LVDS serial output ratedfor 27Ω load Small 49-lead BGA package
Block Diagrams

April 2001
SCAN921023/SCAN921224
MHz
Bit
VDS
Serializer
and
Deserializer
with
IEEE
(JT
AG)
and
at-speed
BIST
ic,good price


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