SCAN18374TSSC ,D Flip-Flop with 3-STATE Outputsapplicationsdard Test Access Port and BOUNDARY-SCAN Architec-ture with the incorporation of the def ..
SCAN18374TSSCX ,D Flip-Flop with 3-STATE OutputsFunctional DescriptionThe SCAN18374 consists of two sets of nine edge-trig- LOW-to-HIGH Clock (ACP ..
SCAN18540TSSC ,Inverting Line Driver with 3-STATE OutputsapplicationsTest Access Port and Boundary Scan Architecture with theincorporation of the defined bo ..
SCAN18540TSSC ,Inverting Line Driver with 3-STATE Outputsapplicationsnals. This device is compliant with IEEE 1149.1 Standard
SCAN18374TSSC-SCAN18374TSSCX
D Flip-Flop with 3-STATE Outputs
SCAN18374T D-Type Flip-Flop with 3-STATE Outputs October 1991 Revised May 2000 SCAN18374T D-Type Flip-Flop with 3-STATE Outputs General Description Features The SCAN18374T is a high speed, low-power D-type flip-IEEE 1149.1 (JTAG) Compliant flop featuring separate D-type inputs organized into dual 9-Buffered positive edge-triggered clock bit bytes with byte-oriented clock and output enable control 3-STATE outputs for bus-oriented applications signals. This device is compliant with IEEE 1149.1 Stan- 9-bit data busses for parity applications dard Test Access Port and BOUNDARY-SCAN Architec- ture with the incorporation of the defined BOUNDARY-Reduced-swing outputs source 32 mA/sink 64 mA SCAN test logic and test access port consisting of TestGuaranteed to drive 50Ω transmission line to TTL input Data Input (TDI), Test Data Out (TDO), Test Mode Select levels of 0.8V and 2.0V (TMS), and Test Clock (TCK). TTL compatible inputs 25 mil pitch SSOP (Shrink Small Outline Package) Includes CLAMP and HIGHZ instructions Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number Package Description SCAN18374TSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description AI , BI Data Inputs (0–8) (0–8) ACP, BCP Clock Pulse Inputs AOE , BOE 3-STATE Output Enable Inputs 1 1 AO , BO 3-STATE Outputs (0–8) (0–8) Truth Tables Inputs AO (0–8) ACP AOE AI 1 (0–8) XHX Z LL L LH H Inputs BO (0–8) BCP BOE BI 1 (0–8) XHX Z LL L LH H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = L-to-H Transition © 2000 DS010963
