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SCAN182245ASSCXNSN/a589avaiNon-Inverting Transceiver with 25 Ohm Series Resistor Outputs


SCAN182245ASSCX ,Non-Inverting Transceiver with 25 Ohm Series Resistor OutputsapplicationsScan Architecture with the incorporation of the defined

SCAN182245ASSCX
Non-Inverting Transceiver with 25 Ohm Series Resistor Outputs
SCAN182245A Non-Inverting Transceiver with 25Ω Series Resistor Outputs December 1993 Revised January 2001 SCAN182245A Non-Inverting Transceiver with 25Ω Series Resistor Outputs General Description Features The SCAN182245A is a high performance BiCMOS bidi-High performance BiCMOS technology rectional line driver featuring separate data inputs orga-25Ω series resistors in outputs eliminate the need for nized into dual 9-bit bytes with byte-oriented output enable external terminating resistors and direction control signals. This device is compliant with Dual output enable control signals IEEE1149.1Standard Test Access Port and Boundary 3-STATE outputs for bus-oriented applications Scan Architecture with the incorporation of the defined 25 mil pitch SSOP (Shrink Small Outline Package) boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test ModeIEEE 1149.1 (JTAG) Compliant Select (TMS), and Test Clock (TCK). Includes CLAMP, IDCODE and HIGHZ instructions Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT Power Up 3-STATE for hot insert Member of Fairchild’s SCAN Products Ordering Code: Package Order Number Package Description Number SCAN182245ASSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide SCAN182245AMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description A1 Side A1 Inputs or 3-STATE Outputs (0–8) B1 Side B1 Inputs or 3-STATE Outputs (0–8) A2 Side A2 Inputs or 3-STATE Outputs (0–8) B2 Side B2 Inputs or 3-STATE Outputs (0–8) G1, G2 Output Enable Pins (Active LOW) DIR1, DIR2 Direction of Data Flow Pins © 2001 DS011657
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