SC68C752BIB48 ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and 68 mode uP interfacFeatures Dual channel with 68 mode (Motorola) μP interface Up to 5 Mbit/s data rate 64-byte tran ..
SC68C94A1A ,nullQuad universal asynchronous receiver/transmitter QUART
SC68C94C1A ,nullQuad universal asynchronous receiver/transmitter QUART
SC68C94C1A ,nullQuad universal asynchronous receiver/transmitter QUART
SC72131S ,stock - PLL FOR DIGITAL TUNING SYSTEM(DTS)
SC72131S ,stock - PLL FOR DIGITAL TUNING SYSTEM(DTS)
SFECV10M7FA00-R0 , Ceramic Filters (CERAFIL) for FM Receivers
SFF1004G , Isolation 10.0 AMPS. Glass Passivated Super Fast Rectifiers
SFF1005G , Isolation 10.0 AMPS. Glass Passivated Super Fast Rectifiers
SFF12N60 , N-Channel MOSFET
SFF1606G , Isolation 16.0 AMPS. Glass Passivated Super Fast Rectifiers
SFF2004G , Isolation 20.0 AMPS. Glass Passivated Super Fast Rectifiers
SC68C752BIB48
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and 68 mode uP interfac
General descriptionThe SC68C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s.
The SC68C752B offers enhanced features. It has a Transmission Control Register (TCR)
that stores receiver FIFO threshold levels to start/stop transmission during hardware and
software flow control. With the FIFO Rdy register, the software gets the status of
TXRDYn/RXRDYn for all four ports in one access. On-chip status registers provide the
user with error indications, operational status, and modem interface control. System
interrupts may be tailored to meet user requirements. An internal loopback capability
allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TXn signal and
receives characters on the RXn signal. Characters can be programmed to be 5 bits, 6 bits, bits, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own desired
baud rate based upon a programmable divisor and its input clock. It can transmit even,
odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing
errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The
UART also contains a software interface for modem control operations, and has software
flow control and hardware flow control capabilities.
The SC68C752B is available in LQFP48 and HVQFN32 packages.
Features Dual channel with 68 mode (Motorola) μP interface Up to 5 Mbit/s data rate 64-byte transmit FIFO 64-byte receive FIFO with error flags Programmable and selectable transmit and receive FIFO trigger levels for DMA and
interrupt generation Software/hardware flow control Programmable Xon/Xoff characters Programmable auto-RTS and auto-CTS Optional data flow resume by Xon any character DMA signalling capability for both received and transmitted data Supports 5 V, 3.3 V and 2.5 V operation
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte
FIFOs and 68 mode μP interface
Rev. 04 — 20 January 2010 Product data sheet
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs5 V tolerant on input only pins1 Software selectable baud rate generator Prescaler provides additional divide-by-4 function Industrial temperature range (−40 °C to +85 °C) Fast data bus access time Programmable Sleep mode Programmable serial interface characteristics 5-bit, 6-bit, 7-bit, or 8-bit characters Even, odd, or no parity bit generation and detection 1, 1.5, or 2 stop bit generation False start bit detection Complete status reporting capabilities in both normal and Sleep mode Line break generation and detection Internal test and loopback capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)
Ordering information For data bus pins D7 to D0, see Table 25 “Limiting values”.
Table 1. Ordering informationSC68C752BIB48 LQFP48 plastic low profile quad flat package; 48 leads;
body7×7× 1.4 mm
SOT313-2
SC68C752BIBS HVQFN32 plastic thermal enhanced very thin quad flat package; leads; 32 terminals; body5×5× 0.85 mm
SOT617-1
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Block diagramNXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Pinning information
5.1 PinningNXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
5.2 Pin descriptionTable 2. Pin description 28 19 I
Address 0 select bit. Internal registers address selection. 27 18 I
Address 1 select bit. Internal registers address selection. 26 17 I
Address 2 select bit. Internal registers address selection. 11 9 I
Address 3. A3 is used to select Channel A or Channel B. A logic LOW selects
Channel A, and a logic HIGH selects Channel B. (See Table3.)
CDA 40 - I
Carrier Detect (active LOW). These inputs are associated with individual UART Channel A and Channel B. A logic LOW on these pins indicates that a carrier has
been detected by the modem for that channel. The state of these inputs is
reflected in the Modem Status Register (MSR).
CDB 16 - I 10 8 I
Chip Select (active LOW). This pin enables data transfers between the user CPU and the SC68C752B for the channel(s) addressed. Individual UART
sections (A, B) are addressed by A3. See Table3.
CTSA 38 25 I
Clear to Send (active LOW). These inputs are associated with individual UART Channel A and Channel B. A logic 0 (LOW) on the CTSn pins indicates the
modem or data set is ready to accept transmit data from the SC68C752B. Status
can be tested by reading MSR[4]. These pins only affect the transmit and receive
operations when auto-CTS function is enabled via the Enhanced Feature
Register EFR[7] for hardware flow control operation.
CTSB 23 15 I 44 27 I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant
bit and the first data bit in a transmit or receive serial data stream.D1 45 28 I/O 46 29 I/O 47 30 I/O 48 31 I/O 1 32 I/O 2 1 I/O 3 2 I/O
DSRA 39 - I
Data Set Ready (active LOW). These inputs are associated with individual UART Channel A and Channel B. A logic 0 (LOW) on these pins indicates the
modem or data set is powered-on and is ready for data exchange with the UART.
The state of these inputs is reflected in the Modem Status Register (MSR).
DSRB 20 - I
DTRA 34 - O
Data Terminal Ready (active LOW). These outputs are associated with individual UART Channel A and Channel B. A logic 0 (LOW) on these pins
indicates that the SC68C752B is powered-on and ready. These pins can be
controlled via the Modem Control Register. Writing a logic 1 to MCR[0] will set the
DTRn output pin to logic 0 (LOW), enabling the modem. The output of these pins
will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
DTRB 35 - O
GND 17, 24 13[1] I
Signal and power ground.IRQ 30 21 O
Interrupt Request. Interrupts from UART Channel A and Channel B are
wire-ORed internally to function as a single IRQ interrupt. This pin transitions to a
logic 0 (if enabled by the Interrupt Enable Register) whenever a UART channel(s)
requires service. Individual channel interrupt status can be determined by
addressing each channel through its associated internal register, using CS and
A3. An external pull-up resistor must be connected between this pin and VCC.
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOsR/W 15 12 I A logic LOW on this pin will transfer the contents of the data bus (D[7:0]) from an
external CPU to an internal register that is defined by address bits A[2:0]. A logic
HIGH on this pin will load the contents of an internal register defined by address
bits A[2:0] on the SC68C752B data bus (D[7:0]) for access by an external CPU.
n.c. 12, 25,
29,37
14, 20 - not connected
OPA 32 22 O
User defined outputs. This function is associated with individual Channel A and
Channel B. The state of these pins is defined by the user through the software
settings of MCR[3]. OPA/OPB is a logic 0 when MCR[3] is set to a logic1.
OPA/OPB is a logic 1 when MCR[3] is set to a logic 0. The output of these two
pins is HIGH after reset.
OPB 97 O
RESET 36 24 I
Reset (active LOW). This pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset
time. RESET is an active LOW input.
RIA 41 - I
Ring Indicator (active LOW). These inputs are associated with individual UART Channel A and Channel B. A logic 0 on these pins indicates the modem has
received a ringing signal from the telephone line. A LOW-to-HIGH transition on
these input pins generates a modem status interrupt, if enabled. The state of
these inputs is reflected in the Modem Status Register (MSR).
RIB 21 - I
RTSA 33 23 O
Request to Send (active LOW). These outputs are associated with individual UART Channel A and Channel B. A logic 0 on the RTSn pin indicates the
transmitter has data ready and waiting to send. Writing a logic 1 in the Modem
Control Register MCR[1] will set this pin to a logic 0, indicating data is available.
After a reset these pins are set to a logic 1. These pins only affect the transmit
and receive operations when auto-RTS function is enabled via the Enhanced
Feature Register (EFR[6]) for hardware flow control operation.
RTSB 22 16 O
RXA 5 4 I
Receive data input. These inputs are associated with individual serial channel data to the SC68C752B. During the local Loopback mode, these RXn input pins
are disabled and transmit data is connected to the UART receive input internally.RXB 4 3 I
RXRDYA 31 - O
Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the trigger level has been reached or the FIFO has at least one character. It goes
HIGH when the receive FIFO is empty.RXRDYB 18 - O
TXA 7 5 O
Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC68C752B. During the local Loopback mode, the TXn
output pin is disabled and transmit data is internally connected to the UART
receive input.
TXB 8 6 O
TXRDYA 43 - O
Transmit Ready (active LOW). TXRDYA or TXRDYB go LOW when there are at least a trigger level number of spaces available or when the FIFO is empty. It
goes HIGH when the FIFO is full or not empty.TXRDYB 6- O
VCC 19, 42 26 I
Power supply input.XTAL1 13 10 I
Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an
internal oscillator circuit (see Figure 13). Alternatively, an external clock can be
connected to this pin to provide custom data rates.
XTAL2 14 11 O
Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2 is used as a crystal oscillator output or a buffered clock output.
Table 2. Pin description …continued
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs[1] HVQFN32 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
Functional descriptionThe UART will perform serial-to-parallel conversion on data characters received from
peripheral devices or modems, and parallel-to-parallel conversion on data characters
transmitted by the processor. The complete status of each channel of the SC68C752B
UART can be read at any time during functional operation by the processor.
The SC68C752B can be placed in an alternate mode (FIFO mode) relieving the processor
of excessive software overhead by buffering received/transmitted characters. Both the
receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of
error status per byte for the receiver FIFO) and have selectable or programmable trigger
levels. Primary outputs RXRDYn and TXRDYn allow signalling of DMA transfers.
The SC68C752B has selectable hardware flow control and software flow control.
Hardware flow control significantly reduces software overhead and increases system
efficiency by automatically controlling serial data flow using the RTSn output and CTSn
input signals. Software flow control automatically controls data flow by using
programmable Xon/Xoff characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (216− 1).
6.1 Trigger levelsThe SC68C752B provides independent selectable and programmable trigger levels for
both receiver and transmitter DMA and interrupt generation. After reset, both transmitter
and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of
one byte. The selectable trigger levels are available via the FCR. The programmable
trigger levels are available via the Trigger Level Register (TLR).
6.2 Hardware flow controlHardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS
can be enabled/disabled independently by programming EFR[7:6].
With auto-CTS, CTSn must be active before the UART can transmit data.
Auto-RTS only activates the RTSn output when there is enough room in the FIFO to
receive data and de-activates the RTSn output when the receive FIFO is sufficiently full.
The halt and resume trigger levels in the TCR determine the levels at which RTSn is
activated/deactivated.
Table 3. Channel selection using CS pin - none 0 channelA 1 channelB
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOsIf both auto-CTS and auto-RTS are enabled, when RTSn is connected to CTSn, data
transmission does not occur unless the receive FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.
6.2.1 Auto-RTSAuto-RTS data flow control originates in the receiver block (see Figure 1 “Block diagram
of SC68C752B” on page 3). Figure 5 shows RTSn functional timing. The receiver FIFO
trigger levels used in auto-RTS are stored in the TCR. RTSn is active if the receiver FIFO
level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is
reached, RTSn is de-asserted. The sending device (for example, another UART) may
send an additional byte after the trigger level is reached (assuming the sending UART has
another byte to send) because it may not recognize the de-assertion of RTSn until it has
begun sending the additional byte. RTSn is automatically reasserted once the receiver
FIFO reaches the resume trigger level programmed via TCR[7:4]. This re-assertion allows
the sending device to resume transmission.
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.2.2 Auto-CTSThe transmitter circuitry checks CTSn before sending the next data byte. When CTSn is
active, the transmitter sends the next byte. To stop the transmitter from sending the
following byte, CTSn must be de-asserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system. When
flow control is enabled, CTSn level changes do not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends
any data present in the transmit FIFO and a receiver overrun error may result.
6.3 Software flow controlSoftware flow control is enabled through the Enhanced Feature Register and the Modem
Control Register. Different combinations of software flow control can be enabled by setting
different combinations of EFR[3:0]. Table 4 shows software flow control options.
Table 4. Software flow control options (EFR[3:0]) 0 X X no transmit flow control 0 X X transmit Xon1, Xoff1 1 X X transmit Xon2, Xoff2 1 X X transmit Xon1, Xon2, Xoff1, Xoff2 X 0 0 no receive flow control X 1 0 receiver compared Xon1, Xoff1 X 0 1 receiver compares Xon2, Xoff2 0 1 1 transmit Xon1, Xoff1
receiver compares Xon1 and Xon2, Xoff1 and Xoff2 1 1 1 transmit Xon2, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2 1 1 1 transmit Xon1, Xon2, Xoff1, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOsThere are two other enhanced features relating to software flow control:
Xon Any function (MCR[5]): Operation will resume after receiving any character after recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an Xon Any character, which could cause an Xon2 character to be
written to the RX FIFO.
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the
RX FIFO.
6.3.1 Receive flow controlWhen software flow control operation is enabled, the SC68C752B will compare incoming
data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be
received sequentially). When the correct Xoff character are received, transmission is
halted after completing transmission of the current character. Xoff detection also sets
IIR[4] (if enabled via IER[5]) and causes IRQ to go HIGH.
To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
6.3.2 Transmit flow controlXoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level
programmed in TCR[3:0].
Xon1/Xon2 character is transmitted when the RX FIFO reaches the RESUME trigger level
programmed in TCR[7:4].
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an
ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7
characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xon2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.)
It is assumed that software flow control and hardware flow control will never be enabled
simultaneously. Figure 7 shows an example of software flow control.
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.3.3 Software flow control example
6.3.3.1 AssumptionsUART1 is transmitting a large text file to UART2. Both UARTs are using software flow
control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold
(TCR[3:0]= F) set to 60, and Xon threshold (TCR[7:4]= 8) set to 32. Both have the
interrupt receive threshold (TLR[7:4]= D) set to 52.
UART1 begins transmission and sends 52 characters, at which point UART2 will generate
an interrupt to its processor to service the RX FIFO, but assume the interrupt latency is
fairly long. UART1 will continue sending characters until a total of 60 characters have
been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt
transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff
character. Now UART2 is serviced and the processor reads enough data out of the RX
FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1, informing UART1
to resume transmission.
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.4 ResetTable 5 summarizes the state of register after reset.
Remark: Registers DLL, DLM, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal RESET, that is, they hold their initialization values during reset.
Table 6 summarizes the state of registers after reset.
Table 5. Register reset functionsInterrupt Enable Register RESET all bits cleared
Interrupt Identification Register RESET bit 0 is set; all other bits cleared
FIFO Control Register RESET all bits cleared
Line Control Register RESET reset to 0001 1101 (1Dh)
Modem Control Register RESET all bits cleared
Line Status Register RESET bits 5 and 6 set; all other bits cleared
Modem Status Register RESET bits 0to 3 cleared; bits 4to 7 input signals
Enhanced Feature Register RESET all bits cleared
Receiver Holding Register RESET pointer logic cleared
Transmitter Holding Register RESET pointer logic cleared
Transmission Control Register RESET all bits cleared
Trigger Level Register RESET all bits cleared
Table 6. Signal RESET functionsTXn RESET HIGH
RTSn RESET HIGH
DTRn RESET HIGH
RXRDYn RESET HIGH
TXRDYn RESET LOW
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.5 InterruptsThe SC68C752B has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of
interrupts and the IRQ signal in response to an interrupt generation. The IER can also
disable the interrupt system by clearing bits 3:0 and bits 7:5. When an interrupt is
generated, the IIR indicates that an interrupt is pending and provides the type of interrupt
through IIR[5:0]. Table 7 summarizes the interrupt control functions.
It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
Table 7. Interrupt control functions000001 None none none none
000110 1 receiver line
status
OE, FE, PE, or BI errors occur
in characters in the RX FIFO
FE, PE, BI: all erroneous
characters are read from
the RX FIFO.
OE: read LSR
001100 2 RX time-out stale data in RX FIFO read RHR
000100 2 RHR interrupt DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
read RHR
000010 3 THR interrupt TFE (THR empty)
(FIFO disable) FIFO passes above trigger
level
(FIFO enable)
read IIR or a write to the
THR
000000 4 modem status MSR[3:0]=0 read MSR
010000 5 Xoff interrupt receive Xoff character(s)/
special character
receive Xon character(s)/
Read of IIR
100000 6 CTS, RTS RTSn pin or CTSn pin change
state from active (LOW) to
inactive (HIGH)
read IIR
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.5.1 Interrupt mode operationIn Interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the
receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to
continuously poll the Line Status Register (LSR) to see if any interrupt needs to be
serviced. Figure 8 shows Interrupt mode operation.
6.5.2 Polled mode operationIn Polled mode (IER[3:0]= 0000) the status of the receiver and transmitter can be
checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO
Interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU. Figure 9 shows FIFO
polled mode operation.
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.6 DMA operationThere are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by
FCR[3].
In DMA mode 0 or FIFO disable (FCR[0]= 0) DMA occurs in single character transfers. In
DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the
processor for longer periods of time.
6.6.1 Single DMA transfers (DMA mode 0/FIFO disable)Figure 10 shows TXRDYn and RXRDYn in DMA mode 0/FIFO disable.
6.6.1.1 TransmitterWhen empty, the TXRDYn signal becomes active. TXRDYn will go inactive after one
character has been loaded into it.
6.6.1.2 ReceiverRXRDYn is active when there is at least one character in the FIFO. It becomes inactive
when the receiver is empty.
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.6.2 Block DMA transfers (DMA mode1)Figure 11 shows TXRDYn and RXRDYn in DMA mode1.
6.6.2.1 TransmitterTXRDYn is active when there is a trigger level number of spaces available. It becomes
inactive when the FIFO is full.
6.6.2.2 ReceiverRXRDYn becomes active when the trigger level has been reached, or when a time-out
interrupt occurs. It will go inactive when the FIFO is empty or an error in the receive FIFO
is flagged by LSR[7].
6.7 Sleep modeSleep mode is an enhanced feature of the SC68C752B UART. It is enabled when EFR[4],
the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:
The serial data input line, RXn, is idle (see Section 6.8 “Break and time-out
conditions”).
The transmit FIFO and transmit shift register are empty.
There are no interrupts pending except THR and time-out interrupts.
Remark: Sleep mode will not be entered if there is data in the receive FIFO.In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced. The UART will
wake up when any change is detected on the RXn line, when there is any change in the
state of the modem input pins, or if data is written to the transmit FIFO.
Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLM.
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.8 Break and time-out conditionsAn RX idle condition is detected when the receiver line, RXn, has been HIGH for character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TXn line is pulled LOW. A break condition is activated
by setting LCR[6].
6.9 Programmable baud rate generatorThe SC68C752B UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (216− 1). An additional
divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
Figure 12. The output frequency of the baud rate generator is 16 times the baud rate. The
formula for the divisor is:
(1)
Where:
prescaler= 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler= 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
Remark: The default value of prescaler after reset is divide-by-1.Figure 12 shows the internal prescaler and baud rate generator circuitry.
DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the
least significant and most significant byte of the baud rate divisor. If DLL and DLM are
both zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit and receive clock rates.
Table 8 and Table 9 show the baud rate and divisor correlation for crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.
Figure 13 shows the crystal clock circuit reference.
divisor
XTAL1 crystal input frequency
prescaler------- --------------- -------------------------------------------------------------⎝⎠⎛⎞
desired baud rate 16×-------------- ---------------------------------------------------------------------------=
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Table 8. Baud rates using a 1.8432 MHz crystal 2304 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 9. Baud rates using a 3.072 MHz crystal 2304 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40
7200 27 1.23
9600 20
19200 10
38400 5
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Register descriptionsEach register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
Table 10.
[1] MCR[7] can only be modified when EFR[4] is set.
[2] Accessed by a combination of address pins and register bits.
[3] Accessible only when LCR[7]is logic1.
[4] Accessible only when LCR is set to 1011 1111 (BFh).
[5] Accessible only when EFR[4]= 1 and MCR[6]= 1, that is, EFR[4] and MCR[6] are read/write enables.
[6] Accessible only when CS= 0, MCR[2]= 1, and loopback is disabled (MCR[4]=0).
Table 10. Register map - read/write properties 0 0 Receive Holding Register (RHR) Transmit Holding Register (THR) 0 1 Interrupt Enable Register (IER) Interrupt Enable Register 1 0 Interrupt Identification Register (IIR) FIFO Control Register (FCR) 1 1 Line Control Register (LCR) Line Control Register 0 0 Modem Control Register (MCR)[1] Modem Control Register[1] 0 1 Line Status Register (LSR) 1 0 Modem Status Register (MSR) 1 1 ScratchPad Register (SPR) ScratchPad Register 0 0 Divisor Latch LSB (DLL) [2][3] divisor latch LSB [2][3] 0 1 Divisor Latch MSB (DLM) [2][3] divisor latch MSB [2][3] 1 0 Enhanced Feature Register (EFR) [2][4] Enhanced Feature Register [2][4] 00Xon1 word [2][4] Xon1 word [2][4] 01Xon2 word [2][4] Xon2 word [2][4] 10Xoff1 word [2][4] Xoff1 word [2][4] 11Xoff2 word [2][4] Xoff2 word [2][4] 1 0 Transmission Control Register (TCR) [2][5] Transmission Control Register [2][5] 1 1 Trigger Level Register (TLR) [2][5] Trigger Level Register [2][5] 1 1 FIFO ready register [2][6]
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOsTable 11 lists and describes the SC68C752B internal registers.
[1] These registers are accessible only when LCR[7]=0.
[2] This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
[3] The Special register set is accessible only when LCR[7] is set to a logic 1.
[4] Enhanced Feature Register; XON1/XON2 and XOFF1/XOFF2 are accessible only when LCR is set to ‘BFh’.
Table 11. SC68C752B internal registers
General register set[1]
Special register set[3]
Enhanced register set[4]
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Remark: Refer to the notes under Table 10 for more register access information.
7.1 Receiver Holding Register (RHR)The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the line control register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
Remark: In this case, characters are overwritten if overflow occurs.If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
7.2 Transmit Holding Register (THR)The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.3 FIFO Control Register (FCR)This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 12
shows FIFO Control Register bit settings.
Table 12. FIFO Control Register bits description7:6 FCR[7] (MSB),
FCR[6] (LSB)
RX trigger. Sets the trigger level for the receive FIFO.
00 - 8 characters
01 - 16 characters
10 - 56 characters
11 - 60 characters
5:4 FCR[5] (MSB),
FCR[4] (LSB)
TX trigger. Sets the trigger level for the transmit FIFO.
00 - 8 spaces
01 - 16 spaces
10 - 32 spaces
11 - 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function. FCR[3] DMA mode select.
logic 0= Set DMA mode ‘0’
logic 1= Set DMA mode ‘1’ FCR[2] Reset transmit FIFO.
logic 0= No FIFO transmit reset (normal default condition)
logic 1= Clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[1] Reset receive FIFO.
logic 0= no FIFO receive reset (normal default condition)
logic 1= Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
logic 0= disable the transmit and receive FIFO (normal default
condition)
logic 1= enable the transmit and receive FIFO
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.4 Line Control Register (LCR)This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR. T able 13
shows the Line Control Register bit settings.
Table 13. Line Control Register bits description LCR[7] Divisor latch enable.
logic 0= divisor latch disabled (normal default condition)
logic 1= divisor latch enabled LCR[6] Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TXn output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic0.
logic 0= no break condition (normal default condition)
logic 1= forces the transmitter output (TXn) to a logic 0 to alert the
communication terminal to a line break condition LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3]=1).
logic0= parity is not forced (normal default condition)
LCR[5]= logic 1 and LCR[4]= logic 0: parity bit is forced to a logic 1 for the
transmit and receive data.
LCR[5]= logic 1 and LCR[4]= logic 1: parity bit is forced to a logic 0 for the
transmit and receive data. LCR[4] Parity type select.
logic 0= odd parity is generated (if LCR[3]=1).
logic 1= even parity is generated (if LCR[3]=1). LCR[3] Parity enable.
logic 0= no parity (normal default condition).
logic 1= a parity bit is generated during transmission and the receiver checks for received parity. LCR[2] Number of stop bits. Specifies the number of stop bits.= 1 stop bit (word length= 5, 6, 7, 8)= 1.5 stop bits (word length=5)= 2 stop bits (word length= 6, 7, 8)
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.= 5 bits= 6 bits= 7 bits= 8 bits
NXP Semiconductors SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.5 Line Status Register (LSR)Table 14 shows the Line Status Register bit settings.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the receive FIFO (next character to be read). The LSR[4:2] registers do not
physically exist, as the data read from the receive FIFO is output directly onto the output
data bus, D[4:2], when the LSR is read. Therefore, errors in a character are identified by
reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the receive FIFO, and is cleared only
when there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the receive FIFO read pointer. The
receive FIFO read pointer is incremented by reading the RHR.
Table 14. Line Status Register bits description LSR[7] FIFO data error.
logic 0= No error (normal default condition)
logic 1= At least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO. LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0= transmitter hold and shift registers are not empty
logic 1= transmitter hold and shift registers are empty LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0= Transmit Hold Register is not empty
logic 1= Transmit Hold Register is empty. The processor can now load up to
64 bytes of data into the THR if the TX FIFO is enabled. LSR[4] Break interrupt.
logic0= no break condition (normal default condition)
logic1= A break condition occurred and associated byte is 00, that is,
RXn was LOW for one character time frame. LSR[3] Framing error.
logic0= no framing error in data being read from receive FIFO (normal
default condition)
logic1= Framing error occurred in data being read from receive FIFO, that is, received data did not have a valid stop bit.
2LSR[2] Parity error.
logic 0= no parity error (normal default condition)
logic 1= parity error in data being read from receive FIFO LSR[1] Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1= overrun error has occurred LSR[0] Data in receiver.
logic 0 = no data in receive FIFO (normal default condition)
logic 1= at least one character in the receive FIFO
