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SC28L202A1DGG
Dual universal asynchronous receiver/transmitter (DUART)
Product data sheet
Supersedes data of 2004 Apr 16
2005 Nov 01
Philips Semiconductors Product data sheet
SC28L202Dual universal asynchronous receiver/transmitter
(DUART)
DESCRIPTION 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FEATURES 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORDERING INFORMATION 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONFIGURATIONS 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL) 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA) 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OVERALL DESCRIPTION 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BRIEF DESCRIPTION OF FUNCTIONAL BLOCKS 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Circuits 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UARTs 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitters and Receivers 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Character and Address Recognition 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flow Control 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Modes and Software 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DETAILED DESCRIPTIONS 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Circuit 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Ports 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Operation 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Operation 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbitrating Interrupt Structure 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROGRAMMING THE HOST INTERFACE 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER DESCRIPTION AND PROGRAMMING NOTE 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Registers that control Global Properties of the 28L202 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCCR – Global Configuration Control Register 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCCR(7:6) DACKN Assertion 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCCR(5:3): Reserved 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCCR(2:1): Interrupt vector configuration 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCCR(0): Interrupt Status Masking 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFSR A and B Special Feature & Status Register 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFSR(7:4) Reserved 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFSR(3) Status of loop back error check. 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFSR(0) Reserved 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRR Test and Revision Register. 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRR[7] Test 2 Enable 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRR[6:0] – Chip Revision Code 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STCR – Scan Test Control Register. 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SES – System Enable Status Register, A and B 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EOS – Enhanced Operation Status Register 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Registers 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
These registers are generally concerned with formatting, transmitting and receiving data. 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR0 – Mode Register 0, A and B 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR0[7] Fixed length Watchdog Timer 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR0[5:4] – Tx interrupt fill level. 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR0[3] – FIFO Size 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR0[2:0] – Legacy Baud Rate Group Selection 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 – Mode Register 1, A and B 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1[7] – Receiver Request to Send (hardware flow control) 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1[6] – Receiver interrupt control bit 1. 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 [5] – Error Mode Select and sub modes 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1[4:3] – Parity Mode Select 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1[2] – Parity Type Select 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1[1:0] – Bits per Character Select 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR2 – Mode Register 2, A and B 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR2[7:6] – Mode Select 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR2[7:6] = b’00 Normal Mode 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR2[7:6] = b’01 Automatic Echo 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Philips Semiconductors Product data sheet
SC28L202Dual universal asynchronous receiver/transmitter
(DUART)
MR3 – Mode Register 3, A and B 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR3[7 & 6] Xon/Xoff Character Stripping 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR3[5:4] Reserved 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR3[3:2] Xon/Xoff Processing 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR3[1:0] Address Recognition 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxCSR – Receiver Clock Select Register A and B 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxCSR Transmitter Clock Select Register A and B 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rx and Tx Clock Select Table 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRx – Command Register Extension, A and B 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CR[7] – Lock Tx and Rx enables. 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CR[6] – Enable Transmitter 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CR[5] – Enable Receiver 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CR[4:0] – Miscellaneous Commands (See Table below) 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND REGISTER EXTENSION TABLE A and B 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR – Channel Status Register A and B 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR[7] – Received Break 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR[6] – Framing Error (FE) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR[5] – Parity Error (PE) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR[4] – Overrun Error (OE) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR [3] – Transmitter Idle (Tx Idle) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR[2] – Transmitter Ready (TxRDY) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR[1] – RxFIFO Full (RxFULL) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR[0] – Receiver Ready (RxRDY) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR – Interrupt Status Register A and B 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[7] – Input Change of State. 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[6] Fixed Watchdog Time-out. 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[5] – Address Recognition Status Change. 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[4] – Xon/Xoff Status Change. 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[3] – Counter Timer Status 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[2] – Change in Channel Break Status. 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[1] – RxINT. (Also Rx DMA hand shake at I/O pins) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[0] – TxINT. (Also Tx DMA hand shake at I/O pins) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR – Interrupt Mask Register A and B 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR[7] COS enable 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR[6] Fixed Watchdog Enable 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR[5] Address recognition enable 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR[4] Xon/Xoff Enable 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR[3] Counter/Timer Enable 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR[1] Receiver (Rx) Enable 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR[0] Transmitter (Tx) Enable 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxFIFO – Receiver FIFO, A and B 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxFIFO – Transmitter FIFO, A and B 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxFIL – Receiver FIFO Interrupt Level, A and B 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxFL – Receiver FIFO Fill Level Register 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxFIL – Transmitter FIFO Interrupt Level A and B 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxEL – Transmitter FIFO Empty Level Register 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers for Character Recognition 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XonCR – Xon/Xoff Character Register A and B 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XoffCR – Xoff Character Register A and B 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARCR – Address Recognition Character Register A and B 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XISR – Xon–Xoff Interrupt Status Register A and B (Reading this register clears XISR(7:4)) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XISR[7:6] Received X Character Status. 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XISR[5:4] Automatic transmission Status. 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XISR[3:2] TxD Condition of the automatic flow control status. 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XISR[1:0] TxD X character Status. 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WCXER Watch Dog, Character, Address and X Enable Register – A and B 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Counters, Timers and Baud Rate generators 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PBRGPU – Programmable BRG Timer Reload Registers, Upper 0 and 1 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PBRGPL – Programmable BRG Timer Reload Registers, Lower 0 and 1 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTCS 0 and 1 – Counter Timer clock source 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTVU – Counter Timer Value Registers, Upper 0 and 1 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTVL – Counter timer Value Registers, Lower 0 and 1 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Philips Semiconductors Product data sheet
SC28L202Dual universal asynchronous receiver/transmitter
(DUART)
Registers of the Arbitrating Interrupt System and Bidding control 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICR – Interrupt Control Register 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UCIR – Update CIR 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CIR – Current Interrupt Register 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IVR – Interrupt Vector Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modification of the IVR 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GICR – Global Interrupting Channel Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GIBCR – Global Interrupting Byte Count Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GITR – Global Interrupting Type Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GRxFIFO – Global RxFIFO Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GTxFIFO – Global TxFIFO Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCRBRK – Bidding Control Register – Break Change, A and B 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCRCOS – Bidding Control Register – Change of State, A and B 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCRx – Bidding Control Register – Xon/Xoff, A and B 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCRA – Bidding Control Register – Address, A and B 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCR C/T – Bidding Control Register –C/T, 0 and 1 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BCRLBE – Bidding Control Register – Received Loop Back Error 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers of the I/O ports 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPCRL – Input Port Change Register Lower Nibble, A and B (n = A for A, n = B for B) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPCRU – Input Port Change Register Upper Nibble, A and B (n = A for A, n = B for B) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPR – Input Port Register, A and B (n = A for A, n = B for B) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPCE – Input Change Detect Enable, A and B (n = A for A, n = B for B) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/OPCR 0 – I/O Port Configuration Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/OPCR 1 – I/O Port Configuration Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/OPCR 2 – I/O Port Configuration Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/OPCR 3 – I/O Port Configuration Register 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOPR A and SOPR B – Set the Output Port Bits (OPR A and OPR B) 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROPR A and ROPR B – Reset ROPR Output Port Bits (OPR A and OPR B) 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPR – Output Port Register, A and B (n = A for A, n = B for B) 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THE REGISTERS FOR COMPATIBILITY WITH PREVIOUS DUARTS 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REGISTER DESCRIPTIONS Mode Registers 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 Mode Register 1 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 A[7] – Channel A Receiver Request–to–Send Control (Flow Control) 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1[6] – Receiver interrupt control bit 1. See description under MR0[6]. 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 A[5] – Channel A Error Mode Select 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 A[4:3| – Channel A Parity Mode Select 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 A[2] – Channel A Parity Type Select 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 A[1:0] – Channel A Bits Per Character Select 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR2 Mode Register 2 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR Status Register 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR A[7] – Received Break 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR A[6] – Channel A Framing Error 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR A[5] – Channel A Parity Error 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR A[4] – Channel A Overrun Error 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR A[3] – Channel A Transmitter Empty (TxEMT A) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR A[2] – Channel A Transmitter Ready (TxRDY A) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR A[1] – Channel A FIFO Full (FFULL A) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR A[0] – Channel A Receiver Ready (RxRDY A) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR B – Channel B Status Register 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR A – Channel A Clock Select Register CSR A [7:4] – Channel A Receiver Clock Select 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR Clock Select Register 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR A [3:0] – Channel A EXTERNAL Transmitter Clock Select 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR B [7:4] – Channel B Receiver Clock Select 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CSR B [3:0] – Channel B Transmitter Clock Select 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rx FIFO Register. For characters shorter than 8 bits the unused bits are set to zero 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tx FIFO register. For characters shorter than 8 bits the unused bits are set to zero 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CR A and B Command Register 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CR Command Register 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND REGISTER TABLE A and B 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPCR Input Port Configuration Register 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPCR [7:4] I/03A, I/O2 A, I/O1 A, I/O0 A Change–of–State 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPCR [3:0] I/O3 A, I/O2 A, I/O1 A, I/O0 A logical level of I/O pin. 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Philips Semiconductors Product data sheet
SC28L202Dual universal asynchronous receiver/transmitter
(DUART)
ISR – Interrupt Status Register 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[7] – Input Port Change Status 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[6] – Channel B Change In Break 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[5] – Rx B Interrupt 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[4] – Tx B Interrupt 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[3] – Counter Ready. 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[2] – Channel A Change in Break 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[1] – Rx A Interrupt 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISR[0] – Tx A Interrupt 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IMR – Interrupt Mask Register 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTPU Counter Timer Preset Upper (Counter/Timer 0) 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTPL Counter –Timer Preset Lower (Counter/Timer 0) 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTVU Counter Timer Value Upper (Counter/Timer 0) 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTVL Counter –Timer Value Lower (Counter/Timer 0) 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IVR Interrupt Vector register in 68K mode and General purpose read write register in the x86 mode 48. . . . . . . . . . . . . . . . . . . . . . . . .
IPR Input Port Register I/O(6:0) A 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPCR Output Port Configuration Register. Controls [7:2] B 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOPR – Set Bits in the OPR 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROPR – Reset Bits in the OPR 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPR Output Port Register 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER MAPS 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REGISTER MAP DETAIL (based on 28L92) 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER MAP 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER MAP 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER MAP 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL TIMING CONSIDERATIONS FOR THE SC28L202 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC ELECTRICAL CHARACTERISTICS (NOMINAL 5 VOLTS) 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS (NOMINAL 5 VOLTS) 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC ELECTRICAL CHARACTERISTICS (NOMINAL 3.3 VOLTS) 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS (NOMINAL 3.3 VOLTS) 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING DIAGRAMS 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Philips Semiconductors Product data sheet
SC28L202Dual universal asynchronous receiver/transmitter
(DUART)
LIST OF FIGURES

Figure 1. 80xxx TSSOP56 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2. 68xxx TSSOP56 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3. Active area in 68K mode. 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4. Reset Timing (80XXX mode) 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5. Reset Timing (68XXX mode) 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6. Bus Timing (80XXX mode) 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7. Bus Timing (Read Cycle) (68XXX mode) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8. Bus Timing (Write Cycle) (68XXX mode) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9. Interrupt Cycle Timing (68XXX mode) 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10. Port Timing 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11. Interrupt Timing (80xxx mode) 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12. Clock Timing 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13. Transmitter External Clocks 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14. Receiver External Clock 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15. Transmitter Timing 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16. Receiver Timing 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17. Wake-Up Mode 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18. Test Conditions on Outputs 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm (SOT364-1) 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIST OF TABLES

Table 1. Interrupt Values 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2. SC28L202 REGISTER BIT DESCRIPTIONS 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3. Receiver FIFO Interrupt Fill Level MR0(3)=0 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4. Receiver FIFO Interrupt Fill Level MR0(3)=1 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5. Transmitter FIFO Interrupt Fill Level MR0(3)=0 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6. Transmitter FIFO Interrupt Fill Level MR0(3)=0 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7. SC28L92 Register Addressing READ (RDN = 0) WRITE (WRN = 0) 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8. Baud Rate Generator Characteristics 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9. Receiver FIFO Interrupt Fill Level MR0(3)=0 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10. Receiver FIFO Interrupt Fill Level MR0(3)=1 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11. Transmitter FIFO Interrupt Fill Level MR0(3)=0 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12. Transmitter FIFO Interrupt Fill Level MR0(3)=1 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13. Baud Rate (Base on a 14.7456 MHz crystal clock) 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14. ACR 6:4 Field Definition 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1. Interrupt Values 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2. SC28L202 REGISTER BIT DESCRIPTIONS 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3. Receiver FIFO Interrupt Fill Level MR0(3)=0 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4. Receiver FIFO Interrupt Fill Level MR0(3)=1 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5. Transmitter FIFO Interrupt Fill Level MR0(3)=0 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6. Transmitter FIFO Interrupt Fill Level MR0(3)=0 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7. SC28L92 Register Addressing READ (RDN = 0) WRITE (WRN = 0) 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8. Baud Rate Generator Characteristics 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9. Receiver FIFO Interrupt Fill Level MR0[3] = 0 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10. Receiver FIFO Interrupt Fill Level MR0[3] = 1 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11. Transmitter FIFO Interrupt Fill Level MR0[3] = 0 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12. Transmitter FIFO Interrupt Fill Level MR0[3] = 1 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13. Baud Rate (Base on a 14.7456 MHz crystal clock) 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Philips Semiconductors Product data sheet
SC28L202Dual UART
DESCRIPTION

The 28L202 is a high performance dual UART. Its functional and
programming features closely match but greatly extend those of
previous Philips dual channel UARTs. Its configuration on power up
is similar that of the SC26C92. Its differences from the SC26C92
are: 256-character receiver, 256 character transmit FIFOs, 3 V and
5 V compatibility, 8 I/O ports for each UART—16 total, arbitrating
interrupt system and overall faster bus and data speeds. It is
fabricated in an advanced 0.5 micron CMOS process.
It is a member of the IMPACT line of Data Communications parts
Pin programming will allow the device to operate with either the
Motorola or Intel bus interface by changing the function of some pins
(reset is inverted, DACKN, and IACKN enabled for example).
The Philips Semiconductors 28L202 Dual Universal Asynchronous
Receiver/Transmitter (DUART) is a single-chip CMOS-LSI
communications device that provides two full-duplex asynchronous
receiver/transmitter channels in a single package. It interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system. The use of the Interrupt system provides
intelligent interrupt vectors.
The operating mode and data format of each channel may be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of twenty-seven
fixed baud rates; a 16X clock derived from one of two programmable
counter/timers, or an external 1X or 16X clock. The baud rate
generator and counter/timer can operate directly from a crystal or
from external clock inputs. The ability to independently program the
operating speed of the receiver and transmitter make the DUART
particularly attractive for dual-speed channel applications such as
clustered terminal systems and bridges.
Each receiver and transmitter is buffered by 256 character FIFOs to
nearly eliminate the potential of receiver overrun, transmitter
underrun and to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability (Xon/Xoff and
RTS/CTS) is provided to disable a remote transmitter when the
receiver buffer is full.
Also provided on the 28L202 is a multipurpose 8-bit I/O for each
channel. These can be used as general-purpose I/O ports or can be
assigned specific functions (such as clock inputs or status and
interrupt outputs) under program control. Normally they will be used
for modem control and DMA interface. All ports have change of state
detectors and input sections are always active making output
signals available to the internal circuits and the control processor.
The 28L202 is available in a 52–pin TSSOP package. For other
package options, contact Philips.
FEATURES
Member of IMPACT family: 3.3 V to 5.0 V , –40°C to +85°C and
80xx or 68k bus interface (I/M modes) for all devices. Bit-by-bit real time transmission error check for high data integrity
systems. Dual full-duplex independent asynchronous receiver/transmitters 256 character FIFOs for each receiver and transmitter Three character recognition system per channel, used as: General purpose character recognition Xon/Xoff character recognition Address recognition Wake up (multi-drop or ‘9 bit’) mode System provides 4 levels of automation on a recognition event Programmable data format 5 to 8 data bits plus parity and 9 bit mode Odd, even, no parity or force parity 9/16,1, 1.5 or 2 stop bits 16-bit programmable Counter/Timer Programmable baud rate for each receiver and transmitter
selectable from: 27 fixed rates: 50 to 2.0 Meg baud (includes MIDI rate) Other baud rates via external clocks and C/T Programmable user-defined rates derived from a programmable
Counter/timer External 1X or 16X clock Parity, framing, and overrun error detection Line break detection and generation; false start bit detection Programmable channel mode Normal (full-duplex) Automatic echo Local loop back Remote loop back Multi-drop mode (also called ‘wake-up’ or ‘9-bit’) Multi-function 8 bit I/O input port per channel loosely assigned to
each channel. Can serve as clock or control inputs Change of state detection on eight inputs Inputs have typically >100 MΩ pull-up resistors Modem and DMA interface Versatile arbitrating interrupt system Interrupt system totally supports ‘single query’ polling Output port can be configured to provide a total of up to six
separate interrupt type outputs that may be wire-ORed
(switched to open drain). Each FIFO can be independently programmed for any of 256
interrupt levels Watch dog timer for each receiver Maximum data transfer rates: 1X – 3 Mb/sec, 16X – 2 Mb/sec Automatic wake-up mode for multi-drop applications Start-end break interrupt/status Detects break which originates in the middle of a character On-chip crystal oscillator Power down mode at less than 10 μa Receiver time-out mode
Philips Semiconductors Product data sheet
SC28L202Dual UART
ORDERING INFORMATION
PIN CONFIGURATIONS
Figure 1. 80xxx TSSOP56
Figure 2. 68xxx TSSOP56
Philips Semiconductors Product data sheet
SC28L202Dual UART
PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL) (see Figure 1)
Philips Semiconductors Product data sheet
SC28L202Dual UART
CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA) (see Figure 2)
Philips Semiconductors Product data sheet
SC28L202Dual UART
OVERALL DESCRIPTION

The SC28L202 is composed of several functional blocks. They are
listed in the approximate order of hierarchy as seen from the pins of
the device. Bus interface. 68K or x86 format Timing Circuits I/O Ports UARTs Transmitters and Receivers Transmitter real time error test FIFO Structures Arbitrating Interrupt Structure Character & Address Recognition Flow Control Test and Software compatibility with previous Philips (Signetics)
UARTs
BRIEF DESCRIPTION OF FUNCTIONAL BLOCKS
Bus Interface
The Two basic modes of Bus Interface

The bus interface operates in ‘68K’ or ‘x86’ format as selected by
the I/M pin. The signals used by this section are the Address, Data
bus, Chip select, read/write, Data acknowledge and Interrupt
acknowledge and Interrupt request. Assertion of DACKN requires
two edges of the Sclk after the assertion of CEN. The default mode
is the x86 mode. Pin or register programming may change it to the
68K mode.
Timing Circuits
Crystal Oscillator

The crystal oscillator is the main timing element for the 28L202.
It is nominally set at 14.7456 MHz. Operation with a crystal as a
frequency standard is specified from 7 MHz to 16.2 MHz. The use of
an external clock allows all frequencies to 50 MHz. Clock prescalers
are provided to match various available system clocks to those
needed for baud rate generation.
NOTE: if an external clock is used X2 should not drive more

than 2 CMOS or 2 TTL equivalents.
Fixed Rate BRG

The BRG is the baud rate generator, is driven by the X1/Sclk input
through a programmable prescale divider. It generates all of the 27
‘fixed’ internal baud rates. This baud rate generator is designed to
generate the industry standard baud rates from a 14.7456 MHz
crystal or clock frequency. X1/Sclk frequencies different from
14.7456 MHz will cause the ‘fixed’ baud rates to change by exactly
the ratio of 14.7456 to the different frequency.
Counter-Timer

The two counter-timers are programmable 16 bit ‘down’ counters. It
provides miscellaneous baud rates, timing periods and acts as an
extra watchdog timer for the receivers. It has 8 programmable clock
sources derived from internal and external signals. It may also act
as a character counter for the receiver. Interrupts from the counter
the receivers and transmitters and may be delivered to I/O ports. It
has 8 programmable clock sources derived from internal and
external signals.
I/O ports

The SC28L202 is provided with 16 I/O ports. These ports are true
input and/or output structures and are equipped with a change of
state detector. The input circuit of these pins is always active. Under
program control the ports my display internal signals or static logic
levels. The functions represented by the I/O ports include hardware
flow control. Modem signals, signals for interrupt conditions or
various internal clocks and timing intervals. Noisy inputs to the I/O
ports are filtered (de-bounced) by a 38.4 KHz clock. Change of state
detectors are provided for each pin and are always available.
UARTs

The UARTs are fully independent, full duplex and provide all normal
asynchronous functions: 5 to 8 data bits, parity odd or even,
programmable stop bit length, false start bit detection. Also provided
are 256 byte FIFOs Xon/Xoff software flow. The BRG,
Counter-timer, or external clocks provide the baud rates. The
receivers and transmitters may operate in either the ‘1x’ or ‘16x’
modes.
The control section recognizes two address schemes. One is the
subset of the other: a four (4) bit and an eight (7) bit address
spaces. The purpose of this is to provide a large degree of software
compatibility with previous Philips/Signetics UARTs.
Transmitters and Receivers

The transmitters and receivers are independent devices capable of
full duplex operation. Baud rates, interrupt and status conditions are
under separate control. Transmitters have automatic simplex
‘turnaround’. Receivers have RTS and Xon/Xoff flow control and a
three character recognition system.
Transmitter Real Time Error Check

This is a circuit used to verify that the correct data arrived at the
destination. It is done real time with one or two bit times of
programmable delay. The purpose is to relieve the processor of the
burden of byte-by-byte checking and the delay in sending a block of
data back for processor checking.
The function is that the receiver returns the data received back to
the transmitting station where it is compared to a delayed version of
the data sent. If an error occurs, and interrupt may be generated for
the particular bit that is in error. This is essentially a loop back
condition where circuits internal to the UART delay and compare the
data.
It is suggested that a very high priority be set in the interrupt
arbitration bid control register for this interrupt when in use.
FIFO Structures

The FIFO structure is 256 bytes for each of the four FIFOs in the
DUART. They are organized as 11 bit words for the receiver and 8
bye words for the transmitter. The interrupt level may be set at any
value from 0 to 255. The interrupt level is independently set for each
FIFO.
FIFO interrupt and DMA fill/empty levels are controlled by the RxFIL
and TxFIL registers which may set any level of the from 0 to 255.
The signals associated with the FIFO fill levels are available to the
I/O pins (for interrupt or DMA) and to the arbitrating interrupt system
for ‘fine tuning’ of the arbitration authority.
Philips Semiconductors Product data sheet
SC28L202Dual UART
processor. The advantageous feature of this system is the
presentation of the context of the interrupt. It is presented in both a
current interrupt register and in the interrupt vector. The context of
the interrupt shows the interrupting channel, identifies which of the
18 possible sources in requesting interrupt service and in the case
of a receiver or transmitter gives the current fill level of the FIFO.
The content of the current interrupt register also drives the Global
Registers of the interrupt system. These registers are indirect
addresses (pointers) to the interrupt source requesting service.
Programming of Bid Control Registers allows the interrupt level of
any source to be varied at any time over a range of 256 levels.
Character and Address Recognition

The character recognition system is designed as a general-purpose
system. There is one for each UART. Each recognition block stores
up to three characters. The recognition is done on a byte boundary
and sets status and interrupt when recognition events occur. Three
modes of automatic operation are provided for the in-band flow
control and three modes of automatic operation are provided for
address recognition. Both in-band flow control and address
recognition may also be completely under the control of the host
processor.
A subset of the recognition system is Xon/Xoff character recognition
and the recognition of the multi-drop address character. If Xon/Xoff
or multi-drop function is enabled the recognition system passes the
information about the recognition event to the appropriate receiver
or transmitter state machine for execution. In any case the
information about a recognition event is available to the interrupt
system and to the control processor.
Flow Control

Flow control is implemented in either the traditional RTS/CTS
protocol or in the ‘inbound’ Xon/Xoff method. Both may be controlled
by fully/partially automatic methods or by interrupt generation.
Test Modes and Software

Four test modes are provided to verify UART function and processor
interface integrity. The first three are Auto echo, Local Loop Back,
and Remote Loop Back. Through local loop back the software
developer may verify all of the interrupt, flow control; the hardware
designer verify all of the timing and pin connections. This information
is obtained without any recourse to external test equipment, logic
analyzers or terminals.
The fourth, Receiver Error Loop back verification, employs a method
of automatic checking (accounting for transmission delays) of the
transmitted data to as echoed back through the remote receiver.
Errors generate interrupt and status events.
DETAILED DESCRIPTIONS
NOTE: For the convenience of the reader some paragraphs

of the following sections are repeated in descriptions of
closely linked functions described in other sections.
Bus Interface

The bus interface operates in two modes selected by the I/M pin. If
this pin is HIGH the signals DACKN signal is not generated or used
and data flow to and from the chip is controlled by the state the
CEN, RDN, WRN pin combination. If the I/M pin is tied low the data
is written to the device when the DACKN pin is asserted low by the
data bus pins. Addressing of the various functions of the DUART is
through the address bus A(6:0). Data is presented on the 8-bit data
bus.
DACKN Cycle

When operating in the ‘68K’ mode, bus cycle completion is indicated
by the DACKN pin (an open-drain signal) going LOW. The timing of
DACKN is controlled by GCCR[7:6] where three time delays area
available. The delay begins with the falling edge of CEN. DACKN is
presented after 1/2 to three periods of the X1/SCLK. The minimum
time will be two edges of the X1/SCLK and will be realized when the
bus cycle begins just before the transition of X1/SCLK. Usually in
this mode the address and data are set up with respect to the
leading edge of the bus cycle. Timing diagrams for this mode are
drawn with DACKN in consideration. When CEN is withdrawn before
DACKN occurs, the generation of the DACKN signal and bus cycle
will be terminated. In this case, the bus timing will return to that of
Intel type timing for that particular cycle. This timing should not be
less than the minimum read or write pulse.
The DACKN pin is an open-drain driver. At the termination of an
access to the L202 DACKN drives the pin to high impedance until
the next DACKN cycle. This will occur at the termination of the CEN
or IACKN cycle.
NOTE: The faster X86 timing may be used in the 68K mode IF the

bus cycles are faster than 1/2 period of the Sclk clock. Withdrawing
CEN before DACKN prevents the generation of DACKN. In this case
bus timing is effectively that of the X86 mode.
When operating in the ‘x86’ mode DACKN is not generated. Data is
written on the termination of CEN or WRN whichever one occurs
first. Read data is presented from the leading edge of the read
condition (CEN and RDN both low).
In the 68K mode data is written to the registers on the rise of CEN or
the fall of DACKN, whichever one occurs first. Data on a read cycle
will become valid with respect to the fall of CEN. It will always be
valid at the fall of DACKN.
IACKN Cycle, Update CIR

When the host CPU responds to the interrupt, it will usually assert
the IACKN signal low. This will cause the intelligent interrupt system
of the DUART to generate an IACKN cycle in which the condition of
the interrupting source is determined. When IACKN asserts, the last
valid of the interrupt arbitration cycle is captured in the CIR. The
value captured presents all of the important details of the highest
priority interrupt at the moment the IACKN (or the ‘Update CIR’
command) was asserted. Due to system interrupt latency the
interrupt condition captured by the CIR may not be the condition that
caused the initial assertion of the interrupt.
The Dual UART will respond to the IACKN cycle with an interrupt
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or when ‘Interrupt Vector Modification’ is
enabled via ICR, it may contain codes for the interrupt type and/or
interrupting channel. This allows the interrupt vector to steer the
interrupt service directly to the proper service routine. The interrupt
value captured in the CIR remains until another IACKN or ‘Update
CIR’ command is given to the DUART. The interrupting channel and
interrupt type fields of the CIR set the current ‘interrupt context’ of
the DUART. The channel component of the interrupt context allows
the use of Global Interrupt Information registers that appear at fixed
positions in the register address map. For example, a read of the
Philips Semiconductors Product data sheet
SC28L202Dual UART
interrupt parameters and for writing to and reading from FIFOs
without explicitly addressing them.
The CIR will load with 0x00 if IACKN or Update CIR is asserted
when the arbitration circuit is NOT asserting an interrupt. In this
condition there is no arbitration value that exceeds the threshold
value. When Interrupt vector modification is active in this situation
the interrupt vector bits associated with the CIR will all be zero. A
zero type field indicates nothing with in the DUART is requiring
processor service.
NOTE: IACKN is essentially a special read action where the value of

the interrupt vector is presented to the data bus.
Timing Circuit
Crystal Oscillator

The crystal oscillator operates directly from a crystal, tuned between
7.0 MHz and 16.2 MHz connected across the X1/Sclk and X2 inputs
with a minimum of external components. BRG values listed for the
clock select registers correspond to a 14.7456 MHz crystal
frequency. Use of different frequencies will change the ‘standard’
baud rates by precisely the ratio of 14.7456 MHz to the different
crystal frequency.
An external clock up to 50 MHz frequency range may be connected
to X1/Sclk pin. If an external clock is used instead of a crystal,
X1/Sclk must be driven and X2 left floating or driving a load of not
more than 2 CMOS or TTL equivalents. The X1/Sclk clock serves as
the basic timing reference for the baud rate generator (BRG) and is
available to the programmable BRG (PBRG), counter-timers, control
logic and the UART receivers and transmitters.
Baud Rate Generator BRG

The baud rate generator operates from the oscillator or external
X1/Sclk clock input and generates 27 commonly used data
communications baud rates (including MIDI) ranging from 50 baud
to 921.6K baud. These common rates may be increased (up to
3000K baud) when faster clocks are used on the X1/Sclk clock
input. (See Receiver and Transmitter Clock Select Register
descriptions.) All of these are available simultaneously for use by
any receiver or transmitter. The clock outputs from the BRG are at
16X the actual baud rate.
Please see counter timer description for a description of the
frequency error that the asynchronous protocol may tolerate.
Depending on character length it varies from 4.1% to 6.7%.
Counter-Timer

The two Counter/Timers are programmable 16 bit dividers that are
used for generating miscellaneous clocks or generating timeout
periods or counting characters received by the receivers. Interrupts
may be generated any time the counter passes through 0x00. These
clocks may be used by any or all of the receivers and transmitters in
the DUART or may be directed to an I/O pin for miscellaneous use.
Counter/Timer programming

The counter timer is a 16-bit programmable divider that operates in
one of four modes: character count, counter, timer, and time out.
Character count counts characters. The timer mode generates a
square wave. In the counter mode it generates a time delay. In the
time out mode it monitors the time between received characters.
The C/T uses the numbers loaded into the Counter/Timer Lower
Register (CTPL) and the Counter/Timer Upper Register (CTPU) as
its divisor. The counter timer is controlled with six commands:
Start/Stop C/T, Read/Write Counter/Timer lower register and
Read/Write Counter/Timer upper register. These commands have
slight differences depending on the mode of operation. Please see
Whenever the these timers are selected via the receiver or
transmitter Clock Select register their output will be configured as a
16x clock for the respective receiver or transmitter. Therefore one
needs to program the timers to generate a clock 16 times faster than
the data rate. The formula for calculating ’n’, the number loaded to
the CTPU and CTPL registers, based on a particular input clock
frequency is shown below.
For the timer mode the formula is as follows:� C/T clock input frequency�16� (desired baud rate))
(If the pulse mode is selected, then ‘2’ in the divisor should be ‘1’.
This doubles the C/T output speeds for any given input clock.)
NOTE: ‘n’ may assume a value of 1. In previous Philips data

communications controllers this value was not allowed. The
Counter/Timer Clock Select Register (CTCS) controls the
Counter/Timer input frequency.
The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and receiver
state machines include divide by 16 circuits, which provide the final
frequency and provide various timing edges used in the qualifying
the serial data bit stream. Often this division will result in a
non-integer value: 26.3 for example. One may only program integer
numbers to a digital divider. There for 26 would be chosen. If 26.7
were the result of the division then 27 would be chosen. This gives a
baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage error
of 1.14% or 1.12% respectively, well within the ability of the
asynchronous mode of operation. Higher input frequency to the
counter reduces the error effect of the fractional division.
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is
communicating may also have a small error in the precise baud rate.
In a ‘clean’ communications environment using one start bit, eight
data bits and one stop bit the total difference allowed between the
transmitter and receiver frequency is approximately 4.6%. Less than
eight data bits will increase this percentage.
Programmable Baud Rate Generators. PBRG

Two PBRG Counters (Used only for random baud rate generation)
The two PBRG Timers are programmable 16 bit dividers that are
used for generating miscellaneous clocks. These clocks may be
used by any or all of the receivers and transmitters in the SC28L202
or output to the general purpose I/O pins.
Each timer unit has eight different clock sources available to it as
described in the PBRG clock source Register. Note that the timer
run and stop controls are also contained in this register. The PBRG
counters generate a symmetrical square wave whose half period is
equal in time to the division of the selected PBRG Timer clock
source by the number loaded to the PBRGPU and PBRGPL Preset
Registers. Thus, the output frequency will be the clock source
frequency divided by twice the 16 bit value loaded to these registers.
This is the result of counting down once for the high portion of the
output wave and once for the low portion.
Whenever the these timers are selected via the receiver or
transmitter Clock Select register their output will be configured as a
16x clock for the respective receiver or transmitter. Therefore one
needs to program the timers to generate a clock 16 times faster than
the data rate. The formula for calculating ’n’, the number loaded to
Philips Semiconductors Product data sheet
SC28L202Dual UART
I/O Ports

Eight I/O ports are ‘loosely’ provided for each channel. They may be
programmed to be inputs or outputs. The input circuits are always
active whether programmed as and input or an output. In general a
2-bit code in the I/OPCR (I/O Port Control Register) controls what
function these pins will present. All I/O ports default to high
impedance input state on power up. All 16 I/O pins have a small
pull-up ‘resistor’ that provides approximately 5 μA current.
When calling software written for legacy two channel UARTs
manufactured by Philips (Signetics), be sure I/O pins are set to
input where the legacy software expected an input. Declare I/O
pins as output where the legacy software expected an output.
Input Characteristics of the I/O ports

Eight I/O pins are provided for each channel. These pins are
configured individually to be inputs or outputs. As inputs they may
be used to bring external data to the bus, as clocks for internal
functions or external control signals. Each I/O pin has a ‘Change of
State’ detector. The change detectors are used to signal a change in
the signal level at the pin (Either 0-to-1 or 1-to-0 transitions). The
level change on these pins must be stable for 25 to 50 μs (two
edges of the internally generated 38.4 kHz baud rate clock) before
the detectors will signal a valid change. These are typically used for
interface signals from modems to the DUART and from there to the
host.
Output Port of the I/O ports

The OPR, I/OPCR, MR, and CR registers may control the I/O pins
when configured as outputs. (For the control in the lower 16 position
address space the control register is the OPCR) Via appropriate
programming the pins of the output port may be configures as
another parallel port to external circuits, or they may represent
internal conditions of the UART. When this 8-bit port is used as a
general-purpose output port, the output port pins drive inverse logic
levels of the individual bits in the Output Port Register (OPR). The
OPR register is set and reset by writing to the SOPR and ROPR
addresses. (See the description of the SOPR and ROPR registers).
The output pins will drive the same data polarity of the OPR
registers. The I/OPCR (or the OPCR) register conditions these
output pins to be controlled by the OPR or by other signals in the
chip. Output ports are driven high on hardware reset.
UART Operation
Receiver and Transmitter

The Dual UART has two full duplex asynchronous
receiver/transmitters. The operating frequency for the receiver and
transmitter can be selected independently from the baud rate
generator, the counter, or from an external input. Registers that are
central to basic full-duplex operation are the mode registers (MR0,
MR1 and MR2), the clock select registers (RxCSR and TxCSR), the
command register (CR), the status register (SR), the transmit
holding register (TxFIFO), the receive holding register (RxFIFO),
interrupt status register (ISR) and interrupt mask register (IMR).
MR3 controls the automatic activity or the Xon/Xoff flow control,
Address recognition, multi-drop (‘9-bit’ mode) and general purpose
character recognition. Because MR3 does not exist in legacy
UARTs, these features should be disabled before legacy code is
loaded.
Transmitter Status Bits

The SR (Status Register, one per UART) contains two bits that show
can not be active without TxRDY also being active. These two bits
will go active upon initial enabling of the transmitter.
The transmitter status bits are normally cleared by servicing the
interrupt condition they represent or by Tx reset or Tx disable
commands.
Transmission resumes and the Tx Idle bit is cleared when the CPU
loads at least one new character into the TxFIFO. The TxRDY will
not extinguish until the TxFIFO is completely full. The TxRDY bit will
always be active when the transmitter is enabled and there is at
lease one open position in the TxFIFO.
The transmitter is disabled by a hardware reset, a transmitter reset
in the command register or by the transmitter disable bit also in the
command register (CR). The transmitter must be explicitly enabled
via the CR before transmission can begin. Note that characters
cannot be loaded into the TxFIFO while the transmitter is disabled,
hence it is necessary to enable the transmitter and then load the
TxFIFO. It is not possible to load the TxFIFO and then enable the
transmission.
Note the difference between transmitter disable and transmitter
reset.
Either hardware or software may cause the reset action. When reset
the transmitter stops transmission immediately. The transmit data
output will be driven high, transmitter status bits set to zero and any
data remaining in the TxFIFO is effectively discarded.
The transmitter disable is controlled by the Tx Enable bit in the
command register. Setting this bit to zero will not stop the transmitter
immediately but will allow it to complete any tasks presently
underway. It is only when the last character in the TxFIFO and its
stop bit(s) have been transmitted that the transmitter will go to its
disabled state. While the transmitter enable/disable bit in the
command register is at zero the TxFIFO will not accept any more
characters and the Tx Idle and TxRDY bits of the status register set
to zero.
Transmission of ‘break’

Transmission of a break character is often needed as a
synchronizing condition in a data stream. The ‘break’ is defined as a
start bit followed by all zero data bits by a zero parity bit (if parity is
enabled) and a zero in the stop bit position. The forgoing is the
minimum time to define a break. The transmitter can be forced to
send a break (continuous low condition) by issuing a start break
command via the CR. Once the break starts, the TxD output
remains low until the host issues a command to ‘stop break’ via the
CR or the transmitter is issued a software or hardware reset. In
normal operation the break is usually much longer than one
character time.
1x and 16x modes, Transmitter

The transmitter clocking has two modes: 16x and 1x. Data is always
sent at the 1x rate. However the logic of the transmitter may be
operated with a clock that is 16 times faster than the data rate or at
the same rate as the data i.e. 1x. All clocks selected internally for
the transmitter (and the receiver) will be 16x clocks. Only when an
external clock is selected may the transmitter logic and state
machine operate in the 1x mode. The 1x or 16x clocking makes little
difference in transmitter operation. (This is not true in the receiver)
In the 16X-clock mode the transmitter will recognize a byte in the
TxFIFO within 1/16 to 2/16-bit time and thus begin transmission of
the start bit. In the 1x mode this delay may be up to 2 bit times.
Philips Semiconductors Product data sheet
SC28L202Dual UART
encodes the number of empty positions for presentation to the
interrupt arbitration system. The encoding value is the number of
empty positions. Thus, an empty TxFIFO will bid with the value or
255; when full it will not bid at all; one position empty bids with the
value 0. A Full TxFIFO will not bid since no character is available.
Normally TxFIFO will present a bid to the arbitration system
whenever it has one or more empty positions. The Bits of the
TxFIFO Interrupt Level in the MR0(5:4) allow the user to modify this
characteristic so that bidding will not start until one of four levels
(one or more filled, empty, 16 filled, 240 filled, full) have been
reached. As will be shown later this feature may be used to make
moderate improvements in the interrupt service efficiency. A similar
system exists for the Receiver.
Transmitter

The 28L202 is conditioned to transmit data when the transmitter is
enabled through the command register. The transmitter of the
28L202 indicates to the CPU that it is ready to accept a character by
setting the ISR TxRDY bit in the status register. This condition can
be programmed to generate an interrupt request at I/O4 or IRQN.
When the transmitter is initially enabled the TxRDY and Tx Idle bits
will be set in the status register. When a character is loaded to the
transmit FIFO the Tx Idle bit will be reset. The Tx Idle bit will not set
until the transmit FIFO is empty and the transmit shift register has
finished transmitting the stop bit of the last character written to the
transmit FIFO.
The TxRDY bit is set whenever the transmitter is enabled and the
TxFIFO is not full. Data is transferred from the holding register to
transmit shift register when it is idle or has completed transmission
of the previous character. Characters cannot be loaded into the
TxFIFO while the transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the Tx Idle bit in the Status Register (SR) will be set to 1.
Transmission resumes and the Tx Idle bit is cleared when the CPU
loads a new character into the TxFIFO.
If the transmitter is disabled, it continues operating until the
character currently being transmitted is completely sent out. The
transmitter can be forced to send a continuous Low condition by
issuing a send break command. The transmitter can be reset
through a software command. If it is reset, operation ceases
immediately and the transmitter must be enabled through the
command register before resuming operation.
If CTS option of hardware flow control is enabled (MR2 [4] = 1), the
CTS input at I/O0 or I/O1 must be Low in order for the character to
be transmitted. The transmitter will check the state of the CTS input
at the beginning of each character transmitted. If it is found to be
High, the transmitter will delay the transmission of any following
characters until the CTS has returned to the low state. CTS going
high during the serialization of a character will not affect that
character.
It is an interesting point of the I/O system inputs being always active
that by enabling transmitter to be sensitive the I/O0 or I/O1 and then
controlling the I/O pin as an out put that one is able to control the
RS-485 method) the meaning of the I/O0 B or I/O1 B signals is ‘all
bytes loaded to the transmitter’s FIFO have been transmitted
including the last stop bit(s). See the MR2(5) description for enabling
this automatic function.
Receiver Operation
Receiver

The receiver accepts serial data on the RxD pin, converts the serial
input to parallel format, checks for start bit, stop bit, parity bit (if any),
framing error or break condition, and presents the assembled
character and its status condition to the CPU via the RxFIFO. Three
status bits are FIFOed with each character received. The RxFIFO is
really 11 bits wide: eight data and 3 status. Unused FIFO bits for
character lengths less than 8 bits are set to zero.
It is important to note that in the asynchronous protocol the receiver
logic considers the entire message to be contained within the start
bit to the stop bit. It is not aware that a message may contain many
characters. The receiver returns to its idle mode at the end of each
stop bit! As described below it immediately begins to search for
another start bit, which is normally, of course, immediately
forthcoming.
1x and 16x mode, Receiver

The receiver operates in one of two modes: 1x and 16x. Of the two,
the 16x is more robust and the preferred mode. Although the 1x
mode may allow a faster data rate is does not provide for the
alignment of the receiver 1x data clock to that of the transmitter. This
strongly implies that the 1x clock of the remote transmitter is
available to the receiver; the two devices are physically close to
each other.
The 16x mode operates the receiver logic at a rate 16 times faster
than the 1x data rate. This allows for validation of the start bit length,
the validation of level changes at the receiver serial data input
(RxD), and the validation of the stop bit length. Of most importance
in the 16x mode is the ability of the receiver logic to align the phase
of the internally generated receiver 1x data clock to that of the
received start bit of the remote transmitter. This occurs with an
accuracy of less than 1/16 bit time.
Receiver

The receiver of the 28L202 is conditioned to receive data when
enabled through the command register. The receiver looks for a
High-to-Low (mark-to-space) transition of the start bit on the RxD
input pin. If a transition is detected, the state of the RxD pin is
sampled each 16X clock for 7-1/2 clock periods (16X clock mode) or
at the next rising edge of the bit time clock (1X clock mode). If RxD
is sampled high, (that is the start bit was low less than 7/16 to � bit
time) the start bit is judged invalid and the search for another valid
start bit begins immediately. If RxD is still low, a valid start bit is
assumed and the receiver then continues to sample the input at
one-bit time intervals at the theoretical center of the bit. When the
proper number of data bits and parity bit (if used) have been
assembled, and one half-stop bit has been detected the receiver
loads the byte to the FIFO. The least significant bit is received first.
The data is then transferred to the Receive FIFO and the ISR
RxRDY bit in the SR is set to a 1. This condition can be
programmed to generate an interrupt at IRQN or I/O[4:5] for
channels A or B respectively. If the character length is less than 8
bits, the most significant unused bits in the RxFIFO are set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received with
Philips Semiconductors Product data sheet
SC28L202Dual UART
the receiver operates as if a new start bit had been detected. It then
continues assembling the next character.
The error conditions of parity error, framing error, and overrun error
(if any) are written to the SR at the received character boundary.
This is just before the RxRDY status bit is set.
A break condition is detected when RxD is Low for the entire
character including the parity bit, if used, and stop bit. When a break
is found a character consisting of all zeros will be loaded into the
RxFIFO, the received break bit in the SR and the ‘change of break’
bit in the ISR are set to 1 and the receiver ready is set in the SR.
The RxD input must return to high for two (2) clock edges of the
RxC1x clock for the receiver to recognize the end of the break
condition. At the end of the break condition the search for the next
start bit begins.
Two edges of the RxC1x clock will usually require a high time of one
RxC1x clock period or 3 RxC1x edges since the clock of the
controller is usually not synchronous to nor in phase with the RxC1x
clock.
Receiver Status Bits

There are five (5) status bits that are evaluated with each byte (or
character) received: received break, framing error, parity error,
overrun error, and change of break. The first three are appended to
each byte and stored in the RxFIFO. The last two are not
necessarily related to the byte being received or a byte that is in the
RxFIFO. They are however developed by the receiver state
machine.
The receiver status bits are normally cleared by servicing the
interrupt condition they represent or by Rx reset or Rx disable
commands or the several error reset commands in the Command
Register (CR).
The ‘received break’ will always be associated with a zero byte in
the RxFIFO. It means that zero character was a break character and
not a zero data byte. The reception of a break condition will always
set the ‘change of break’ (see below) status bit in the Interrupt
Status Register (ISR).
The Change of break condition is reset by a reset error status
command in the command register
A framing error occurs when a non-zero character was seen and
that character has a zero in the stop bit position.
The parity error indicates that the receiver-generated parity was not
the same as that sent by the transmitter.
The framing, parity and received break status bits are reset when
the associated data byte is read from the RxFIFO since these ‘error’
conditions are attached to the byte that has the error
The overrun error occurs when the RxFIFO is full, the receiver shift
register is full, and another start bit is detected. At this moment the
receiver has 257 valid characters and the start bit of the 258th has
been seen. At this point the host has approximately 6/16 bit time to
read a byte from the RxFIFO or the overrun condition will be set.
The 258th character then overruns the 257th and the 258th the 259th
and so on until an open position in the RxFIFO is seen. (‘seen’
meaning at least one byte was read from the RxFIFO.)
Overrun is cleared by a use of the ‘error reset’ command in the
command register.
NOTE: Precaution must be taken when reading an overrun FIFO.

There will be 256th valid characters in the receiver FIFO. There will
be one character in the receiver shift register. However it will NOT
be known if more than one ‘over-running’ character has been
received since the overrun bit was set. The 257th character received
and read as valid but it will not be known how many characters were
lost between the two characters of the 256th and 257th reads of the
RxFIFO. In the 8-bit mode, the numbers 8 and 9 replace the
numbers 256 and 257 above.
The ‘Change of break’ means that either a break has been detected
or that the break condition has been cleared. This bit is available in
the ISR. The break change bit being set in the ISR and the received
break bit being set in the SR will signal the beginning of a break. At
the termination of the break condition only the change of break in
the ISR will be set. After the break condition is detected the
termination of the break will only be recognized when the RxD input
has returned to the high state for two successive edges of the 1x
clock; 1/2 to 1 bit time. (see above)
The receiver is disabled by reset or via CR commands. A disabled
receiver will not interrupt the host CPU under any circumstance in
the normal mode of operation. If the receiver is in the multi-drop or
special mode, it will be partially enabled and thus may cause an
interrupt. Refer to section on Wake-Up and the register description
for MR1 for more information.
Receiver FIFO

The receiver buffer memory is a 256 byte FIFO with three status bits
appended to each data byte. (The FIFO is then 256 11-bit ‘words’).
The receiver state machine gathers the bits from the receiver shift
register and the status bits from the receiver logic and writes the
assembled byte and status bits to the RxFIFO shortly after the stop
bit has been sampled. Logic associated with the FIFO encodes the
number of filled positions for presentation to the interrupt arbitration
system. The encoding is always the number of filled positions. Thus,
a full RxFIFO will bid with the value of 255 and the Status Register
RxFULL bit is set. When empty it will not bit at all. One position
occupied bids with the value 1. An empty FIFO will not bid since no
character is available.
Normally RxFIFO will present a bid to the arbitration system
whenever it has one or more filled positions. The bits of the RxFIFO
Interrupt Offset Level (RxFIL) or the bits of the MR2(3:2) allow the
user to modify this characteristic so that bidding will not start until
one of four levels (one or more filled, 64 filled, 192 filled, full) have
been reached. As will be shown later this feature may be used to
make slight improvements in the interrupt service efficiency. A
similar system exists in the transmitter.
RxFIFO Status Bits. Status reporting modes

This description applies to the upper three bits in the ‘Status
Register’. These three bits are not ‘in the status register’; they are
part of the RxFIFO. The three status bits at the output of the RxFIFO
are presented as the upper three bits of the status register included
in each UART.
The error status of a character, as reported by a read of the SR
(status register upper three bits) can be provided in two ways, as
programmed by the error mode control bit in the mode register:
‘Character mode’ or the ‘Block Mode’. The block mode may be
further modified (via a CR command) to set the status bits as the
characters enter the FIFO or as they are read from the FIFO.
In the ‘character’ mode, status is provided on a character by
Philips Semiconductors Product data sheet
SC28L202Dual UART
In the ‘block’ mode (on entry) the status provided in the SR for these
three bits is the logical OR of the status for all characters coming to
the input of the RxFIFO since the last reset error command was
issued. In this mode each of the status bits stored in the RxFIFO are
passed through a latch as they are sequentially written to the
receiver FIFO. If any of the characters has an error bit set that latch
will set and remain set until it is reset with a ‘receiver reset’ issued
from the command register or a chip reset is issued. The purpose of
this mode is indicating an error in the data block as opposed to an
error in a character. This mode improves receiver service efficiency.
In modern systems with low error rates, it is more efficient to ask for
retransmit of a block error data than to analyze it on a byte by byte
system.
The above paragraph describes the block mode activity as the data
is entered to the RxFIFO. Normally the status would be read only
once—at the beginning of the service to the receiver interrupt. If an
error is not set then the entire amount of data in the RxFIFO would
be read without any more reading if the receiver status. This
effectively doubles the efficiency of reading the receiver RxFIFO.
The use of the block mode on Exit passes the data and error
conditions as the RxFIFO is read. Here the final read of the status
register would be after the last byte was read from the RxFIFO. This
delays the knowledge of an error condition until after the data has
been read.
The latch used in the block mode to indicate ‘problem data’ is
usually set as the characters are read out of the RxFIFO. Via a
command in the CR the latch may be configured to set as error
characters are loaded to the RxFIFO. This gives the advantage of
indicating ‘problem data’ up to 256 (or the FIFO size) characters
earlier.
In either mode, reading the SR does not affect the RxFIFO. The
RxFIFO address is advanced only when the RxFIFO is read.
Therefore, the SR should be read prior to reading the corresponding
data character.
If the RxFIFO is full when a new character is received, the character
is held in the receiver shift register until a position is available in the
RxFIFO. At this time there are 257 valid characters in the RxFIFO. If
an additional character is received while this state exists, the
contents of the RxFIFO are not affected: the character previously in
the shift register is lost and the overrun error status bit, SR [4], will
be set upon receipt of the start bit of the new (overrunning)
character.
Wake Up Mode (Also the ‘9-bit’, ‘multi-drop’, ‘party; line’ or Special

mode)
The SC28L202 provides four modes of this common asynchronous
‘party line’ protocol where the parity bit is used to indicate that a byte
is address data or information data. Three automatic modes and the
default Host operated mode are provided. The automatic mode has
several sub modes (see below). In the full automatic the internal
state machine devoted to this function will handle all operations
associated with address recognition, data handling, receiver enables
and disables. In both modes the meaning of the parity bit is
changed. It is often referred to as the A/D bit or the address/data
bit—sometimes the ‘9th’ bit. It is used to indicate whether the byte
presently in the receiver shift register is an ‘address’ byte or a ‘data’
byte. A ‘1’ usually means address, a ‘0’ data.
Its purpose is to allow several receivers connected to the same data
enable itself to receive the following data stream. Upon receipt of an
address not its own it would then disable itself. As descried below
appropriate status bits are available to describe the operation.
Again, for this mode an ‘address byte’ is a byte that has the bit in the
parity position set to logical 1.
The use of the multi-drop mode usually implies a ‘master and slave’
configuration of the several UART stations so programmed. The
software control should allow time for the slave stations to respond
to the receipt of an address bit. Often a reply from the addressed
station is expected to confirm the receipt of the address. Please see
control the automatic features of the address recognition in
MR3[1:0].
Enabling the Wake Up mode

(This mode is variously referred to as ‘9-bit’ or ‘Multi-drop’.)
This mode is selected by programming bits MR1 [4:3] (the parity
bits) to ’11’. The wake up feature has four modes of operation: one
strictly under processor control and three automatic. These modes
are controlled by bits 6, 1, 0 in the MR3 register. Bit 6 controls the
loading of the address byte to the RxFIFO and MR3[1:0] determines
the sub mode as shown in the following list.
MR3[1:0] = 00 Normal Wake Up Mode (default) which is the same
as previous DUARTs and is therefore controlled by the processor.
The Host controls operation via interrupts it receives and commands
it writes to the DUART command registers (CR).
Normal Wake up (The default configuration)

The enabling of the wake-up mode executes a partial enabling of the
receiver state machine. Even though the receiver has been reset the
wake up mode will over ride the disable and reset condition.
In the default (mode ‘00’ above and the least efficient) configuration
for this mode of operation, a ’master’ station transmits an address
character followed by data characters for the addressed ’slave’
station. The slave stations, whose receivers are normally disabled
(not reset), examine the received data stream. Upon recognition of
its address bit (this is the parity bit redefined to indicate the
associated byte is an address bye – not the address itself)

interrupts the CPU (by setting RxRDY). The CPU (host) compares
the received address to its station address and enables the receiver
if it wishes to receive the subsequent data characters. Upon receipt
of another address character, the CPU may disable the receiver to
initiate the process again.
A transmitted character consists of a start bit; the programmed
number of data bits, an address/data (A/D) bit and the programmed
number of stop bits. The CPU selects the polarity of the transmitted
A/D bit by programming bit MR1 [2]. MR1 [2] = 0 transmits a zero in
the A/D bit position which identifies the corresponding data bits as
data. MR1 [2] = 1 transmits a one in the A/D bit position which

identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bytes into the TxFIFO.
While in this mode, the receiver continuously looks at the received
data stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RxFIFO if the
received A/D bit is a one, but discards the received character if the
received A/D bit is a zero. If the receiver is enabled, all received
characters are transferred to the CPU via the RxFIFO. In either case
when the address character is recognized the data bits are loaded
into the data FIFO while the A/D bit is loaded into the status FIFO
position normally used for parity error (SR [5]). Framing error,
Philips Semiconductors Product data sheet
SC28L202Dual UART
The several automatic controls. These modes are concerned with
the recognition of the address character itself MR3 [1:0] = 01 Auto wake. Enable receiver on address
recognition for this station. Upon recognition of its assigned
address the local receiver will be enabled by the character
recognition state machine and normal receiver communications
with the host will be established. MR3 [1:0] = 10 Auto Doze. Disable receiver on address
recognition, not for this station. Upon recognition of an address
character that is not its own, in the Auto Doze mode, the receiver
will be disabled by the character recognition state machine and
the address just received either discarded or loaded to the
RxFIFO depending on the programming of MR0 [6]. MR3 [1:0] = 11 Auto wake and doze. Both modes described
above. The programming of MR3 [1:0] to 11 will enable both the
auto wake and auto doze features.
The enabling of the wake-up mode executes a partial enabling of the
receiver state machine. Even though the receiver has been reset the
wake up mode will over ride the disable and reset conditions.
Receiver Reset and Disable

Receiver disable stops the receiver immediately – data being
assembled in the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected.
Receiver reset will discard the present shift register data, reset the
receiver ready bit (RxRDY), clear the status of the byte at the top of
the FIFO and re-align the FIFO read/write pointers. This effectively
‘clears’ the receiver FIFO although the FIFO data is not altered.
Receiver Watchdog Timer

A ‘watchdog timer’ is associated with each receiver. Its interrupt is
enabled by the ‘watchdog’ bits of the ‘Watch Dog, Character
Address, and X enable’ register (WCXER). The purpose of this timer
is to alert the control processor that characters are in the RxFIFO
which have not been read and/or the data stream has stopped. This
situation may occur at the end of a transmission when the last few
characters received are not sufficient to cause an interrupt. This
counter times out after 64 bit times. It is reset each time a read of
the RxFIFO is executed.
Receiver Time-out Mode

In addition to the watch dog timer described in the receiver section,
the counter/timer may be used for a similar function. Its
programmability, of course, allows much greater precision of timeout
intervals.
The time-out mode uses the received data stream to control the
counter. Each time a received character is transferred from the shift
register to the RxFIFO, the counter is restarted. If a new character is
not received before the counter reaches zero count, the counter
ready bit is set, and an interrupt can be generated. This mode can
be used to indicate when data has been left in the RxFIFO for more
than the programmed time limit. Otherwise, if the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU may not know
there is data left in the FIFO. The CTPU and CTPL value would be
programmed for just over one character time, so that the CPU would
be interrupted as soon as it has stopped receiving continuous data.
This mode can also be used to indicate when the serial line has
been marking for longer than the programmed time limit. In this
case, the CPU has read all of the characters from the FIFO, but the
last character received has started the count. If there is no new data
during the programmed time interval, the counter ready bit will get
set, and an interrupt can be generated.
Writing the appropriate command to the command register enables
the time-out mode. Writing an ‘Ax’ to CR A or CR B will invoke the
time-out mode for that channel. Writing a 0xCx to CR A or CR B will
disable the time-out mode. CTPU and CTPL should be loaded with a
count-down value that, with the selected clock, will generate a time
period greater than the normal receive character period. The
time-out mode disables the regular START/STOP Counter
commands and puts the C/T into counter mode under the control of
the received data stream. Each time a received character is
transferred from the shift register to the RxFIFO, the C/T is stopped
after 1 C/T clock, reloaded with the value in CTPU and CTPL and
then restarted on the next C/T clock. If the C/T is allowed to end the
count before a new character has been received, the counter ready
bit, ISR [3], will be set. If IMR [3] is set, interrupt arbitration for the
C/T will begin. Invoking the ‘Set Time-out Mode On’ command, CRx
= ‘Ax’, clears the counter ready bit and stop the counter until the
next character is received.
Exiting the time mode will clear the counter ready bit.
Arbitrating Interrupt Structure

(NOTE: The advantages and intelligence of this system may be
completely defeated by merely setting the arbitration value in the
ICR to 0x00 and not using the CIR. One would then rely on
traditional interrupt service by searching and testing various status
registers on the assertion of the IRQN.)
The interrupt system determines when an interrupt should be
asserted thorough an arbitration (or bidding) system. This arbitration
is exercised over the several systems within the DUART that may
generate an interrupt. These will be referred to as ‘interrupt sources’.
There are 18 in all and may of those have several sub-levels. In
general the arbitration is based on the fill level of the receiver FIFO
or the empty level of the transmitter FIFO. The FIFO levels are
encoded into an 8-bit number, which is concatenated to the channel
number and source identification code. All of this is compared (via
the bidding or arbitration process) to a user defined ‘threshold’.
Whenever a source exceeds the numerical value of the threshold
the interrupt will be generated.
Interrupt sources that do not have a FIFO are each provided with a
‘programmable field’ that will determine their importance in the
arbitration and type identification process. (See Table 1 below)
At the time of interrupt acknowledge (IACKN) the source which has
the highest bid (not necessarily the source that caused the interrupt
to be generated) will be captured in a ‘Current Interrupt Register’
(CIR). This register will contain the complete definition of the
interrupting source: channel, types of interrupt (receiver, transmitter,
change of state, etc.) and FIFO fill level. The value of the bits in the
CIR are used to drive the interrupt vector and global registers such
that controlling processor may be steered directly to the proper
service routine. A single read operation to the CIR provides all the
information needed to qualify and quantify the most common
interrupt sources.
Philips Semiconductors Product data sheet
SC28L202Dual UART
The interrupt sources for each channel are listed below. Receiver without error Receiver with error for each channel Receiver Watch Dog Time-out Event Transmitter Change in break received status per channel Rx loop back error Change of state on channel input pins Xon/Xoff character recognition Counter-Timer Address character recognition No interrupt active (very useful in polled service and as a test
value to terminate interrupt service)
Transmit FIFO empty level and Receiver FIFO fill levels are unique
for each channel and may be set at any level.
Associated with the interrupt system are the interrupt mask register
(IMR) and the interrupt status register (ISR) resident in each UART.
Programming of the IMR selects which of the above sources may
enter the arbitration process. The IMR enables the interrupt. Only
the bidders in the ISR whose associated bit in the IMR is set to one
(1) will be permitted to enter the arbitration process. The ISR can be
read by the host CPU to determine all currently active interrupting
conditions. For convenience of reading the ISR the MR1 (6) bit,
when set, allows the reading of the ISR masked by the bits of the
IMR.
Enabling and Activating Interrupt sources

An interrupt source becomes enabled when writing a one to the
proper Interrupt Mask Register bit (IMR) activates its interrupt
capability. An interrupt source can never generate an IRQN or have
its ‘bid’ or interrupt number appear in the CIR unless the source has
been enabled by the appropriate bit in an IMR.
An interrupt source is active if it is presenting its bid to the interrupt
arbiter for evaluation. Most sources have simple activation
requirements. The watch-dog timer, break received, Xon/Xoff or
Address Recognition and change of state interrupts become active
when the associated events occur and the arbitration value
generated thereby exceeds the threshold value programmed in the
ICR (Interrupt Control Register).
The transmitter and receiver functions have additional controls to
modify the condition upon which the initiation of interrupt ‘bidding’
begins: the TxINT and RxINT fields of the MR0 and MR2 registers.
These fields can be used to start bidding or arbitration when the
RxFIFO is not empty, 50% full, 75% full or 100% full. For the
transmitter it is not full, 50% empty, 75% empty and empty.
Example: To increase the probability of transferring the contents of a
nearly full RxFIFO, do not allow it to start bidding until 50% or 75%
full. This will prevent its relatively high priority from winning the
arbitration process at low fill levels. A high threshold level could
accomplish the same thing, but may also mask out low priority
interrupt sources that must be serviced. Note that for fast channels
and/or long interrupt latency times using this feature should be used
with caution since it reduces the time the host CPU has to respond
to the interrupt request before receiver overrun occurs.
Setting interrupt priorities

The bid or interrupt number presented to the interrupt arbiter is
composed of character counts, channel codes, fixed and
programmable bit fields. The interrupt values are generated for
various interrupt sources as shown in Table 1. The value
represented by the bits 11 to 4 in Table 1 are compared against the
value represented by the ‘Threshold. The ‘Threshold’, bits 10 to 0 of
the ICR (Interrupt Control Register), is aligned such that bit 0 of the
threshold is compared to bit 1 of the interrupt value generated by
any of the sources. Whenever the value of the interrupt source is
greater than the threshold the interrupt will be generated.
The channel number arbitrates only against other channels. The
threshold is not used for the channel arbitration. This results in
channel B having the highest arbitration number. The decreasing
order is B to A. If all other parts of an arbitration cycle are equal then
the channel number will determine which channel will dominate in
the arbitration process.
Note several characteristics of Table 1 in bits 4:1. These bits contain
the identification of the bidding source as indicated below: x001 Receiver without error x101 Receiver with error (errors are: parity, framing and overrun.
Break is not considered an error. x100 Receiver Watch Dog x010 Transmitter 1110 Change of Break 1111 Rx Loop Back Error 0110 Change of State on I/O Ports 0111 Xon/Xoff Event 1000 Counter timer 1011 Address Recognition 0000 No interrupt source active
The codes form bits 4:1 drive part of the interrupt vector modification
and the Global Interrupt Type Register. The codes are unique to
each source type and identify them completely. The channel
numbering progresses from ‘A’ to ‘B’ as the binary numbers 0 to 1
and identify the interrupting channel uniquely. As the channels
arbitrate ‘B’ will have the highest bidding value and ‘A’ the lowest.
Philips Semiconductors Product data sheet
SC28L202Dual UART
Table 1. Interrupt Values
Interrupt Arbitration and IRQN generation

Interrupt arbitration is the process used to determine that an
interrupt request should be presented to the host. The arbitration is
carried out between the ‘Interrupt Threshold’ and the ‘sources’
whose interrupt bidding is enabled by the IMR. The interrupt
threshold is part of the ICR (Interrupt Control Register) and is a
value programmed by the user. The ‘sources’ present a value to the
interrupt arbiter. That value is derived from four fields: the channel
number, type of interrupts source, FIFO fill level, and a
programmable value. The interrupt request (IRQN) will be asserted
only when one or more of these values exceeds the threshold value
in the interrupt control register will.
Following assertion of the IRQN the host will either assert IACKN
(Interrupt Acknowledge) or will use the command to ‘Update the
CIR’. At the time either action is taken the CIR will capture the value
of the source that is prevailing in the arbitration process. (Call this
value the winning bid).
The Sclk drives the arbitration process. It evaluates the 12 bits of
the arbitration bus at � the Sclk rate developing a value for the CIR
every two Sclk cycles. New arbitration values presented to the
arbitration block during an arbitration cycle will be evaluated in the
next arbitration cycle.
For sources other than receiver and transmitters the user may set
the high order bits of an interrupt source’s bid value, thus tailoring
the relative priority of the interrupt sources. The fill level of their
respective FIFOs controls the priority of the receivers and
transmitters. The more filled spaces in the RxFIFO the higher the bid
value; the more empty spaces in the TxFIFO the higher its priority.
Channels whose programmable high order bits are set will be given
interrupt priority higher than those with zeros in their high order bits,
thus allowing increased flexibility. The transmitter and receiver bid
values contain the character counts of the associated FIFOs as high
order bits in the bid value. Thus, as a receiver’s RxFIFO fills, it bids
with a progressively higher priority for interrupt service. Similarly, as
empty space in a transmitter’s TxFIFO increases, its interrupt
arbitration priority increases.
The programmable fields allow the software to adjust the authority or
value of the bid for those devices not having a FIFO.
weather report or stock market ‘ticker-tape’ report needs breaks in
the data so that a receiver knows where the data starts. Once start
of the break is detected it is important to reset the ‘change of break’
interrupt so that this bit can signal the condition of the break ending.
This is signaled by the ‘L202 the setting another change of break
event in the ISR. Since it is assumed the data will be starting very
soon after the end of break it is important to give the change of
break condition a high priority. This may be accomplished by setting
the arbitration value for the ‘change of break’ to a high value. The
value in the ‘change of break programmable field’ in Table 1 would
be 0x7F.
IACKN Cycle, Update CIR

When the host CPU responds to the interrupt, it will usually assert
the IACKN signal low. This will cause the DUART to generate an
IACKN cycle in which the condition of the interrupting device is
determined. When IACKN asserts, the last valid interrupt number is
captured in the CIR. The value captured presents most of the
important details of the highest priority interrupt at the moment the
IACKN (or the ‘Update CIR’ command) was asserted.
The Dual UART will respond to the IACKN cycle with an interrupt
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or when ‘Interrupt Vector Modification’ is
enabled via ICR, it may contain codes for the interrupt type and/or
interrupting channel. This allows the interrupt vector to steer the
interrupt service directly to the proper service routine. The interrupt
value captured in the CIR remains until another IACKN cycle occurs
or until an ‘Update CIR’ command is given to the DUART. The
interrupting channel and interrupt type fields of the CIR set the
current ‘interrupt context’ of the DUART. The channel component of
the interrupt context allows the use of Global Interrupt Information
registers that appear at fixed positions in the register address map.
For example, a read of the Global RxFIFO will read the channel B
RxFIFO if the CIR interrupt context is channel B receiver. At another
time read of the GRxFIFO may read the channel A RxFIFO (CIR
holds a channel A receiver interrupt) and so on. Global registers
exist to facilitate qualifying the interrupt parameters and for writing to
and reading from FIFOs without explicitly addressing them.
The CIR will load with x’00 if IACKN or Update CIR is asserted when
the arbitration circuit is NOT asserting an interrupt. In this condition
Philips Semiconductors Product data sheet
SC28L202Dual UART
Global Registers

The ‘Global Registers’, 10 in all, are driven by the interrupt system.
They are defined by the content of the CIR (Current Interrupt
Register) as a result of an interrupt arbitration. In other words they
are indirect registers pointed to by the content of the CIR. The list of
global register follows: GIBCR The byte count of the interrupting FIFO GICR Channel number of the interrupting channel GITR Type identification of interrupting channel GRxFIFO Pointer to the interrupting receiver FIFO GTxFIFO Pointer to the interrupting transmitter FIFO
A read of the GRxFIFO will give the content of the RxFIFO that
presently has the highest bid value. The purpose of this system is to
enhance the efficiency of the interrupt system. The global registers
and the CIR update procedure are further described in the Interrupt
Arbitration system
Polling, (Normal and using the CIR)

The ‘arbitrating interrupt system’ will reduce the polling overhead to
only two bus cycles. It only requires an update CIR command and a
CIR read to find if service is needed, and if needed to show what
needs to be serviced.
Many users prefer polled to interrupt driven service where there are
not a large number of fast data channels and/or the host CPU’s
other interrupt overhead is low. The Dual UART is functional in this
environment.
The most efficient method of polling is the use of the ‘update CIR’
command (with the interrupt threshold set to zero) followed by a
read of the CIR. This dummy write cycle will perform the same CIR
capture function that an IACKN falling edge would accomplish in an
interrupt driven system. A subsequent read of the CIR, at the same
address, will give information about an interrupt, if any. If the CIR
type field contains 0s, no interrupt is awaiting service. If the value is
non-zero, the fields of the CIR may be decoded for type; channel
and character count information. Optionally, the global interrupt
registers may be read for particular information about the interrupt
status or use of the global RxD and TxD registers for data transfer
as appropriate. The interrupt context will remain in the CIR until
another update CIR command or an IACKN cycle is initiated by the
host CPU occurs. The CIR loads with x’00 if Update CIR is asserted
when the arbitration circuit has NOT detected an arbitration value
that exceeds the threshold value of the ICR. The global registers
and CIR may be used as ‘vectors’ to the service type required.
Traditional methods of polling status registers may also be used.
Their lower efficiency may be greatly offset by use of the UCIR
command and the read of the CIR. They reduce the many reads and
tests of status registers to only one read and one write. This would
normally be accomplished by setting the interrupt threshold to zero.
Then the moment any system within the DUART needs service the
next poll of the CIR would return a non zero value and the type field
will inform the processor which of the possible 18 systems needs
service. In the case of the FIFOs the number of bytes to be written
or read is also available.
Character and Address Recognition
(Also used for Multi-drop, Xon/Xoff systems)

Character recognition is specific to each of the two UARTs. Three
operations specific to ‘Multi-drop’ address recognition or in-band
Xon/Xoff flow control.
Character recognition system continually examines the incoming
data stream. Upon the recognition of a character bits appropriate for
the character recognized are set in the Xon/Xoff Interrupt Status
Register (XISR) and in the Interrupt Status Register (ISR). The
setting of these bit(s) will initiate any of the automatic sequences or
and/or an interrupt that may have enabled via the MR3 register.
NOTE: Reading the XISR Clears the status bits associated with the
recognition.
The characters of the recognition system are fully programmable.
The Xon/Xoff characters will be set to the standard characters if the
hardware or software reset is used.
The character recognition circuits are basically designed to provide
general-purpose character recognition. Additional control logic has
been added to allow for Xon/Xoff flow control and for recognition of
the address character in the multi-drop or ‘wake-up’ mode. This logic
also allows for the generation of interrupts in either the
general-purpose recognition mode or the specific conditions
mentioned above.
The generality of the above provides a modicum of compatibility to
BOP (Bit Oriented Protocol) where the generation and detection of
‘flags’ is required. Parts of usually synchronous BOP protocols
(HDLC in particular) are beginning to show up in asynchronous
formats.
Character Stripping

The MR0[7:6] register provides for stripping the characters used for
character recognition. Recall that the character recognition may be
conditioned to control several aspects of the communication.
However this system is first a character recognition system. The
status of the various states of this system is reported in the XISR
and ISR registers. The character stripping of this system allows for
the removal of the specified control characters from the data stream:
two for the Xon /Xoff and one for the wake up. Via control in the
MR0[7:6] register these characters may be discarded (stripped) from
the data stream when the recognition system ‘sees’ them or they
may be sent on the RxFIFO. Whether they are stripped or not the
recognition system will process them according to the action
requested; flow control, wake up, interrupt generation, etc. Care
should be exercised in programming the stripping option if noisy
environments are encountered. If a normal character were corrupted
to a Xoff character the transmitter would be stopped. If that
character were now stripped from the FIFO stack, then that stripping
action would make it difficult to determine the cause of transmitter
stopping.
When character stripping is invoked and a recognition character is
received that has an error bit set that character is sent to the
RxFIFO even though character stripping is active.
Flow Control (Xon/Xoff)

This section describes in-band flow control or Xon/Xoff signaling.
For the RTS/CTS hardware (out-of-band) control see MR1(7) and
MR2(4) descriptions.
The flow control is accomplished via the character recognition
system giving recognition information to the flow control processor.
Xon and Xoff are special characters used by a receiver to start and
stop the remote transmitter that is sending it data. As described
Philips Semiconductors Product data sheet
SC28L202Dual UART
The modes of control are described in MR3[3:2]
00 = Host mode
01 = Auto transmit
10 = Auto Receive
11 = Auto receive and transmit
Mode control

Xon/Xoff mode control is accomplished via the MR3[3:2]. Xon/Xoff processing disabled. The host will control Rx, Tx. Auto Tx control. Tx is stopped/started when Xoff/Xon is
received. Auto Rx control. Receiver commands Tx to send Xoff at
trigger level. Auto Rx and Tx control. Receiver commands Tx to send
Xoff as the receiver fills and commands the Tx to send
Xon when Rx FIFO fill level is lowered. This results in total
automatic control. No processor interrupt is required.
Note that MR3[7] controls the stripping of Xoff/Xon characters. Xon/Xoff characters are sent to the Rx FIFO Xon/Xoff characters are discarded.
The MR3[7] functions regardless of the setting of MR3[3:2]. This
allows for general purpose character recognition and processing.
(See ‘Character Stripping’.)
Xon Xoff Characters

The programming of these characters is usually done individually.
The standard Xon/Xoff characters are . Xon is 0x11, Xoff 0x13. Any
enabling of the Xon/Xoff functions will use the contents of the Xon
and Xoff character registers as the basis on which recognition is
predicated.
Host mode

When neither the auto-receiver or auto-transmitter modes are set,
the Xon/Xoff logic is operating in the host mode. In host mode, all
activity of the Xon/Xoff logic is initiated by commands to the CRx.
The Xoff command forces the transmitter to disable exactly as
though a Xoff character had been received by the RxFIFO. The
transmitter will remain disabled until the chip is reset or the CR (7:3)
= 10110 (Xoff resume) command is given. In particular, reception of
a Xon or disabling or re-enabling the transmitter will NOT cause
resumption of transmission. Redundant CRTXxx commands, i.e.
CRTXon, CRTXon, are harmless, although they waste time. A
CRTXon may be used to cancel a CRTXoff (and vice versa) but both
may be transmitted depending on the command timing with respect
to that of the transmitter state machine.
Auto-transmitter mode

When a channel receiver loads a Xoff character into the RxFIFO, the
channel transmitter will finish transmission of the current character
and then stop transmitting. A transmitter so idled can be restarted by
the receipt of a Xon character by the receiver or by a hardware or
software reset. The last option results in the loss of the
untransmitted contents of the TxFIFO. When operating in this mode
the Command Register commands for the transmitter are not
effective.
While idle data may be written to the TxFIFO and it continue to
present its fill level to the interrupt arbiter and maintains the integrity
of its status registers.
Use of ’00’ as a Xon/Xoff character is complicated by the Receiver
break operation which loads a ’00’ character on the RxFIFO. The
NOTE: To be recognized as a Xon or Xoff character, the receiver

must have room in the RxFIFO to accommodate the character. An
Xon/Xoff character that is received resulting in a receiver overrun
does not effect the transmitter nor is it loaded into the RxFIFO,
regardless of the state of the Xon/Xoff transparency bit, MR3[7].
Receiver Mode

Since the receiving FIFO resources in the Dual UART are limited,
some means of controlling a remote transmitter is desirable in order
to lessen the probability of receiver overrun. The Dual UART
provides two methods of controlling the data flow. There is a
hardware-assisted means of accomplishing control, the so-called
out-of-band flow control, and an in-band flow control method.
The out-of-band flow control is implemented through the
CTSN–RTSN signaling via the I/O ports. The operation of these
hardware handshake signals is described in the receiver and
transmitter discussions.
In-band flow control is a protocol for controlling a remote transmitter
by embedding special characters within the message stream, itself.
Two characters, Xon and Xoff, which do not represent normal
printable character take on flow control definitions when the
Xon/Xoff capability is enabled. Flow control characters received may
be used to gate the channel transmitter on and off. This activity is
referred to as Auto-transmitter mode. To protect the channel receiver
from overrun, fixed fill levels (hardware set at 240 characters) of the
RxFIFO may be employed to automatically insert Xon/Xoff
characters in the transmitter’s data stream. This mode of operation
is referred to as auto-receiver mode. Commands issued by the host
CPU via the CR can simulate all these conditions.
Auto Receive and Transmit

This is a combination of both modes.
NOTE: Xon /Xoff characters

The Xon/Xoff character with errors will be accepted as valid. The
user has the option sending or not sending these characters to the
FIFO. Error bits associated with Xon/Xoff will be stored normally to
the receiver FIFO.
The channel’s transmitter may be programmed to automatically
transmit a Xoff character without host CPU intervention when the
RxFIFO fill level exceeds a fixed limit (240). In this mode it will
transmit a Xon character when the RxFIFO level drops below a
second fixed limit (16). A character from the TxFIFO that has been
loaded into the TxD shift register will continue to transmit.
Character(s) in the TxFIFO that have not been loaded to the
transmitter shift register are unaffected by the Xon or Xoff
transmission. They will be transmitted after the Xon/Xoff activity
concludes.
If the fill level condition that initiates Xon activity negates before the
flow control character can begin transmission, the transmission of
the flow control character will not occur. That is, either of the
following sequences may be transmitted depending on the timing of
the FIFO level changes with respect to the normal character times:
Fix This
Character Xoff Xon Character
Character Character
Hardware keeps track of Xoff characters sent that are not rescinded
Philips Semiconductors Product data sheet
SC28L202Dual UART
last character sent the Xon/Xoff logic would not automatically send
the negating Xon.
The kill CRTX command (of the command register) can be used to
cleanly terminate any pending CRTX commands.
NOTE: In no case will a Xon/Xoff character transmission be aborted.

Once the character is loaded into the TX Shift Register, transmission
continues until completion or a chip reset or transmitter reset is
encountered. The kill CRTX command has no effect in either of the
Auto modes.
Xon/Xoff Interrupts

The Xon/Xoff logic generates interrupts only in response to
recognizing either of the characters in the XonCR or XoffCR (Xon or
Xoff Character Registers). The transmitter activity initiated by the
Xon/Xoff logic or any CR command does not generate an interrupt.
The character comparators operate regardless of the value in
MR3[3:2]. Hence the comparators may be used as general-purpose
character detectors by setting MR3[3:2]= ‘00’ and enabling the
Xon/Xoff interrupt in the IMR.
The Dual UART can present the Xon/Xoff recognition event to the
interrupt arbiter for IRQN generation. The IRQN generation may be
masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid
level of a Xon/Xoff recognition event is controlled by the Bidding
Control Register X, BCRx, of the channel. The interrupt status can
be examined in ISR[4]. If cleared, no Xon/Xoff recognition event is
interrupting. If set, a Xon or Xoff recognition event has been
detected. The X Interrupt Status Register, XISR, can be read for
details of the interrupt and to examine other, non-interrupting, status
of the Xon/Xoff logic. Refer to the XISR in the Register Descriptions.
The character recognition function and the associated interrupt
generation is disabled on hardware or software reset.
Multi-drop or Wake up or 9 bit mode

This mode is used to address a particular UART among a group
connected to the same serial data source. Normally it is
accomplished by redefining the meaning of the parity bit such that it
indicates a character as address or data. While this method is fully
supported in the SC28L202 it also supports recognition of the
character itself. Upon recognition of its address the receiver will be
enabled and data loaded onto the RxFIFO.
Further the Address recognition has the ability, if so programmed, to
disable (not reset) the receiver when an address is seen that is not
recognized as its own. The particular features of ‘Auto Wake and
Auto Doze’ are described in the detail descriptions under ‘Receiver
Operation’ above.
NOTE: Care should be taken in the programming of the character

recognition registers. Programming x’00, for example, may result in
a break condition being recognized as a control character. This will
be further complicated when binary data is being processed.
PROGRAMMING THE HOST INTERFACE

The SC28L202 is designed for a very close compatibility with legacy
software written for other Philips/Signetics 2 channel UARTs. The
part will initialize to the SC28L92 function. This function is controlled
in the low 16 address positions.
A reset (both hardware and software) will return the part to this
mode with the control registers set for 9600 baud, 8 bits, no parity
and one stop bit. Interrupt will be set for Receiver Ready and
transmitter Empty. Transmitters and receivers will not be enabled.
Basic operation should be obtained by a single write of 0xE0 to the
command register. That will enable the receiver and transmitter.
Addressing outside of the lower 16 address spaces will enable all
the advanced features. In general, before calling legacy code,
advanced features should be disabled (character stripping, for
example).
Writing control words into the appropriate registers programs the
operation of the DUART. Operational feedback is provided via status
registers that can be read by the CPU. The addressing of the
registers is described in the Register Map.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Each channel has 3 mode registers (MR0, 1, 2) which control the
basic configuration of the channel. Mode, command, clock select,
and status registers are duplicated for each channel to provide total
independent operation and control. Refer to Table 2 for register bit
descriptions.
Philips Semiconductors Product data sheet
SC28L202Dual UART
REGISTER DESCRIPTION AND PROGRAMMING
NOTE

Programmers may use either of two register sets or mix the features
of each. It is suggested that only the extended register set be used
in new designs. However if a system needed to use a block of
communications code written for an older system then that code
could merely be called. This is similar to calling a DOS program in
a WINDOWS environment. Before calling legacy code it is
recommended (but not required) to execute ‘Reset to C92’
command. Also consideration must be given to the I/O pins to avoid
contention of drivers of the pins and an external driver.
Two control register descriptions and maps are implemented in the
SC28L92: one represents the previous 4-bit address and the other
the new 7-bit address space representing the all the new features of
the new design.
The Design of the SC28L202 allows for high degree with former
Philips two channel communications controllers—DUARTs.
To facilitate this feature the complete register function and control of
the SC26C92 is replicated in the SC28L202. That is code written for
the SCN2681, SCN68681, SCC2692, SCC68692 and SC26C92 will
operate with this device.
With the execution of code written for previous DUARTs and
immediately after a hardware reset or a ‘Reset to C92’ command the
following configuration will exist: The size of all FIFOs is set to 8 bytes (for legacy code). FIFO interrupt levels are controlled by the bits of the MR
registers All I/O ports are set to input. Receiver FIFO set to interrupt on FIFO ready. Transmitter FIFO set to interrupt on FIFO empty. Baud selection follows previous 4 bit programming and baud rate
grouping controlled by the MR and ACR registers.
Table 2. SC28L202 REGISTER BIT DESCRIPTIONS
Registers that control Global Properties of the 28L202
GCCR – Global Configuration Control Register

THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION.
GCCR(7:6) DACKN Assertion

Motorola bus cycle time can be controlled by selecting a DACKN
assertion time based on X1/Sclk speed. The time programmed
should not be less than the minimum read or write pulse width.
See examples below.
GCCR(5:3): Reserved
GCCR(2:1): Interrupt vector configuration

The IVC field controls if and how the assertion of IACKN (the
interrupt acknowledge pin) will form the interrupt vector for the
DUART. If b’00, no vector will be presented during an IACKN cycle.
The bus will be driven high (0xFF). If the field contains a b’01, the
contents of the IVR, Interrupt Vector Register, will be presented as
the interrupt vector without modification.
If IVC = 0x10, the channel code will replace the LSB of the IVR; if
IVC = b’11 then a modified interrupt type and channel code replace
the 3 LSBs of the IVR. NOTE: The modified type field IVR[2:1] is: 10 Receiver w/o error 11 Receiver with error 01 Transmitter 00 All remaining sources
GCCR(0): Interrupt Status Masking

This bit controls the readout mode of the Interrupt Status Register,
ISR. If set, the ISR reads the current status masked by the IMR, i.e.
only interrupt sources enabled in the IMR can ever show a ‘1’ in the
ISR. If cleared, the ISR shows the current status of the interrupt
source without regard to the Interrupt Mask setting.
Philips Semiconductors Product data sheet
SC28L202Dual UART
SFSR A and B Special Feature & Status Register
SFSR(7:4) Reserved
SFSR(3) Status of loop back error check.

A ‘1’ indicates a loop back error occurred, which will be entered for
interrupt arbitration.
It can be cleared by the processor by a write to this register with
D(3) equal to ‘1’.
SFSR(2:1) Certification of returned data as Valid (This feature

implies the transmitted data is being returned by the remote
receiver. )
Sets automatic checking of returned data. This mode stores
transmitted data and compares it to data returned from the remote
receiver. It is used where relative short delay times are available, up
to two characters in time . This mode will totally relieve the
processor of this task where certainty of transmission and reception
is required. The transmitted data is looped back by the remote
station with a half-bit time delay. The local transmitted data is
internally sent to the local receiver for comparison. An interrupt is
generated in the case of an error (data mismatch, parity or framing).
00 = The checking is disabled
01 = Return data is clocked in on rise of TxC
10 = Return data is clocked on of rise of TxCN
00 = Reserved
SFSR(0) Reserved
TRR Test and Revision Register.
TRR[7] Test 2 Enable

Bypass divide by 16 counter in all TxC and RxC.
TRR[6:0] – Chip Revision Code

Indicates the revision of the chip. Initial code will be 0000000. The
revision code bits [6:0] are hard wired. The default setting of the test
bits is all zero.
STCR – Scan Test Control Register.
STCR(0) Iddq Test – Turns off all pull-up devices on the I/O pins.
SES – System Enable Status Register, A and B

This register reports the enabled status of the several sub systems in the DUART. These systems are sometimes controlled by the state
machines of the receiver FIFOs.
EOS – Enhanced Operation Status Register

This register reports the status of the Enhanced operation in several sub systems in the DUART.
Philips Semiconductors Product data sheet
SC28L202Dual UART
UART Registers
These registers are generally concerned with formatting,
transmitting and receiving data.

The user must exercise caution when changing the mode of running
receivers, transmitters, PBRG or counter/timers. The selected mode
will be activated immediately upon selection, even if this occurs
during the reception or transmission of a character. It is also
possible to disrupt internal controllers by changing modes at critical
times, thus rendering later transmission or reception faulty or
impossible.
An exception to this policy is switching from auto-echo or remote
loop back modes to normal mode. If the deselecting occurs just after
the receiver has sampled the stop bit (in most cases indicated by
the assertion of the channel’s RxRDY bit) and the transmitter is
enabled, the transmitter will remain in auto-echo mode until the end
of the transmission of the stop bit.
MR0 – Mode Register 0, A and B

MR0 can be accessed directly at H’20’ and H’28’ in the Extended section of the address map, or by means of the ‘MR Pointers’ at the 0x00 and
0x08 address pointers used by legacy code.
*This bit control is duplicated at WCXER[7:6], the Watch Dog, Character, Address and X Enable Register.
MR0[7] Fixed length Watchdog Timer

This bit controls the receiver watchdog timer. 0 = disable, 1 =
enable. When enabled, the watch dog timer will generate a receiver
interrupt if the receiver FIFO has not been accessed within 64 bit
times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
MR0[6] – Bit 2 of receiver FIFO interrupt level. This bit along with Bit

6 of MR1 sets the fill level of the 8 byte FIFO that generates the
receiver interrupt.
MR0[6] and MR1[6] Note that this control is split between MR0 and

MR1. This is for backward compatibility to the SC2692 and
SCN2681.
Table 3. Receiver FIFO Interrupt Fill Level
MR0(3)=0
Table 4. Receiver FIFO Interrupt Fill Level
MR0(3)=1

For the receiver these bits control the number of FIFO positions
filled when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
MR0[5:4] – Tx interrupt fill level.
Table 5. Transmitter FIFO Interrupt Fill Level
MR0(3)=0
Table 6. Transmitter FIFO Interrupt Fill Level
MR0(3)=0

For the transmitter these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
transmit FIFO has 8 bytes empty. It will then attempt to interrupt as
soon as the transmitter is enabled. The default setting of the MR0
bits (00) condition the transmitter to attempt to interrupt only when it
is completely empty. As soon as one byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
MR0[3] – FIFO Size

Selects between 8 or 256 byte FIFO structure
MR0[2:0] – Legacy Baud Rate Group Selection

These bits are used to select one of the six-baud rate groups.
See Table 13 for the group organization. 000 Normal mode 001 Extended mode I 100 Extended mode II
Philips Semiconductors Product data sheet
SC28L202Dual UART
MR1 – Mode Register 1, A and B

MR1 can be accessed directly at H’21’ and H’29’ in the Extended section of the address map, or by means of the ‘MR Pointers’ at the 0x00 and
0x08 address pointers used by legacy code.
MR1[7] – Receiver Request to Send (hardware flow control)

This bit controls the deactivation of the RTSN output (I/O2) by the
receiver. The I/O2 output is asserted and negated by commands
applied via the command register or through the setting of the OPR
register bits. MR1[7] = 1 enables the receiver state machine to
controls the sate of the I/O2 (where the RTSN function is assigned)
to be automatically negated (driven high) upon receipt of a valid start
bit if the receiver FIFO is 240 full or greater. (for 8-byte mode the
FIFO full signal is used) RTSN is reasserted when the FIFO fill level
falls below 240 filled FIFO positions. This constitutes a change from
previous members of Philips (Signets)’ UART families where the
RTSN function triggered on FIFO full. This behavior caused
problems with PC UARTs that could not stop transmission at the
proper time.
NOTE: When the FIFO is set to an 8-byte depth the RTSN signaling

is triggered on position 8 of the FIFO
The RTSN feature can be used to prevent overrun in the receiver, by
using the RTSN output signal, to control the CTSN (see MR2(4)
description) input of the transmitting device. It is not recommend to
use the hardware flow control and the ‘in-band’ (Xon/Xoff) flow
control at the same time although the DUART hardware will allow it.
To use the RTSN function: Set MR1(7) to 1 Set I/O0 B or I/O1 B as appropriate to logical 0 Enable receiver
MR1[6] – Receiver interrupt control bit 1.

See description under MR0 [6]. (Writing to this register will reset the
RxFIFO interrupt to the bit configuration of MR0 and MR1. Reading
has no effect.)
*** change in MR in legacy section – at MR0 also***
MR1 [5] – Error Mode Select and sub modes

This bit selects the operating mode of the three FIFOed status bits
(FE, PE, and received break). In the character mode, status is
provided on a character by character basis; the status applies only
to the character at the output of the FIFO.
In the block mode, the status provided in the SR for these bits is the
accumulation (logical OR) of the status for all characters coming to
the output of the FIFO, since the last reset error command was
issued.
The Block Error mode has two-sub mode. These modes are
controlled by the command register. The error is ‘accumulated’ (as
described above) at either the entry of the data in to the FIFO or on
the exit (read of the FIFO). Of the two the setting of the error on the
entry of the data into the FIFO gives the earliest warning of error
data.
MR1[4:3] – Parity Mode Select

If ’with parity’ or ’force parity’ is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the channel to operate in the
special wake up mode.
MR1[2] – Parity Type Select

This bit sets the parity type (odd or even) if the ’with parity’ mode is
programmed by MR1[4:3], and the polarity of the forced parity bit if
the ’force parity’ mode is programmed it has no effect if the ’no
parity’ mode is programmed. In the special ’wake up’ mode, it
selects the polarity of the A/D bit. The parity bit is used to an
address or data byte in the ’wake up’ mode.
MR1[1:0] – Bits per Character Select

This field selects the number of data bits per character to be
transmitted and received. This number does not include the start,
parity, or stop bits.
Philips Semiconductors Product data sheet
SC28L202Dual UART
MR2 – Mode Register 2, A and B

MR2 can be accessed directly at 0x22 and 0x2A in the Extended section of the address map, or by means of the ‘MR Pointers’ at the 0x00 and
0x08 address pointers used by legacy code.
The MR2 register provides basic channel set-up control that may need more frequent updating.
NOTE:
Add 0.5 to values shown for 0 – 7 if channel is programmed for 5 bits/char.
MR2[7:6] – Mode Select

The DUART can operate in one of four modes: Normal, Automatic
Echo, Local Loop Back and Remote Loop Back
MR2[7:6] = b’00 Normal Mode

Normal and default mode The transmitter and receiver operating
independently.
MR2[7:6] = b’01 Automatic Echo

Places the channel in the automatic echo mode, which automatically
retransmits the received data. The following conditions are true
while in automatic echo mode: Received data is re-clocked and re-transmitted on the TxD output. The receiver clock is used for the transmitted data. The receiver must be enabled, but the transmitter need not be
enabled. The TxRDY and Tx Idle status bits are inactive. The received parity is checked, but is not regenerated for
transmission, i.e., transmitted parity bit is as received. Character framing is checked, but the stop bits are retransmitted
as received. Rx data is sent to RxFIFO A received break is echoed as received until the next valid start bit
is detected.• CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
MR2[7:6] = b’10 selects local loop back diagnostic mode. In this mode:
The transmitter output is internally connected to the receiver input. The transmitter’s 1X clock is used for the receiver. The TxD output is held high. The RxD input is ignored. The transmitter must be enabled, but the receiver need not be
enabled.• CPU to transmitter and receiver communications continue
normally.
MR2 [7:6] = b’11 Selects the Remote Loop back diagnostic mode.

In this mode: Received data is re-clocked and re-transmitted on the TxD output. The receiver 1X clock is used for the transmitted data. Received data is not sent to the local CPU, and the error status
conditions are inactive.• The received parity is not checked and is not regenerated for
transmission, i.e., the transmitted parity bit is as received. A received break is echoed as received until the next valid start bit
is detected.
MR2[5] Transmitter Request to Send Control

This bit controls the deactivation of the RTSN output (I/O2) by the
transmitter. This output is manually asserted and negated by
appropriate commands issued via the command register. MR2 [5] = 1
negates (drives to logical 1) RTSN automatically one bit time after
the characters in the transmit shift register and in the TxFIFO (if any)
are completely transmitted (includes the programmed number of
stop bits if the transmitter is not enabled). This feature can be used
to automatically terminate the transmission of a message as follows: Program auto reset mode: MR2[5]= 1. Enable transmitter. Assert RTSN via command. Send message. Verify the next to last character of the message is being sent by
waiting until transmitter ready is asserted. Disable transmitter after
the last character is loaded into the TxFIFO. The last character will be transmitted and RTSN will be reset one
bit time after the last stop bit.
NOTE: when the transmitter controls the RTSN pin the meaning of

the pin is COMPLETELY changed. It has nothing to do with the
normal RTSN/CTSN ‘handshaking’. It is usually used to mean, ‘end
of message’ and to ‘turn the line around’ in simplex communications.
From a practical point of view the simultaneous use of Tx control of
RTSN and Rx control is mutually exclusive. However if this is
programmed the DUART performs as required.
MR2[4] – Clear to Send Control

The state of this bit determines if the CTSN input (I/O0) controls the
operation of the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the state of CTSN
each time it is ready to begin sending a character. If it is asserted
(low), the character is transmitted. If it is negated (high), the TxD
output remains in the marking state and the transmission is delayed
until CTSN goes low. Changes in CTSN, while a character is being
transmitted, do not affect the transmission of that character. This
feature can be used to prevent overrun of a remote receiver.
MR2[3:0] – Stop Bit Length Select

This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 through 2 bits can be
programmed. In all cases, the receiver only checks for a mark
condition at the center of the first stop bit position (one bit time after
the last data bit, or after the parity bit if parity is enabled). If an
Philips Semiconductors Product data sheet
SC28L202Dual UART
MR3 – Mode Register 3, A and B
NOTE:
If these bits are not 0 the characters will be stripped regardless of bits (3:2) or (1:0)
MR3[7 & 6] Xon/Xoff Character Stripping

Control the handling of recognized Xon/Xoff or Address characters.
If set, the character codes are placed on the RxFIFO along with their
status bits just as ordinary characters are. If the character is not
loaded onto the RxFIFO, its received status will be lost unless the
receiver is operating in the block error mode, see MR1[5] and the
general discussion on receiver error handling. Interrupt processing
is not effected by the setting of these bits. See Character recognition
section.
MR3[5:4] Reserved
MR3[3:2] Xon/Xoff Processing

Control the Xon/Xoff processing logic. Auto Transmitter flow control
allows the gating of Transmitter activity by Xon/Xoff characters
received by the Channel’s receiver. Auto Receiver flow control
causes the Transmitter to emit an Xoff character when the RxFIFO
has loaded to a depth of 240 characters. Draining the RxFIFO to a
level of 128 or less causes the Transmitter to emit a Xon character.
All transmissions require no host involvement. A setting other than
b’00 in this field precludes the use of the command register to
transmit Xon/Xoff characters.
NOTE: Interrupt generation in Xon/Xoff processing is controlled by

the IMR (Interrupt Mask Register) of the individual channels. The
interrupt may be cleared by a read of the XISR, the Xon/Xoff
Interrupt Status Register. Receipt of a flow control character will
always generate an interrupt if the IMR is so programmed. The
MR0[3:2] bits have effect on the automatic aspects of flow control
only, not the interrupt generation.
MR3[1:0] Address Recognition

This field controls the operation of the Address recognition logic. If
the device is not operating in the special or ‘wake-up’ mode, this
hardware may be used as a general-purpose character detector by
choosing any combination except b’00. Interrupt generation is
controlled by the channel IMR. The interrupt may be cleared by a
read of the XISR, the Xon/Xoff Interrupt Status Register. See further
description in the section on the Wake Up mode.
Philips Semiconductors Product data sheet
SC28L202Dual UART
RxCSR – Receiver Clock Select Register A and B
TxCSR Transmitter Clock Select Register A and B

Both registers consist of single 6-bit field that selects the clock source for the receiver and transmitter respectively. During a read the unused
bits in this register read b’000. The ‘BRG’ baud rates (fixed BRG rates) shown in the table below are based on the Sclk crystal frequency of
14.7456 MHz. The baud rates shown below will vary as the Sclk crystal clock varies. For example, if the Sclk rate is changed to 7.3728 MHz all
the rates below will reduce by 1/2.
Rx and Tx Clock Select Table
NOTE: Sclk maximum rate is 50 MHz. Data clock rates will follow exactly the ratio of the X1/Sclk to 14.7654 MHz

This field selects the baud rate clock for the Channel A transmitter.
* External clock Pin and external clock mode assignment.
Philips Semiconductors Product data sheet
SC28L202Dual UART
CRx – Command Register Extension, A and B

CR is used to write commands to the DUART.
CR[7] – Lock Tx and Rx enables.

‘0’ prevents changing transmitter and receiver enable bits while
writing to the lower 5 bits of the command register. Bits CR[6:5] are
not changed.
‘1’ allows the receiver and transmitter enable bits to be changed
while issuing a command to the command register.
NOTE: Receiver or transmitter disable is not the same as receiver

or transmitter reset.
WRITES TO THE LOWER 5 BITS OF THE CR WOULD USUALLY
HAVE CR[7] AT ‘0’ in order to maintain the enable/disable condition

of the receiver and transmitter. The bit provides a mechanism for
writing commands to a channel, via CR[4:0], without the necessity of
keeping track of or reading the current enable status of the receiver
and transmitter.
CR[6] – Enable Transmitter

A one written to this bit enables operation of the transmitter. The
TxRDY status bit will be asserted. When disabled by writing a zero
to this bit, the command terminates transmitter operation and resets
the TxRDY and Tx Idle status bits returning the transmitter to its idle
state . However, if a character is being transmitted or if characters
are loaded in the TxFIFO when the transmitter is disabled, the
transmission of the all character(s) is completed before assuming
the inactive state.
CR[5] – Enable Receiver

A one written to this bit enables operation of the receiver. The
receiver immediately begins the search for and the verification the
start bit. If a zero is written, this command terminates operation of
the receiver immediately—a character being received will be lost.
The command has no effect on the receiver status bits or any other
control registers. The data in the RxFIFO will be retained and may
be read. If the receiver is re-enabled subsequent data will be
appended to that already in the RxFIFO. If the special wake-up
mode is programmed, the receiver operates even if it is disabled
(see Wake-up Mode).
CR[4:0] – Miscellaneous Commands (See Table below)

The encoded value of this field can be used to specify a single
command as follows: 00000 No command. 00001 Reserved 00010 Reset receiver. Immediately resets the receiver as if
hardware reset had been applied. The receiver is reset and the
FIFO pointer is reset to the first location effectively discarding all
unread characters in the FIFO. 00011 Reset transmitter. Immediately resets the transmitter as if a
hardware reset had been applied. The transmitter is reset and the
FIFO pointer is reset to the first location effectively discarding all
untransmitted characters in the FIFO. 00101 Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be cleared to
zero. 00110 Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will be
delayed up to two bit times. If the transmitter is active and the
TxFIFO is empty then the break begins when transmission of the
current character is completed. If there are characters in the
TxFIFO, the start of break is delayed until all characters presently
in the TxFIFO and any subsequent characters loaded have been
transmitted. (Tx Idle must be true before break begins).
The transmitter must be enabled to start a break. 00111 Stop break. The TxD line will go high (marking) within two
bit times. TxD will remain high for one bit time before the next
character is transmitted. 01000 Assert RTSN. Causes the RTSN output to be asserted
(low). 01001 Negate RTSN. Causes the RTSN output to be negated
(high).
NOTE: The two commands above actually reset and set,

respectively, the I/O0 B (Channel A) or I/O1 B (Channel B)
pin associated with the OPR register. (See SOPR and
ROPR registers I/O pin control.• 01010 Set C/T Receiver time out mode on 01011 Set MR Pointer to 0 01100 Set C/T Receiver time out mode off 01101 Block error status accumulation on FIFO entry. Allows the
‘received break’, ‘framing error’ and ‘parity error’ bits to be set as
the received character is loaded to the RxFIFO. (normally these
bits are set on reading of the data from the RxFIFO) Setting this
mode can give information about error data up to 256 bytes earlier
than the normal mode. However it clouds the ability to know
precisely which byte(s) are in error. 01110 Power Down Mode On 01111 Disable Power Down Mode 10000 Transmit an Xon Character 10001 Transmit an Xoff Character 10010 C/T start sets the counter timer to the value of the
counter/timer preset register and starts the counter. 10011 C/T stop Effectively stops the counter/timer, captures the
last count value and resets the counter ready status bit in the ISR 10100 Reserved 10101 Reserved. 10110 Transmitter resume command (This command is not active
Philips Semiconductors Product data sheet
SC28L202Dual UART 10111 Host Xoff (or transmitter pause) command (CRTXoff). This
command allows tight host CPU control of the flow control of the
channel transmitter. When interrupted for receipt of a Xoff
character by the receiver, the host may stop transmission of
further characters by the channel transmitter by issuing the Host
Xoff command. Any character that has been transferred to the
TxD shift register will complete its transmission, including the stop
bit before the transmitter pauses. Even though the transmitter is
paused it is still able to send Xon/Xoff by the request of its
associated receiver. 11000 Cancel Host transmit flow control command. Issuing this
command will cancel a previous command to transmit a flow
control character if the flow control character is not yet loaded into
the TxD Shift Register. If there is no character waiting for
transmission or if its transmission has already begun, then this
command has no effect and the character will be sent. 11001 Reserved 11010 Reserved 11011 Reset Address Recognition Status. This command clears
the interrupt status that was set when an address character was
recognized by a disabled receiver operating in the special mode. 11100 Reserved 11101 Block error status accumulates on FIFO read (Default
State) 11110 Reset to ‘C92’ Register Set 11111 Reserved for channel B, for channel A: executes a chip
wide reset. Executing this command in channel a is equivalent to
a hardware reset with the RESET(N) pin. Executing in channel B
has no effect.
COMMAND REGISTER EXTENSION TABLE A and B

Commands 0x0E, 0x0F, 0x1F (marked with • ) are global and exist only in channel A’s register space.
Philips Semiconductors Product data sheet
SC28L202Dual UART
SR – Channel Status Register A and B
SR[7] – Received Break

This bit indicates that an all zero character (including parity, if used)
of the programmed length has been received with a stop bit at a
logical zero. A single FIFO position is loaded with 0x00 when a
break is received; further entries to the FIFO are inhibited until the
RxD line returns to the marking state for at least one half bit time
(two successive edges of the internal or external 1x clock). When
this bit is set, the change in break bit in the ISR (ISR [2]) is set.
ISR[2] is also set when the end of the break condition, as defined
above, is detected. The break detect circuitry is capable of detecting
breaks that originate in the middle of a received character. However,
if a break begins in the middle of a character, it must last until the
end of the next character in order for it to be detected.
SR[6] – Framing Error (FE)

This bit indicates that a stop bit was not detected when an otherwise
non-zeros data character (including parity, if enabled) was received.
The stop bit check is made in the middle of the first stop bit position.
SR[5] – Parity Error (PE)

This bit is set when the ’with parity’ or ’force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity. In the special ’wake up mode’, the
parity error bit stores the received A/D bit.
SR[4] – Overrun Error (OE)

This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of the
start bit of a new character when the RxFIFO is full and a character
is already in the receive shift register (257 valid characters in the
receiver) waiting for an empty FIFO position. When this occurs, the
character in the receive shift register (and its break detect, parity
error and framing error status, if any) is lost. This bit is cleared by a
reset error status command.
SR [3] – Transmitter Idle (Tx Idle)

This bit is set when the transmitter underruns, i.e., both the TxFIFO
and the transmit shift register are empty. It is set after transmission
of the last stop bit of a character, if no character is in the TxFIFO
awaiting transmission. It is negated when the TxFIFO is loaded by
the CPU, or when the transmitter is disabled or reset. This bit is
concerned with the transmitter transmitting data and it essentially
shows ‘ transmitter underrun’. If, while it is underrun it is
commanded to send an X on/Xoff character it will remain at the zero
state. If it is underrun and while sending an Xon/Xoff character the
TxFIFO is loaded then the bit will go low.
SR[2] – Transmitter Ready (TxRDY)

This bit, when set, indicates that the TxFIFO is ready to be loaded
with at least one more character. This bit is cleared when the
TxFIFO is full or is above its interrupt threshold level set in the MR
registers or TxFIFO interrupt Fill Level register (TxFIL). Characters
loaded in the TxFIFO while the transmitter is disabled will not be
transmitted.
SR[1] – RxFIFO Full (RxFULL)

This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all 256 RxFIFO positions are occupied. It is reset
when the CPU reads the RxFIFO and that read leaves one or more
empty byte position(s). If a character is waiting in the receive shift
register because the RxFIFO is full, RxFULL is not reset until the
second read of the RxFIFO since the waiting character is
immediately loaded to the RxFIFO.
SR[0] – Receiver Ready (RxRDY)

This bit indicates that a character has been received and is waiting
in the RxFIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the RxFIFO and reset
when the CPU reads the RxFIFO, and no more characters are in the
RxFIFO.
Philips Semiconductors Product data sheet
SC28L202Dual UART
ISR – Interrupt Status Register A and B

This register provides the status of all potential interrupt sources for
a UART channel. When generating an interrupt arbitration value, the
contents of this register are masked by the interrupt mask register
(IMR). If a bit in the ISR is a ’1’ and the corresponding bit in the IMR
is also a ‘1’; interrupt arbitration for this source will begin. If the
corresponding bit in the IMR is a zero, the state of the bit in the ISR
can have no affect on the IRQN output. Note that the IMR may or
may not mask the reading of the ISR as determined by GCCR[06].
If GCCR[0] is cleared, the reset and power on default, the ISR is
read without modification. If GCCR[0] is set, the read of the ISR
gives a value of the ISR ANDed with the IMR.
ISR[7] – Input Change of State.

This bit is set when a change of state occurs at the I/O1 or I/O0
input pins. It is reset when the CPU reads the Input Port Register,
IPR.
ISR[6] Fixed Watchdog Time-out.

This bit is set when the receiver’s watchdog timer has counted more
than 64 bit times since the last RxFIFO event. RxFIFO events are a
read of the RxFIFO or GRxFIFO, or the load of a received character
into the FIFO. The interrupt will be cleared automatically when the
RxFIFO or GRxFIFO is read. The receiver watch-dog timer is
included to allow detection of the very last characters of a received
message that may be waiting in the RxFIFO, but are too few in
number to successfully initiate an interrupt. Refer to the watchdog
timer description for details of how the interrupt system works after a
watchdog time-out.
ISR[5] – Address Recognition Status Change.

This bit is set when a change in receiver state has occurred due to
an Address character being received from an external source and
matches the reference address in ARCR. The bit and interrupt is
negated by a write to the CR with command x11011, Reset Address
Recognition Status.
ISR[4] – Xon/Xoff Status Change.

This bit is set when a Xon/Xoff character being received from an
external source. The bit is negated by a read of the channel
Xon/Xoff Interrupt Status Register, XISR.
ISR[3] – Counter Timer Status

The C/T has timed out or the count passed through 0. This bit is
cleared by issuing the ‘stop C/T ’ command.
ISR[2] – Change in Channel Break Status.

This bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
issues a reset break change interrupt command via the CR.
ISR[1] – RxINT. (Also Rx DMA hand shake at I/O pins)

The general function of this bit is to indicate that the RxFIFO has
data available and that it has entered the arbitration process. The
particular meaning of this bit is programmed by RxFIL register. If
programmed as receiver ready (MR2[3:2] = 00), it indicates that at
least one character has been received and is waiting in the RxFIFO
to be read by the host CPU. It is set when the character is
transferred from the receive shift register to the RxFIFO and reset
when the CPU reads the last character from the RxFIFO.
If RxFIL is programmed as FIFO full, ISR[1] is set when a character
is transferred from the receive holding register to the RxFIFO and
the transfer causes the RxFIFO to become full, i.e. all 256 FIFO
positions are occupied. It is reset whenever RxFIFO is not full. If
there is a character waiting in the receive shift register because the
FIFO is full, the bit is set again when the waiting character is
transferred into the FIFO.
The other two conditions of these bits, 3/4 and half full operate in a
similar manner. The ISR[1] bit is set when the RxFIFO fill level
meets or exceeds the value; it is reset when the fill level is less. See
the description of the MR2 register.
NOTE: This bit must be at a one (1) for the receiver to enter the

arbitration process. It is the fact that this bit is zero (0) when the
RxFIFO is empty that stops an empty FIFO from entering the
interrupt arbitration. Also note that the meaning if this bit is not quite
the same as the similar bit in the status register (SR).
ISR[0] – TxINT. (Also Tx DMA hand shake at I/O pins)

The general function of this bit is to indicate that the TxFIFO has an
at least one empty space for data. The particular meaning of the bit
is controlled by MR0 [5:4] indicates the TxFIFO may be loaded with
one or more characters. If MR0[5:4] = 00 (the default condition) this
bit will not set until the TxFIFO is empty—256 bytes available. If the
fill level of the TxFIFO is below the trigger level programmed by the
TxINT field of the Mode Register 0, this bit will be set. A one in this
position indicates that at least one character can be sent to the
TxFIFO. It is turned off as the TxFIFO is filled above the level
programmed by MR0[5:4. This bit turns on as the FIFO empties.
(Note that the RxFIFO bit turns on as the FIFO fills.) This often a
point of confusion in programming interrupt functions for the receiver
and transmitter FIFOs.
NOTE: This bit must be at a one (1) for the transmitter to enter the

arbitration process. It is the fact that this bit is zero (0) when the
TxFIFO is full that stops a full TxFIFO from entering the interrupt
arbitration. Also note that the meaning if this bit is not quite the same
as the similar bit in the status register (SR).
Philips Semiconductors Product data sheet
SC28L202Dual UART
IMR – Interrupt Mask Register A and B

The programming of this register selects which bits in the ISR cause
an interrupt output. If a bit in the ISR is a ’1’ and the corresponding
bit in the IMR is a ’1’, the interrupt source is presented to the internal
interrupt arbitration circuits, eventually resulting in the IRQN output
being asserted (low). If the corresponding bit in the IMR is a zero,
the state of the bit in the ISR has no affect on the IRQN output.
IMR[7] COS enable

Allows a change of state in the inputs equipped with input change
detectors to cause an interrupt.
IMR[6] Fixed Watchdog Enable

Controls the generation of an interrupt watchdog timer event. If set,
a count of 64 idle bit times in the receiver will begin interrupt
arbitration.
IMR[5] Address recognition enable

Enables the generation of an interrupt in response to changes in the
Address Recognition circuitry of the Special Mode (multi-drop or
wake-up mode).
IMR[4] Xon/Xoff Enable

Enables the generation of an interrupt in response to recognition of
an in-band flow control character.
IMR[3] Counter/Timer Enable

Enable the C/T interrupt when the C/T reaches 0 count.[2] Enables
the generation of an interrupt when a Break condition has been
detected by the channel receiver.
IMR[1] Receiver (Rx) Enable

Enables the generation of an interrupt when servicing for the
RxFIFO is desired.
IMR[0] Transmitter (Tx) Enable

Enables the generation of an interrupt when servicing for the
TxFIFO is desired.
RxFIFO – Receiver FIFO, A and B

The FIFO for the receiver is 11 bits wide and 256 ‘words’ deep. The
status of each byte received is stored with that byte and is moved
along with the byte as the characters are read from the FIFO. The
upper three bits are presented in the STATUS register and they
change in the status register each time a data byte is read from the
FIFO. Therefor the status register should be read BEFORE the byte
is read from the RxFIFO if one wishes to ascertain the quality of the
byte.
The foregoing applies to the ‘character error’ mode of status
reporting. See MR1[5] and ‘RxFIFO Status’ descriptions for ‘block
error’ status reporting. Briefly, ‘Block Error’ gives the accumulated
error of all bytes received by the RxFIFO since the last ‘Reset Error’
command was issued. (CR = 0x04)
TxFIFO – Transmitter FIFO, A and B

The FIFO for the transmitter is 8 bits wide by 256 bytes deep. For character lengths less than 8 bits the upper bits will be ignored by the
transmitter state machine and thus are effectively discarded.
RxFIL – Receiver FIFO Interrupt Level, A and B

The position in the Rx FIFO that causes the receiver will enter the interrupt arbitration process. This register is used to offset the effect of the
arbitration threshold. It use may yield moderate improvements in the interrupt service. It will also ‘equalize’ interrupt latency and allow for larger
aggregate block transfers between fast and slow channels. Writing to this register removes the interrupt control established in MR0 and MR1.
RxFL – Receiver FIFO Fill Level Register
Philips Semiconductors Product data sheet
SC28L202Dual UART
TxFIL – Transmitter FIFO Interrupt Level A and B

The position in the Tx FIFO that caused the transmitter will enter the interrupt arbitration process. This register is used to offset the effect of the
arbitration threshold. It use may yield moderate improvements in the interrupt service. It will also ‘equalize’ interrupt latency and allow for larger
aggregate block transfers between fast and slow channels. Writing to this register removes the interrupt control established in MR0 and MR1.
TxEL – Transmitter FIFO Empty Level Register

The number of empty bytes in the Transmitter FIFO.
Registers for Character Recognition

Please not that, although the names of the registers imply a particular function, there is not any hardware function directly attached to them.
They are just three characters that may be used for any function requiring recognition or simple character stripping.
It is only when other internal logic is enabled that the reception of a recognized character will trigger particular chip functions and/or interrupts.
XonCR – Xon/Xoff Character Register A and B

An 8-bit character register that contains the compare value for a Xon character.
XoffCR – Xoff Character Register A and B

An 8-bit character register that contains the compare value for a Xoff character.
ARCR – Address Recognition Character Register A and B

An 8 bit character register that contains the compare value for the wake-up address character.
Philips Semiconductors Product data sheet
SC28L202Dual UART
XISR – Xon–Xoff Interrupt Status Register A and B (Reading this register clears XISR(7:4))
XISR[7:6] Received X Character Status.

This field can be read to determine if the receiver has encountered a
Xon or Xoff character in the incoming data stream. These bits are
maintained until a read of the XISR. The field is updated by X
character reception regardless of the state of MR3(7) and MR3(3:2)
or IMR(4). The field can therefore be used as a character detector
for the bit patterns stored in the Xon and Xoff Character Registers.
XISR[5:4] Automatic transmission Status.

This field indicates the last flow control character sent in the Auto
Receiver flow control mode. If Auto Receiver mode has not been
enabled, this field will always read b’00. It will likewise reset to b’00 if
MR0(3) is reset. If the Auto Receiver mode is exited while this field
reads b’10, it is the user’s responsibility to transmit a Xon, when
appropriate.
XISR[3:2] TxD Condition of the automatic flow control status.

This field tracks the transmitter’s flow status as follows: 00 – normal transmission. Transmitter is not affected by Xon or
Xoff. 01 – TxD halt pending. After the current character finishes the
transmitter will stop. The status will then change to b’11. 10 – re–enabled. The transmitter had been halted and has been
restarted. It is sending (or is prepared to send) data characters.
After a read of the XISR, it will return to ‘normal’ status. 11 – The transmitter is stopped due to an Xoff character being
received from its associated receiver. The transmitter is ‘flow
controlled’.
XISR[1:0] TxD X character Status.

This field allows determination of the type of character being
transmitted. It will always be b’00 if none of the automatic X
character controls of MR3[3:2] is enabled. 01 – The channel is waiting for a data character to transfer from
the TxFIFO. This condition will only occur for a bit time after a Xon
or Xoff character transmission unless the TxFIFO is empty. 10 – A command to send an Xoff character is pending. 11 – A command to send an Xon character is pending.
Conditions b’10 and b’11 will not exist for more than a character
time.
WCXER Watch Dog, Character, Address and X Enable Register – A and B

This register enables the UART’s Character Recognition, Address
Recognition and Receiver watchdog timer. If both enable and
disable are active a disable results. This register is used to enable
the general–purpose character recognition feature WITHOUT
causing any Xon/Xoff or wakeup mode activities to occur. The
recognition event is reported in the ISR register.
* This bit control is duplicated at MR0[7].
Philips Semiconductors Product data sheet
SC28L202Dual UART
Programmable Counters, Timers and Baud Rate generators
PBRGPU – Programmable BRG Timer Reload Registers, Upper 0 and 1

This is the upper byte of the 16–bit value used by the BRG timer in generating a baud rate clock
PBRGPL – Programmable BRG Timer Reload Registers, Lower 0 and 1

This is the lower byte of the 16–bit value used by the BRG timer in generating a baud rate clock.
CTCS 0 and 1 – Counter Timer clock source
NOTE: Writing to this register removes the control established in the counter/timer portion of the ACR in the default register map
CTVU – Counter Timer Value Registers, Upper 0 and 1

Reading this register gives the value of the upper 8 bits of the counter timer.
CTVL – Counter timer Value Registers, Lower 0 and 1

Reading this register gives the value of the upper 8 bits of the
counter timer.
NOTE: The counter timer should be stopped before reading. Usually

the clock of the counter timer is not synchronized with the read of
the C/T. It is therefore possible to capture changing data during the
read. Depending on the clock speed with respect to the read cycle
this could be made worse or completely eliminated. If the Stop
counter command is issued and following that the C/T is read there
will be no uncertainty go its value. If it is necessary to read the C/T
‘on the fly’ then reading it twice and comparing the values will
correct the problem. The double read will not be effective if the
counter timer clock is faster than a read cycle.
PBRGCS – Programmable BRG Clock Source

Start/Stop control and clock select register for the two BRG
receiver(s) or transmitter(s) the receivers and transmitters will
Philips Semiconductors Product data sheet
SC28L202Dual UART
CTPU Counter Timer Preset Upper 0 and 1
CTPL Counter –Timer Preset Low 0 and 1

The CTPU and CTPL hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value that
may be loaded into the CTPU/CTPL registers is H‘0000’. Note that
these registers are write–only and cannot be read by the CPU.
In the timer mode, the C/T generates a square wave whose period is
twice the value (in C/T clock periods) of the CTPU and CTPL. The
waveform so generated is often used for a data clock. The formula
for calculating the divisor n to load to the CTPU and CTPL for a
particular 1X data clock is shown below.
NOTE: The 2 in the denominator is for the Square wave generation.

For the Pulse mode change the 2 to a 1.� C/T clock input frequency�16� (Baud rate desired))
(If the pulse mode is selected, then ‘2’ in the divisor should be ‘1’.
This doubles the C/T output speeds for any given input clock.)
Often this division will result in a non–integer number, 26.3 for
example. One can only program integer numbers in a digital divider.
Therefore, 26 would be chosen. This gives a baud rate error of
0.3/26.3, which is 1.14% and well within the ability asynchronous
mode of operation.
If the value in CTPU and CTPL is changed, the current half–period
will not be affected, but subsequent half periods will be. The C/T will
not be running until it receives an initial ‘Start Counter’ command
from the command register (or a read at address A6–A0 = 0001110
in the lower 16 position address space) . After this, while in timer
mode, the C/T will run continuously. Receipt of a start counter
command causes the counter to terminate the current timing cycle
and to begin a new cycle using the values in CTPU and CTPL.
The counter ready status bit (ISR [3]) is set once each cycle of the
square wave. The bit is reset by a stop counter command from the
command register (or a read with A6–A0 = 0x0F in the lower 16
position address space). The command however, does not stop the
C/T. the generated square wave is output on I/O3 if it is programmed
to be the C/T output. In the counter mode, the value C/T loaded into
CTPU and CTPL by the CPU is counted down to 0. Counting begins
upon receipt of a start counter command. Upon reaching terminal
count H‘0000’, the counter ready interrupt bit (ISR [3]) is set. The
counter continues counting past the terminal count until stopped by
the CPU. If I/O3 is programmed to be the output of the C/T, the
output remains high until terminal count is reached; at which time it
goes low. The output returns to the High State and ISR [3] is cleared
when the counter is stopped by a stop counter command. The CPU
may change the values of CTPU and CTPL at any time, but the new
count becomes effective only on the next start counter commands. If
new values have not been loaded, the previous count values are
preserved and used for the next count cycle
In the counter mode, the current value of the upper and lower 8 bits
of the counter (CTPU, CTPL) may be read by the CPU. It is
recommended that the counter be stopped when reading to prevent
potential problems that may occur if a carry from the lower 8 bits to
the upper 8 bits occurs between the times that both halves of the
counter are read. However, note that a subsequent start counter
command will cause the counter to begin a new count cycle using
the values in CTPU and CTPL. When the C/T clock divided by 16 is
selected, the maximum divisor becomes 1,048,575.
The CTS, RTS, CTS Enable Tx signals

CTS (Clear To Send) is usually meant to be a signal to the
transmitter meaning that it may transmit data to the receiver. The
CTS input is on pin I/O0 A for Tx A and on I/O1 A for Tx B. The CTS
signal is active low; thus; it is called CTSN A for Tx A and CTSN B
for Tx B. RTS is usually meant to be a signal from the receiver
indicating that the receiver is ready to receive data. It is also active
low and is, thus, called RTSN A for Rx A and RTSN B for Rx B.
RTSN A is on pin I/O0 B and RTSN B is on I/O1 B. A receiver’s
RTSN output will usually be connected to the CTS input of the
associated transmitter. Therefore, one could say that RTS and CTS
are different ends of the same wire!
MR2 (4) is the bit that allows the transmitter to be controlled by the
CTS pin (I/O0 A or I/O1 A). When this bit is set to one AND the CTS
input is driven high, the transmitter will stop sending data at the end
of the present character being serialized. It is usually the RTS output
of the receiver that will be connected to the transmitter’s CTS input.
The receiver will set RTS high when the receiver FIFO is full AND
the start bit of the ninth character is sensed. Transmission then
stops with nine valid characters in the receiver. When MR2 (4) is set
to one, CTSN must be at zero for the transmitter to operate. If MR2
(4) is set to zero, the I/O pin will have no effect on the operation of
the transmitter. MR1 (7) is the bit that allows the receiver to control
I/O0 B. When the receiver controls I/O0 B (or I/O1 B), the meaning
of that pin will be the RTSN function.
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