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SC28L198A1BE
Octal UART for 3.3V and 5V supply voltage
Product specification
Supersedes data of 1998 Nov 04
IC19 Data Handbook
1999 Jan 14
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
Table of Contents
Description 2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uses 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features 3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configurations 4
. . . . . . . . . . . . . . . . . . . . . . . . .
Pinout 4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 6
. . . . . . . . . . . . . . . . .
Block Diagram 7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description 7
. . . . . . . . . . . . . . . . . . . . .
Conceptual Overview 7
. . . . . . . . . . . . . . . . . . . . . . . Host Interface 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous bus cycle 7. . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous bus cycle 7. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Circuits 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sclk – System Clock 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Generator BRG 8. . . . . . . . . . . . . . . . . . . . . . . .
BRG Counters (Used for random baud rate generation) 8
Channel Blocks 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Character Recognition 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Registers 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Ports 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Descriptions 9
. . . . . . . . . . . . . . . . . . . . . . .
Receiver and Transmitter 9
. . . . . . . . . . . . . . . . . . . Transmitter 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Bits 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission of ”break” 10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1x and 16x modes, Transmitter 10. . . . . . . . . . . . . . . . . . . . .
Transmitter FIFO 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1x and 16x mode, Receiver 10. . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Status Bits 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver FIFO 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxFIFO Status: Status reporting modes 11. . . . . . . . . . . . . .
I/O ports 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Pins 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Registers 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Character Recognition 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Xon Xoff Characters 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-drop or Wake up or 9 bit mode 12. . . . . . . . . . . . . . . . .
Character Stripping 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Arbitration and IRQN generation 12. . . . . . . . . . . . . . . .
IACKN Cycle, Update CIR 13. . . . . . . . . . . . . . . . . . . . . . . . . .
Polling 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling and Activating Interrupt sources 13. . . . . . . . . . . . .
Setting Interrupt Priorities 13. . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation 14
. . . . . . . . . . . . . . . . . . . . . . . . Major Modes 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minor Modes 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watch-dog Timer Time–out Mode 15. . . . . . . . . . . . . . . . . . .
Wake Up Mode 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Xon/Xoff Operation 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER DEFINITIONS 18
. . . . . . . . . . . . . . . . . . . . MR – Mode Registers 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UCIR – Update CIR 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Output Pin Control 30
. . . . . . . .
Register Maps 31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Map Summary 31
. . . . . . . . . . . . . . . . . . . . .
Register Map Detail 32
. . . . . . . . . . . . . . . . . . . . . . . .
Reset Conditions 41
. . . . . . . . . . . . . . . . . . . . . . . . . . . Device Configuration after Hardware Reset or CRa cmd=x1F 41
Cleared registers: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clears Modes for: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disables: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Halts: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limitations: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Specifications (5V) 42
. . . . . . . . . . . .
AC Electrical Characteristic (5V) 43
. . . . . . . . . . . .
DC Electrical Specifications (3.3V) 45
. . . . . . . . . .
AC Electrical Characteristics (3.3V) 46
. . . . . . . . . .
INDEX 52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESCRIPTIONThe Philips 28L198 Octal UART is a single chip CMOS–LSI
communications device that provides 8 full-duplex asynchronous
channels with significantly deeper 16 byte FIFOs, Automatic
in–band flow control using Xon/Xoff characters defined by the user
and address recognition in the wake up mode. Synchronous bus
interface is used for all communication between host and OCTART.
It is fabricated using Philips 1.0 micron CMOS technology that
combines the benefits of low cost, high density and low power
consumption.
The operating speed of each receiver and transmitter can be
selected independently from one of 22 fixed baud rates, a 16X clock
derived from one of two programmable baud rate counters or one of
three external 16X clocks (1 available at 1x clock rate). The baud
rate generator and counter can operate directly from a crystal or
from seven other external or internal clock inputs. The ability to
independently program the operating speed of the receiver and
transmitter makes the Octal UART particularly attractive for dual
speed full duplex channel applications such as clustered terminal
systems. The receivers and transmitters are buffered with FIFOs of
16 characters to minimize the potential for receiver overrun and to
reduce interrupt overhead. In addition, a handshaking capability and
in–band flow control are provided to disable a remote UART
transmitter when the receiver buffer is full or nearly so.
To minimize interrupt overhead an interrupt arbitration system is
included which reports the context of the interrupting UART via
direct access or through the modification of the interrupt vector. The
context of the interrupt is reported as channel number, type of
device interrupting ( receiver COS etc.) and, for transmitters or
receivers, the fill level of the FIFO.
The Octal UART provides a power down mode in which the
oscillator is stopped but the register contents are maintained. This
results in reduced power consumption of several orders of
magnitudes. The Octal UART is fully TTL compatible when
operating from a single +5V power supply. Operation at 3.3 volts is
maintained with CMOS interface levels.
The device also offered in a version which maintains TTL input and
output levels while operating with a 3.3 volt power supply.
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
UsesStatistical Multiplexers
Data Concentrators
Packet–switching networks
Process Control
Building or Plant Control
Laboratory data gathering
ISDN front ends
Computer Networks
Point–of–Sale terminals
Automotive, cab and engine controls
Entertainment systems
MIDDI keyboard control music systems
Theater lighting control
Terminal Servers
Computer–Printer/Plotter links
FEATURES Single 3.3V and 5V power supply Eight Philips industry standard full duplex UART channels Sixteen byte receiver FIFOs for each UART Sixteen byte transmit FIFOs for each UART In band flow control using programmable Xon/Xoff characters Flow control using CTSN RTSN hardware handshaking Automatic address detection in multi-drop mode Three byte general purpose character recognition Fast data bus, 30 ns data bus release time, 125 ns bus cycle time Programmable interrupt priorities Automatic identification of highest priority interrupt pending Global interrupt and control registers ease setup and interrupt
handling Vectored interrupts with programmable interrupt vector formats
Interrupt vector modified with channel number
Interrupt vector modified with channel number and channel type
Interrupt vector not modified IACKN and DACKN signal pins Watch dog timer for each receiver (64 receive clock counts) Programmable Data Formats:
5 to 8 data bits plus parity
Odd, even force or no parity
1, 1.5 or 2 stop bits Flexible baud rate selection for receivers and transmitters:
22 fixed rates; 50 – 230.4K baud or 100 to 460.8K baud
Additional non–standard rates to 500K baud with internal
generators
Two reload–counters provide additional programmable baud
rate generation
External 1x or 16x clock inputs
Simplified baud rate selection 1 MHz 1x and 16x data rates full duplex all channels. Parity, framing and overrun error detection False start bit detection Line break detection and generation Programmable channel mode
Normal(full duplex)
Diagnostic modes
automatic echo
local loop back
emote loop back Four I/O ports per UART for modem controls, clocks, RTSN, I/O
etc.
All I/O ports equipped with ”Change of State Detectors” Two global inputs and two global outputs for general purpose I/O Power down mode On chip crystal oscillator, 2–8 MHz TTL input levels. Outputs switch between full VCC and VSS High speed CMOS technology 84 pin PLCC 100 pin LQFP
ORDERING CODE
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
PIN CONFIGURATIONS
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Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
PIN CONFIGURATIONS
PINOUT ÁÁÁÁÁ
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Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
Pin DescriptionÁÁÁÁÁ
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NOTE: Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf.) These edges may move as fast as 1 to 3 ns
fall or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See
previous note on Sclk noise under pin assignments.
ABSOLUTE MAXIMUM RATINGS1ÁÁÁÁÁÁ
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NOTES: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is
not implied.
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
BLOCK DIAGRAMAs shown in the block diagram, the Octal UART consists of: an
interrupt arbiter, host interface, timing blocks and eight UART
channel blocks. The eight channels blocks operate independently,
interacting only with the timing, host I/F and interrupt blocks.
FUNCTIONAL DESCRIPTIONThe SC28L198 is composed of several functional blocks: Synchronous host interface block A timing block consisting of a common baud rate generator
making 22 industry standard baud rates and 2 16–bit counters
used for non–standard baud rate generation 4 identical independent full duplex UART channel blocks Interrupt arbitration system evaluating 24 contenders I/O port control section and change of state detectors.
CONCEPTUAL OVERVIEW
Host InterfaceThe Host interface is comprised of the signal pins CEN, W/RN,
IACKN, DACKN, IRQN Sclk and provides all the control for data
transfer between the external and internal data buses of the host
and the OCTART. The host interface operates in a synchronous
mode with the system (Sclk) which has been designed for a nominal
operating frequency of 33 MHz. The interface operates in either of
occurs in the C4 time and occurs approximately 18 ns after the
rising edge of C4.
Addressing of the various functions of the OCTART is through the
address bus A(7:0). The 28L198 is compatible with the SC28L198
OCTAL UART in software and function. A[7], in a general sense, is
used to separate the data portion of the circuit from the control
portion.
Asynchronous bus cycleThe asynchronous mode requires one bus cycle of the chip select
(CEN) for each read or write to the chip. No more action will occur
on the bus after the C4 time until CEN is returned high.
Synchronous bus cycleIn the synchronous mode a read or write will be done every four
cycles of the Sclk. CEN does not require cycling but must remain
low to keep the synchronous accesses active. This provides a burst
mode of access to the chip.
In both cases each read or write operation(s) will be completed in
four (4) Sclk cycles. The difference in the two modes is only that the
asynchronous mode will not begin another bus cycle if the CEN
remains active after the four internal Sclk have completed. Internally
the asynchronous cycle will terminate after the four periods of Sclk
regardless of how long CEN is held active
In all cases the internal action will terminate at the withdrawal of
CEN. Synchronous CEN cycles shorter than multiples of four Sclk
cycles minus 1 Sclk and asynchronous CEN cycles shorter than four
Sclk cycles may cause short read or write cycles and produce
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
counters. A buffer for the System Clock generates internal timing for
processes not directly concerned with serial data flow.
Crystal OscillatorThe crystal oscillator operates directly from a crystal, tuned between
1.0 and 8.0 MHz, connected across the X1/CCLK and X2 inputs with
a minimum of external components. BRG values listed for the clock
select registers correspond to a 3.6864 MHz crystal frequency. Use
of a 7.3728 MHz crystal will double the Communication Clock
frequencies.
An external clock in the 100 KHz to 10 MHz frequency range may
be connected to X1/CCLK. If an external clock is used instead of a
crystal, X1/CCLK must be driven and X2 left floating. The X1 clock
serves as the basic timing reference for the baud rate generator
(BRG) and is available to the BRG timers . The X1 oscillator input
may be left unused if the internal BRG is not used and the X1 signal
is not selected for any counter input.
Sclk – System ClockA clock frequency, within the limits specified in the electrical
specifications, must be supplied for the system clock Sclk. To
ensure the proper operation of internal controllers, the Sclk
frequency provided, must be strictly greater than twice the frequency
of X1 crystal clock, or any external 1x data clock input. The system
clock serves as the basic timing reference for the host interface and
other internal circuits.
Baud Rate Generator BRGThe baud rate generator operates from the oscillator or external
X1/CCLK clock input and is capable of generating 22 commonly
used data communications baud rates ranging from 50 to 230.4K
baud. These common rates may be doubled (up to 460.8 and 500K
baud) when faster clocks are used on the X1/X2 clock inputs. (See
Receiver and Transmitter Clock Select Register descriptions.) All of
these are available simultaneously for use by any receiver or
transmitter. The clock outputs from the BRG are at 16X the actual
baud rate.
BRG Counters (Used for random baud rate generation)The two BRG Timers are programmable 16 bit dividers that are used
for generating miscellaneous clocks. These clocks may be used by
any or all of the receivers and transmitters in the Octart or output on
the general purpose output pin GPO.
Each timer unit has eight different clock sources available to it as
described in the BRG Timer Control Register. (BRGTCR). Note
that the timer run and stop controls are also contained in this
register. The BRG Timers generate a symmetrical square wave
whose half period is equal in time to the division of the selected
BRG Timer clock source by the number loaded to the BRG Timer
Reload Registers ( BRGTRU and BRGTRL). Thus, the output
frequency will be the clock source frequency divided by twice the
value loaded to the BRGTRU and BRGTRL registers. This is the
result of counting down once for the high portion of the output wave
and once for the low portion.
Whenever the these timers are selected via the receiver or
transmitter Clock Select register their output will be configured as a
16x clock for the respective receiver or transmitter. Therefore one
needs to program the timers to generate a clock 16 times faster than
Note: ’n’ may assume values of 0 and 1. In previous Philips data
communications controllers these values were not allowed.
The BRG timer input frequency is controlled by the BRG Timer
control register (BRGTCR)
The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and
receiver state machines include divide by 16 circuits which provide
the final frequency and provide various timing edges used in the
qualifying the serial data bit stream. Often this division will result in
a non–integer value; 26.3 for example. One may only program
integer numbers to a digital divider. There for 26 would be chosen.
If 26.7 was the result of the division then 27 would be chosen. This
gives a baud rate error of 0.3/26.3 or 0.3/26.7. which yields a
percentage error of 1.14% or 1.12% respectively; well within the
ability of the asynchronous mode of operation.
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is
communicating may also have a small error in the precise baud rate.
In a ”clean” communications environment using one start bit, eight
data bits and one stop bit the total difference allowed between the
transmitter and receiver frequency is approximately 4.6%. Less
than eight data bits will increase this percentage.
Channel BlocksThere are eight channel blocks, each containing an I/O port control,
a data format control, and a single full duplex UART channel
consisting of a receiver and a transmitter with their associated 16
byte FIFOs. Each block has its own status register, interrupt status
and interrupt mask registers and their interface to the interrupt
arbitration system.
A highly programmable character recognition system is also
included in each block. This system is used for the Xon/Xoff flow
control and the multi-drop (”9 bit mode”) address character
recognition. It may also be used for general purpose character
recognition.
Four I/O pins are provided for each channel. These pins are
configured individually to be inputs or outputs. As inputs they may
be used to bring external data to the bus, as clocks for internal
functions or external control signals. Each I/O pin has a ”Change of
State” detector. The change detectors are used to signal a change
in the signal level at the pin (Either 0 to 1 or 1 to 0). The level
change on these pins must be stable for 25 to 50 Us (two edges of
the 38.4 KHz baud rate clock) before the detectors will signal a valid
change. These are typically used for interface signals from modems
to the OCTART and from there to the host. See the description of
the ”UART channel” under detailed descriptions below.
Character RecognitionCharacter recognition is specific to each of the eight UARTs. Three
programmable characters are provided for the character recognition
for each channel. The three are general purpose in nature and may
be set to only cause an interrupt or to initiate some rather complex
operations specific to ”Multi-drop” address recognition or in–band
Xon/Xoff flow control.
Character recognition is accomplished via CAM memory. The
Content Addressable Memory continually examines the incoming
data stream. Upon the recognition of a control character appropriate
bits are set in the Xon/Xoff Interrupt Status Register (XISR) and
Interrupt Status Register (ISR). The setting of these bit(s) will
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
value”. They may, however, be loaded by a “Gang White” or “Gang
Load” command as described in the “Xon Xoff Characters”
paragraph.
Note: Character recognition is further described in the Minor Modes
of Operation.
Interrupt ControlThe interrupt system determines when an interrupt should be
asserted thorough an arbitration (or bidding) system. This
arbitration is exercised over the several systems within the OCTART
that may generate an interrupt. These will be referred to as
”interrupt sources”. There are 64 in all. In general the arbitration is
based on the fill level of the receiver FIFO or the empty level of the
transmitter FIFO. The FIFO levels are encoded into a four bit
number which is concatenated to the channel number and source
identification code. All of this is compared (via the bidding or
arbitration process) to a user defined ”threshold”. When ever a
source exceeds the numerical value of the threshold the interrupt
will be generated.
At the time of interrupt acknowledge (IACKN) the source which has
the highest bid (not necessarily the source that caused the interrupt
to be generated) will be captured in a ”Current Interrupt Register”
(CIR). This register will contain the complete definition of the
interrupting source: channel, type of interrupt (receiver, transmitter,
change of state, etc.), and FIFO fill level. The value of the bits in the
CIR are used to drive the interrupt vector and global registers such
that controlling processor may be steered directly to the proper
service routine. A single read operation to the CIR provides all the
information needed to qualify and quantify the most common
interrupt sources.
The interrupt sources for each channel are listed below. Transmit FIFO empty level for each channel Receive FIFO Fill level for each channel Change in break received status for each channel Receiver with error for each channel Change of state on channel input pins Receiver Watch-dog Time out Event Xon/Xoff character recognition Address character recognition
Associated with the interrupt system are the interrupt mask register
(IMR) and the interrupt status register (ISR) resident in each UART.
Programming of the IMR selects which of the above sources may
enter the arbitration process. Only the bidders in the ISR whose
associated bit in the IMR is set to one (1) will be permitted to enter
the arbitration process. The ISR can be read by the host CPU to
determine all currently active interrupting conditions. For
convenience the bits of the ISR may be masked by the bits of the
IMR. Whether the ISR is read unmasked or masked is controlled by
the setting of bit 6 in MR1.
Global RegistersThe ”Global Registers”, 19 in all, are driven by the interrupt system.
These are not real hardware devices. They are defined by the
presently causing an interrupt. The principle purpose of these
”registers” is improving the efficiency of the interrupt service.
The global registers and the CIR update procedure are further
described in the Interrupt Arbitration system
I/O PortsEach of the eight UART blocks contains an I/O section of four ports.
These ports function as a general purpose post section which
services the particular UART they are associated with. External
clocks are input and internal clocks are output through these ports.
Each of the four pins has a change of state detector which will signal
a change (0 to 1 or 1 to 0) at the pin. The change of state detectors
are individually enabled and may be set to cause and interrupt.
These pins will normally be used for flow control hand–shaking and
the interface to a modem. Their control is further described in I/O
Ports section and the I/OPCR register.
DETAILED DESCRIPTIONS
RECEIVER AND TRANSMITTERThe Octal UART has eight full-duplex asynchronous
receiver/transmitters. The operating frequency for the receiver and
transmitter can be selected independently from the baud rate
generator, the counter , or from an external input. Registers that are
central to basic full-duplex operation are the mode registers (MR0,
MR1 and MR2), the clock select registers (RxCSR and TxCSR), the
command register (CR), the status register (SR), the transmit
holding register (TxFIFO), and the receive holding register
(RxFIFO).
TransmitterThe transmitter accepts parallel data from the CPU and converts it
to a serial bit stream on the TxD output pin. It automatically sends a
start bit followed by the programmed number of data bits, an
optional parity bit, and the programmed number of stop bits. The
least significant bit is sent first. Each character is always ”framed”
by a single start bit and a stop bit that is 9/16 bit time or longer. If a
new character is not available in the TxFIFO, the TxD output
remains high, the ”marking” position, and the TxEMT bit in the SR is
set to 1.
Transmitter Status Bits The SR (Status Register, one per UART) contains two bits that show
the condition of the transmitter FIFO. These bits are TxRDY and
TxEMT. TxRDY means the TxFIFO has space available for one or
more bytes; TxEMT means The TxFIFO is completely empty and
the last stop bit has been completed. TxEMT can not be active
without TxRDY also being active. These two bits will go active upon
initial enabling of the transmitter. They will extinguish on the disable
or reset of the transmitter.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads at least one new character into the TxFIFO. The TxRDY will
not extinguish until the TxFIFO is completely full. The TxRDY bit will
always be active when the transmitter is enabled and there is at
lease one open position in the TxFIFO.
The transmitter is disabled by reset or by a bit in the command
register (CR). The transmitter must be explicitly enabled via the CR
before transmission can begin. Note that characters cannot be
loaded into the TxFIFO while the transmitter is disabled, hence it is
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
software reset is issued through command 3x of the Command
register (CR). The disable is done by setting the transmitter disable
bit also in the command register. If the transmitter is disabled, it
continues operating until the character currently being transmitted, if
any, is completely sent, including the stop bit. When reset the
transmitter stops immediately, drives the transmitter serial data out
put to a high level and discards any data in the TxFIFO.
Transmission of ”break”sTransmission of a break character is often needed as a
synchronizing condition in a data stream. The ”break” is defined as
a start bit followed by all zero data bits by a zero parity bit (if parity is
enabled) and a zero in the stop bit position. The forgoing is the
minimum time to define a break. The transmitter can be forced to
send a break (continuous low condition) by issuing a start break
command via the CR. This command does not have any timing
associated with it. Once issued the TxD output will be driven low
(the spacing condition) and remain there until the host issues a
command to ”stop break” via the CR or the transmitter is issued a
software or hardware reset. In normal operation the break is usually
much longer than one character time.
1x and 16x modes, TransmitterThe transmitter clocking has two modes: 16x and 1x. Data is
always sent at the 1x rate. However the logic of the transmitter maybe operated with a clock that is 16 times faster than the data rate or
at the same rate as the data i.e. 1x. All clocks selected internally
for the transmitter (and the receiver) will be 16x clocks. Only when
an external clock is selected may the transmitter logic and state
machine operate in the 1x mode. The 1x or 16x clocking makes
little difference in transmitter operation. (this is not true in the
receiver) In the 16X clock mode the transmitter will recognize a byte
in the TxFIFO within 1/16 to 2/16 bit time and thus begin
transmission of the start bit; in the 1x mode this delay may be up to
2 bit times.
Transmitter FIFOThe transmitter buffer memory is a 16 byte by 8 bit ripple FIFO. The
host writes characters to this buffer. This buffer accepts data only
when the transmitter is enabled. The transmitter state machine
reads them out in the order they were received and presents them to
the transmitter shift register for serialization. The transmitter adds
the required start, parity and stop bits as required the MR2 register
programming. The start bit (always one bit time in length) is sent
first followed by the least significant bit (LSB) to the most significant
bit (MSB) of the character, the parity bit (if used) and the required
stop bit(s).
Logic associated with the FIFO encodes the number of empty
positions available in a four bit value. This value is concatenated
with the channel number and type interrupt type identifier and
presented to the interrupt arbitration system. The encoding of the
”positions empty” value is always 1 less than the number of
available positions. Thus, an empty TxFIFO will bid with the value
or 15; when full it will not bid at all; one position empty bids with the
value 0. A full FIFO will not bid since a character written to it will be
lost
Normally a TxFIFO will present a bid to the arbitration system when
ever it has one or more empty positions. The MR0[5:4] allow the
user to modify this characteristic so that bidding will not start until
ReceiverThe receiver accepts serial data on the RxD pin, converts the serial
input to parallel format, checks for start bit, stop bit, parity bit (if
any),framing error or break condition, and presents the assembled
character and its status condition to the CPU via the RxFIFO. Three
status bits are FIFOed with each character received. The RxFIFO is
really 11 bits wide; eight data and 3 status. Unused FIFO bits for
character lengths less than 8 bits are set to zero. It is important to
note that receiver logic considers the entire message to be
contained within the start bit to the stop bit. It is not aware that a
message may contain many characters. The receiver returns to its
idle mode at the end of each stop bit! As described below it
immediately begins to search for another start bit which is normally,
of course, immediately forth coming.
1x and 16x mode, ReceiverThe receiver operates in one of two modes; 1x and 16x. Of the two,
the 16x is more robust and the preferred mode. Although the 1x
mode may allow a faster data rate is does not provide for the
alignment of the receiver 1x data clock to that of the transmitter.
This strongly implies that the 1x clock of the remote transmitter is
available to the receiver; the two devices are physically close to
each other.
The 16x mode operates the receiver logic at a rate 16 times faster
than the 1x data rate. This allows for validation of the start bit,
validation of level changes at the receiver serial data input (RxD),
and a stop bit length as short as 9/16 bit time. Of most importance
in the 16x mode is the ability of the receiver logic to align the phase
of the receiver 1x data clock to that of the transmitter with an
accuracy of less than 1/16 bit time.
When the receiver is enabled ( via the CR register) it begins looking
for a high to low (mark to space) transition on the RxD input pin. If a
transition is detected, an internal counter running at 16 times the
data rate is reset to zero. If the RxD remains low and is still low
when the counter reaches a count of 7 the receiver will consider this
a valid start bit and begin assembling the character. If the RxD input
returns to a high state the receiver will reject the previous high to low
(mark to space) transition on the RxD input pin. This action is the
”validation” of the start bit and also establishes the phase of the
receiver 1x clock to that of the transmitter The counter operating at
16x the data rate is the generator for the 1x data rate clock. With
the phase of the receiver 1x clock aligned to the falling of the start
bit (and thus aligned to the transmitter clock) AND with a valid start
bit having been verified the receiver will continue receiving bits by
sampling the RxD input on the rising edge of the 1x clock that is
being generated by the above mentioned counter running 16 times
the data rate. Since the falling edge of the 1x clock was aligned to
falling edge of the start bit then the rising of the clock will be in the
”center” of the bit cell.
This action will continue until a full character has been assembled.
Parity , framing, and stop bit , and break status is then assembled
and the character and its status bits are loaded to the RxFIFO At
this point the receiver has finished its task for that character and will
immediately begin the search for another start bit.
Receiver Status BitsThere are five (5) status bits that are evaluated with each byte (or
character) received: received break, framing error, parity error,
overrun error, and change of break. The first three are appended to
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
. The ”received break” will always be associated with a zero byte in
the RxFIFO. It means that zero character was a break character
and not a zero data byte. The reception of a break condition will
always set the ”change of break” (see below) status bit in the
Interrupt Status Register(ISR).
A framing error occurs when a non zero character was seen and
that character has a zero in the stop bit position.
The parity error indicates that the receiver generated parity was not
the same as that sent by the transmitter.
The overrun error occurs when the RxFIFO is full, the receiver shift
register is full and another start bit is detected. At this moment the
receiver has 17 valid characters and the start bit of the 18th has
been seen. At this point the host has approximately 7/16 bit time to
read a byte from the RxFIFO or the overrun condition will be set and
the 18th character will overrun the 17th and the 19th the 18th and so
on until an open position in the RxFIFO is seen. The meaning of the
overrun is that data has been lost. Data in the RxFIFO remains
valid. The receiver will begin placing characters in the RxFIFO as
soon as a position becomes vacant.
Note: Precaution must be taken when reading an overrun FIFO.
There will be 16 valid characters. Data will begin loading as soon as
the first character is read. The 17th. character will have been
received as valid but it will not be known how many characters were
lost between the two characters of the 16th. and 17th. reads of the
RxFIFO
The ”Change of break” means that either a break has been detected
or that the break condition has been cleared. This bit is available in
the ISR. The beginning of a break will be signaled by the break
change bit being set in the ISR AND the received break bit being set
in the SR. At the termination of the break condition only the change
of break in the ISR will be set. After the break condition is detected
the termination of the break will only be recognized when the RxD
input has returned to the high state for two successive edges of the
1x clock; 1/2 to 1 bit time.
The receiver is disabled by reset or via CR commands. A disabled
receiver will not interrupt the host CPU under any circumstance in
the normal mode of operation. If the receiver is in the multi-drop or
special mode, it will be partially enabled and thus may cause an
interrupt. Refer to section on Wake–Up and minor modes and the
register description for MR1 for more information.
Receiver FIFOThe receiver buffer memory is a 16 byte ripple FIFO with three
status bits appended to each data byte. (The FIFO is then 16 11 bit
”words”). The receiver state machine gathers the bits from the
receiver shift register and the status bits from the receiver logic and
writes the assembled byte and status bits to the RxFIFO. Logic
associated with the FIFO encodes the number of filled positions for
presentation to the interrupt arbitration system. The encoding is
always 1 less than the number of filled positions. Thus, a full
RxFIFO will bid with the value or 15; when empty it will not bit at all;
one position occupied bids with the value 0. An empty FIFO will not
bid since no character is available. Normally RxFIFO will present a
bid to the arbitration system when ever it has one or more filled
positions. The MR2[3:2 bits allow the user to modify this
characteristic so that bidding will not start until one of four levels
RxFIFO Status: Status reporting modesThe description below applies to the upper three bits in the ”Status
Register” These three bits are not ”in the status register”; They are
part of the RxFIFO. The three status bits at the top of the RxFIFO
are presented as the upper three bits of the status register included
in each UART.
The error status of a character , as reported by a read of the SR
(status register upper three bits) can be provided in two ways, as
programmed by the error mode control bit in the mode register:
”Character mode ” or the ”Block Mode”. The block mode may be
further modified (via a CR command) to set the status bits as the
characters enter the FIFO or as they are read from the FIFO.
In the ’character’ mode, status is provided on a character by
character basis as the characters are read from the RxFIFO: the
”status” applies only to the character at the top of the RxFIFO – The
next character to be read
In the ’block’ mode, the status provided in the SR for these three bits
is the logical OR of the status for all characters coming to the top of
the RxFIFO, since the last reset error command was issued. In this
mode each of the status bits stored in the RxFIFO are passed
through a latch as they are sequentially read. If any of the
characters has an error bit set then that latch will set and remain set
until reset with an ”Reset Error” command from the command
register or a receiver reset. The purpose of this mode is indicating
an error in the data block as opposed to an error in a character
The latch used in the block mode to indicate ”problem data” is
usually set as the characters are read out of the RxFIFO. Via a
command in the CR the latch may be configured to set the latch as
the characters are pushed (loaded to) the RxFIFO. This gives the
advantage of indicating ”problem data” 16 characters earlier .
In either mode, reading the SR does not affect the RxFIFO. The
RxFIFO is ’popped’ only when the RxFIFO is read. Therefore, the
SR should be read prior to reading the corresponding data
character.
If the RxFIFO is full when a new character is received, that
character is held in the receive shift register until a RxFIFO position
is available. At this time there are 17 valid characters in the
RxFIFO. If an additional character is received while this state exists,
the contents of the RxFIFO are not affected: the character
previously in the shift register is lost and the overrun error status bit,
SR[4], will be set upon receipt of the start bit of the new
(overrunning) character.
I/O portsEach of the eight UARTs includes four I/O ports equipped with
”change of state” detectors. The pins are individually programmable
for an input only function or one of three output functions. These
functions are controlled by the ”I/O Port Configuration Register
(I/OPCR)) They will normally be used for the RTSN–CTSN, DTR
hardware signals, RxD or TxD input or output clocks or switch inputs
as well as data out put from the I/OPIOR register.
It is important to note that the input circuits are always active. That
is the signal on a port, whether it is derived from an internal or
external source is always available to the internal circuits associated
with an input on that port.
The ”Change of State” (COS) detectors are sensitive to both a 1 to 0
or a 0 to 1 transition. The detectors are controlled by the internal
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
the four I/O pins and their COS detectors is available at any time in
the IPR (Input Port Register)
The control of data and COS enable for these ports is through the
I/OPIOR register. This is a read/write register and gives individual
control to the enabling of the change of state detectors and also to
the level driven by I/O pins when programmed to drive the logic level
written to the four lower bits of the I/OPIOR. A read of this register
will indicate the data on the pin at the time of the read and the state
of the enabled COS detectors.
General Purpose PinsIn addition to the I/O ports for each UART four other ports are
provided which service the entire chip. Two are dedicated as inputs
and one as an output. The GIN1 and GIN0 are the input pins; GOUT0
the output. These ports are multiplexed to nearly every functional
unit in the chip. See the registers which describe the multitude of
connections available for these pins. The GOUT0 pin is highly
multiplexed output and is controlled by four (4) registers: GPOSR,
GPOR, GPOC and GPOD. The GIN0 and GIN1 pins are available to
the receivers and transmitters, BRG counters and the GOUT0 pin.
Global RegistersThe ”Global Registers”, 19 in all, are driven by the interrupt system.
These are not real hardware devices. They are defined by the
content of the CIR (Current Interrupt Register) as a result of an
interrupt arbitration. In other words they are indirect registers
pointed to by the content of the CIR. The list of global register
follows:
GIBCR The byte count of the interrupting FIFO
GICR Channel number of the interrupting channel
GITR Type identification of interrupting channel
GRxFIFO Pointer to the interrupting receiver FIFO
GTxFIFO Pointer to the interrupting transmitter FIFO
A read of the GRxFIFO will give the content of the RxFIFO that
presently has the highest bid value. The purpose of this system is
to enhance the efficiency of the interrupt system. The global
registers and the CIR update procedure are further described in the
Interrupt Arbitration system
Character RecognitionThe character recognition circuits are basically designed to provide
general purpose character recognition. Additional control logic has
been added to allow for Xon/Xoff flow control and for recognition of
the address character in the multi-drop or ”wake–up” mode. This
logic also allows for the generation of an interrupts in either the
general purpose recognition mode or the specific conditions
mentioned above.
Xon Xoff CharactersThe programming of these characters is usually done individually.
However a method has been provided to write to all of registers in
one operation. There are ”Gang Load” and a ”Gang Write”
commands provided in the channel A Command Register. When
these commands are executed all registers are programmed with
the same characters. The ”write” command loads a used defined
character; the ’load” command loads the standard Xon/Xoff
characters. Xon is x’11; Xoff x’13’. Any enabling of the Xon/Xoff
functions will use the contents of the Xon and Xoff character
accomplished by redefining the meaning of the parity bit such that it
indicates a character as address or data. While this method is fully
supported in the SC28L198 it also supports recognition of the
character itself. Upon recognition of its address the receiver will be
enabled and data pushed onto the RxFIFO.
Further the Address recognition has the ability, if so programmed, to
disable (not reset) the receiver when an address is seen that is not
recognized as its own. The particular features of ”Auto Wake and
Auto Doze” are described in the detail descriptions below.
Note: Care should be taken in the programming of the character
recognition registers. Programming x’00, for example, may result in
a break condition being recognized as a control character. This will
be further complicated when binary data is being processed.
Character StrippingThe MR0 register provides for stripping the characters used for
character recognition. Recall that the character recognition may be
conditioned to control several aspects of the communication.
However this system is first a character recognition system. The
status of the various states of this system are reported in the XISR
and ISR registers. The character stripping of this system allows for
the removal of the specified control characters from the data stream:
two for the Xon /Xoff and one for the wake up. Via control in the
MR0 register these characters may be discarded (stripped) from the
data stream when the recognition system “sees” them or they may
be sent on the RxFIFO. Whether they are stripped or not the
recognition will process them according to the action requested: flow
control, wake up, interrupt generation, etc. Care should be
exercised in programming the stripping option if noisy environments
are encountered. If a normal character was corrupted to an Xoff
character turned off the transmitter and it was then stripped, then the
stripping action could make it difficult to determine the cause of
transmitter stopping.
Interrupt Arbitration and IRQN generationInterrupt arbitration is the process used to determine that an
interrupt request should be presented to the host. The arbitration is
carried out between the ”Interrupt Threshold” and the ”sources”
whose interrupt bidding is enabled by the IMR. The interrupt
threshold is part of the ICR (Interrupt Control Register) and is a
value programmed by the user. The ”sources” present a value to
the interrupt arbiter. That value is derived from four fields: the
channel number, type of interrupt source, FIFO fill level, and
programmable value. . Only when one or more of these values
exceeds the threshold value in the interrupt control register will the
interrupt request (IRQN) be asserted.
Following assertion of the IRQN the host will either assert
IACKN(Interrupt Acknowledge) or will use the command to ”Update
the CIR”. At the time either action is taken the CIR will capture the
value of the source that is prevailing in the arbitration process. (Call
this value the winning bid)
The value in the CIR is the central quantity that results from the
arbitration. It contains the identity of the interrupting channel, the
type of interrupt in that channel (RxD, TxD, COS etc.) the fill levels
of the RxD or TxD FIFOs and , in the case of an RxD interrupt an
indicator of error data or good data. It also drives the Global
Registers associated with the interrupt. Most importantly it drives
the modification of the Interrupt Vector.The arbitration process is driven by the Sclk. It scans the 10 bits of
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
For sources other than receiver and transmitters the user may set
the high order bits of an interrupt source’s bid value, thus tailoring
the relative priority of the interrupt sources. The priority of the
receivers and transmitters is controlled by the fill level of their
respective FIFOs. The more filled spaces in the RxFIFO the higher
the bid value; the more empty spaces in the TxFIFO the higher its
priority. Channels whose programmable high order bits are set will
be given interrupt priority higher than those with zeros in their high
order bits , thus allowing increased flexibility. The transmitter and
receiver bid values contain the character counts of the associated
FIFOs as high order bits in the bid value. Thus, as a receiver’s
RxFIFO fills, it bids with a progressively higher priority for interrupt
service. Similarly, as empty space in a transmitter’s TxFIFO
increases, its interrupt arbitration priority increases.
IACKN Cycle, Update CIRWhen the host CPU responds to the interrupt, it will usually assert
the IACKN signal low. This will cause the OCTART to generate an
IACKN cycle in which the condition of the interrupting device is
determined. When IACKN asserts, the last valid interrupt number is
captured in the CIR. The value captured presents most of the
important details of the highest priority interrupt at the moment the
IACKN (or the ”Update CIR” command) was asserted.
The Octal UART will respond to the IACKN cycle with an interrupt
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or ,when ”Interrupt Vector Modification is
enabled via ICR, it may contain codes for the interrupt type and/or
interrupting channel. This allows the interrupt vector to steer the
interrupt service directly to the proper service routine. The interrupt
value captured in the CIR remains until another IACKN cycle occurs
or until an ”Update CIR” command is given to the OCTART. The
interrupting channel and interrupt type fields of the CIR set the
current ”interrupt context” of the OCTART. The channel component
of the interrupt context allows the use of Global Interrupt Information
registers that appear at fixed positions in the register address map.
For example, a read of the Global RxFIFO will read the channel B
RxFIFO if the CIR interrupt context is channel b receiver. At another
time read of the GRxFIFO may read the channel D RxFIFO (CIR
holds a channel D receiver interrupt) and so on. Global registers
exist to facilitate qualifying the interrupt parameters and for writing to
and reading from FIFOs without explicitly addressing them.
The CIR will load with x’00 if IACKN or Update CIR is asserted when
the arbitration circuit is NOT asserting and interrupt. In this
condition there is no arbitration value that exceeds the threshold
value.
PollingMany users prefer polled to interrupt driven service where there are
a large number of fast data channels and/or the host CPU’s other
interrupt overhead is low. The Octal UART is functional in this
environment.
The most efficient method of polling is the use of the ”update CIR”
command (with the interrupt threshold set to zero) followed by a
read of the CIR. This dummy write cycle will perform the same CIR
capture function that an IACKN falling edge would accomplish in an
interrupt driven system. A subsequent read of the CIR, at the same
address, will give information about an interrupt, if any. If the CIR
status or use of the global RxD and TxD registers for data transfer
as appropriate. The interrupt context will remain in the CIR until
another update CIR command or an IACKN cycle is initiated by the
host CPU occurs. The CIR loads with x’00 if Update CIR is asserted
when the arbitration circuit has NOT detected arbitration value that
exceeds the threshold value.
Traditional methods of polling status registers may also be used.
They of course are less efficient but give the most variable and
quickest method of changing the order in which interrupt sources
are evaluated and interrogated.
Enabling and Activating Interrupt sourcesAn interrupt source becomes enabled when its interrupt capability is
set by writing to the Interrupt Mask Register, IMR. An interrupt
source can never generate an IRQN or have its ”bid” or interrupt
number appear in the CIR unless the source has been enabled by
the appropriate bit in an IMR.
An interrupt source is active if it is presenting its bid to the interrupt
arbiter for evaluation. Most sources have simple activation
requirements. The watch-dog timer, break received, Xon/Xoff or
Address Recognition and change of state interrupts become active
when the associated events occur and the arbitration value
generated thereby exceeds the threshold value programmed in the
ICR (Interrupt Control Register).
The transmitter and receiver functions have additional controls to
modify the condition upon which the initiation of interrupt ”bidding”
begins: the TxINT and RxINT fields of the MR0 and MR2 registers.
These fields can be used to start bidding or arbitration when the
RxFIFO is not empty, 50% full, 75% full or 100% full. For the
transmitter it is not full, 50% empty, 75% empty and empty.
Example: To increase the probability of transferring the contents of a
nearly full RxFIFO, do not allow it to start bidding until 50% or 75%
full. This will prevent its relatively high priority from winning the
arbitration process at low fill levels. A high threshold level could
accomplish the same thing, but may also mask out low priority
interrupt sources that must be serviced. Note that for fast channels
and/or long interrupt latency times using this feature should be used
with caution since it reduces the time the host CPU has to respond
to the interrupt request before receiver overrun occurs.
Setting Interrupt PrioritiesThe bid or interrupt number presented to the interrupt arbiter is
composed of character counts, channel codes, fixed and
programmable bit fields. The interrupt values are generated for
various interrupt sources as shown in the table below: The value
represented by the bits 9 to 3 in the table below are compared
against the value represented by the “Threshold. The “Threshold”
,bits 6 to 0 of the ICR (Interrupt Control Register), is aligned such
that bit 6 of the threshold is compared to bit 9 of the interrupt value
generated by any of the sources. When ever the value of the
interrupt source is greater than the threshold the interrupt will be
generated.
The channel number arbitrates only against other channels. The
threshold is not used for the channel arbitration. This results in
channel D having the highest arbitration number. The decreasing
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
Table 1. Interrupt Arbitration PriorityÁÁÁÁÁÁÁÁÁÁ
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Note several characteristics of the above table in bits 6:3. These
bits contain the identification of the bidding source as indicated
below:
x001 Receiver without error
x101 Receiver with error
xx00 Transmitter
0010 Change of Break
0110 Change of State on I/O Ports
0111 Xon/Xoff Event
0011 Address Recognition
The codes form bits 6:3 drive part of the interrupt vector modification
and the Global Interrupt Type Register. The codes are unique to
each source type and Identify them completely. The channel
numbering progresses from ”a” to ”d” as the binary numbers 000 to
011 and identify the interrupting channel uniquely. As the channels
arbitrate ”d” will have the highest bidding value and ”a” the lowest
Note that the transmitter byte count is off–set from that of the
receiver by one bit. This is to give the receiver more authority in the
arbitration since and over–run receiver corrupts the message but an
under–run transmitter is not harmful. This puts some constraints on
how the threshold value is selected. If a threshold is chosen that
has its MSB set to one then a transmitter can never generate an
interrupt! Of course the counter point to this is the desire to set the
interrupt threshold high so interrupts occur only when a maximum or
near maximum number of characters may be transferred.
To give some control over this dilemma control bits have been
provided in the MR0 and MR2 registers of each channel to
individually control when a receiver or transmitter may interrupt. The
use of these bits will prevent a receiver or a transmitter from
entering the arbitration process even though its FIFO fill level is
above that indicated by the threshold value set. The bits in the MR0
and MR2 register are named TxINT (MR0[5:4]) and RxINT
(MR2[3:2])
The watch-dog is included in the table above to show that it affects
the arbitration. It does not have an identity of its own. A barking
watch-dog will prevent any other source type from entering the
arbitration process except enabled receivers. The threshold is
effectively set to zero when any watch-dog times out. The receivers
arbitrate among them selves and the one with the highest fill level
will win the process. Note that the receiver wining the bid may not
be the one that caused the watch-dog to bark.
The fields labeled ”Programmed Field” are the contents of the
the DSR (Data Set Ready) signal from the modem. In this case its
arbitration value should be high. Once the DSR is recognized then
its arbitration value could be reduced or turned off.
There is a single arbiter interrupt number that is not associated with
any of the UART channels. It is the ”Threshold Value” and is
comprised of 7 bits from the Interrupt Control Register, ICR, and
three zeros in the channel field. It is only when one or more of
the enabled interrupt sources generates a arbitration value
larger than the threshold value that the IRQN will be asserted.When the threshold bidding value is larger than any other bidding
value then the IRQN will be withdrawn. In this condition the CIR will
be loaded with if the IRQN or ”Update CIR” command is asserted.
Because the channels are numbered from 0 to 3 ( A to D) channel 3
will win the bid when all other parts of the bid are equal.
Note: Based on this coding for the receiver and transmitter, a
transmitter would not win a bid in the situation where the Count
Field = 0 unless the threshold value is equal or less than
0000011. A single empty slot is left in the TxFIFO or a single
filled slot in the RxFIFO will bid with a value of zero.
MODES OF OPERATION
Major ModesFour major modes of operation (normal, auto echo, local loop back
and remote loop back) are provided and are controlled by MR2[7:6].
Three of these may be considered diagnostic. See the MR2 register
description.
The normal mode is the usual mode for data I/O operation. Most
reception and transmission will use the normal mode.
In the auto echo mode, the transmitter automatically re-transmits
any character captured by the channel’s receiver. The receiver 1x
clock is used for the transmitter. This mode returns the received
data back to the sending station one bit time delayed from its
departure. Receiver to host communication is normal. Host to
transmitter communication has no meaning.
In the local loop back mode (used for diagnostic purposes) the
transmitter is internally connected to the receiver input. The
transmitter 1x clock used for the receiver. The RxD input pin is
ignored and the transmitter TxD output pin is held high. This
configuration allows the transmitter to send data to the receiver
without any external parameters to affect the transmission of data.
All status bits, interrupt conditions and processor interface operate
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
The remote loop back mode (also used for diagnostic purposes) is
similar to auto echo except that the characters are not sent to the
local CPU, nor is the receiver status updated. The received data is
sent directly to the transmitter where it is sent out on the TxD output.
The received data is not sent to the receive FIFO and hence the
host will not normally be participating in any diagnostics.
Minor ModesThe minor modes provide additional features within the major
modes. In general the minor modes provide a reduction in the
control burden and a less stringent interrupt latency time for the host
processor. These modes could be invoked in all of the major
modes.. However it may not be reasonable in many situations.
Watch-dog Timer Time–out ModeEach receiver in the Octal UART is equipped with a watch-dog timer
that is enabled by the ”Watch-dog Timer Enable Register (WTER).
The watch-dog ”barks” (times out) if 64 counts of the receiver clock
(64 bit times) elapse with no RxFIFO activity. RxFIFO events are a
read of the RxFIFO or GRxFIFO, or the push of a received character
into the RxFIFO. The timer resets when the (G)RxFIFO is read or if
another character is pushed into the RxFIFO. The receiver
watch-dog timer is included to allow detection of the very last
character(s) of a received message that may be waiting in the
RxFIFO, but are too few in number to successfully initiate an
interrupt. The watch-dog timer is enabled for counting if the
channel’s bit in the Watch Dog Timer Control Register (WDTCR) is
set. Note: a read of the GRxFIFO will reset the watch-dog timer of
only the channel specified in the current interrupt context. Other
watch-dogs are unaffected.
The watch-dog timer may generate an input to the interrupt arbiter if
IMR[6] is set. The status of the Watch-dog timer can be seen as Bit
6 of the Interrupt Status Register, ISR[6]. When a Watch-dog timer
that is programmed to generate an interrupt times out it enters the
arbitration process. It will then only allow receivers to enter the
enter the arbitration. All other sources are bidding sources are
disabled. The receivers arbitrate only amongst themselves.. The
receiver only interrupt mode of the interrupt arbiter continues until
the last watch-dog timer event has been serviced. While in the
receiver only interrupt mode, the control of the interrupt threshold
level is also disabled. The receivers arbitrate only between
themselves. The threshold value is ignored. The receiver with the
most FIFO positions filled will win the bid. Hence the user need not
reduce the bidding threshold level in the ICR to see the interrupt
from a nearly empty RxFIFO that may have caused the watch-dog
time–out.
Note: When any watch-dog times our only the receivers arbitrate.
There is no increase in the probability of receiver being serviced
causing the overrun of another receiver since they will still have
priority based upon received character count.
The interrupt will be cleared automatically upon the push of the next
character received or when the RxFIFO or GRxFIFO is read. The
ICR is unaffected by the watch-dog time–out interrupt and normal
interrupt threshold level sensing resumes after the last watch-dog
timer event has been processed. If other interrupt sources are
active, the IRQN pin may remain low.
Wake Up ModeThe SC28L198 provides two modes of this common asynchronous
associated with address recognition, data handling, receiver enables
and disables. In both modes the meaning of the parity bit is
changed. It is often referred to as the A/D bit or the address/data
bit. It is used to indicate whether the byte presently in the receiver
shift register is an ”address” byte or a ”data” byte. ”1” usually means
address; ”0” data.
Its purpose is to allow several receivers connected to the same data
source to be individually addressed. Of course addressing could be
by group also. Normally the ”Master” would send an address byte to
all receivers ”listening” The receiver would then recognize its
address and enable itself receiving the following data stream. Upon
receipt of an address not its own it would then disable itself. As
descried below appropriate status bits are available to describe the
operation.
Enabling the Wake Up modeThis mode is selected by programming bits MR1[4:3] to ’11’. The
sub modes are controlled by bits 6, 1, 0 in the MR0 register. Bit 6
controls the loading of the address byte to the RxFIFO and MR0[1:0]
determines the sub mode as shown in the following table.
MR0[1:0] = 00 Normal Wake Up Mode (default). Host controls
operation via interrupts and commands written to
the command register (CR).
MR0[1:0] = 01 Auto wake. Enable receiver on address
recognition for this station. Upon recognition of
its assigned address, in the Auto Wake mode,
the local receiver will be enabled and normal
receiver communications with the host will be
established.
MR0[1:0] = 10 Auto Doze. Disable receiver on address
recognition, not for this station. Upon recognition
of an address character that is not its own, in the
Auto Doze mode, the receiver will be disabled
and the address just received either discarded or
pushed to the RxFIFO depending on the
programming of MR0[6].
MR0[1:0] = 11 Auto wake and doze. Both modes above. The
programming of MR0[1:0] to 11 will enable both
the auto wake and auto doze features.
The enabling of the wake–up mode executes a partial enabling
of the receiver state machine. Even though the receiver has
been reset the wake up mode will over ride the disable and
reset condition.
Normal Wake up (The default configuration)In the default configuration for this mode of operation, a ’master’
station transmits an address character followed by data characters
for the addressed ’slave’ station. The slave stations, whose
receivers are normally disabled (not reset), examine the received
data stream and interrupts the CPU (by setting RxRDY) only upon
receipt of an address character. The CPU (host) compares the
received address to its station address and enables the receiver if it
wishes to receive the subsequent data characters. Upon receipt of
another address character, the CPU may disable the receiver to
initiate the process again
. A transmitted character consists of a start bit, the programmed
number of data bits, an address/data (A/D) bit, and the programmed
number of stop bits. The polarity of the transmitted A/D bit is
selected by the CPU by programming bit MR1[2]. MR1[2] = 0
transmits a zero in the A/D bit position which identifies the
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
While in this mode, the receiver continuously looks at the received
data stream, whether it is enabled or disabled. If disabled, it sets
the RxRDY status bit and loads the character into the RxFIFO if the
received A/D bit is a one, but discards the received character if the
received A/D bit is a zero. If the receiver is enabled, all received
characters are transferred to the CPU via the RxFIFO. In either
case, the data bits are loaded into the data FIFO while the A/D bit is
loaded into the status FIFO position normally used for parity error
(SR[5]). Framing error, overrun error, and break detect operate
normally whether or not the receiver is enabled.
Automatic operation, Wake Up & DozeThe automatic configuration for this mode uses on-board
comparators to examine incoming address characters. Each UART
channel may be assigned a unique address character. See the
address register map and the description of the Address
Recognition Character Register (ARCR). The device may be
programmed to automatically awaken a sleeping receiver and/or
disable an active receiver based upon address characters received.
The operation of the basic receiver is the same as described above
for the default mode of wake–up operation except that the CPU
need not be interrupted to make a change in the receiver status.
Three bits in the Mode Register 0, (MR0), control the address
recognition operation. MR0[6] controls the RxFIFO operation of the
received character; MR0[1:0] controls the wake up mode options. If
MR0[6] is set the address character will be pushed onto the
RxFIFO, otherwise the character will be discarded. (The charter is
stripped from the data stream) The MR0[1:0] bits set the options as
follows: A b’00 in this field, the default or power–on condition, puts
the device in the default (CPU controlled) wake up mode of
operation as described above. The auto–wake mode, enabled if
MR0[0] is set, will cause the dedicated comparators to examine
each address character presented by the receiver. If the received
character matches the reference character in ARCR, the receiver
will be enabled and all subsequent characters will be FIFOed until
another address event occurs or the host CPU disables the receiver
explicitly. The auto doze mode, enabled if MR0[1] is set, will
automatically disable the receiver if an address is received that does
not match the reference character in the ARCR.
The UART channel can present the address recognition event to the
interrupt arbiter for IRQN generation. The IRQN generation may be
masked by setting bit 5 of the Interrupt Mask Register, IMR. The bid
level of an address recognition event is controlled by the Bidding
Control Register, BCRA, of the channel.
Note: To ensure proper operation, the host CPU must clear any
pending Address Recognition interrupt before enabling a disabled
receiver operating in the Special or Wake–up mode. This may be
accomplished via the CR commands to clear the Address Interrupt
or by resetting the receiver.
Xon/Xoff Operation
Receiver ModeSince the receiving FIFO resources in the Octal UART are limited,
some means of controlling a remote transmitter is desirable in order
to lessen the probability of receiver overrun. The Octal UART
provides two methods of controlling the data flow. A hardware
assisted means of accomplishing control, the so–called out–of–band
flow control, and an in–band flow control method.
In–band flow control is a protocol for controlling a remote transmitter
by embedding special characters within the message stream, itself.
Two characters, Xon and Xoff, which do not represent normal
printable characters take on flow control definitions when the
Xon/Xoff capability is enabled. Flow control characters received
may be used to gate the channel transmitter on and off. This activity
is referred to as Auto–transmitter mode. To protect the channel
receiver from overrun, fixed fill levels (hardware set at 12
characters) of the RxFIFO may be employed to automatically insert
Xon/Xoff characters in the transmitter’s data stream. This mode of
operation is referred to as auto–receiver mode. Commands issued
by the host CPU via the CR can simulate all these conditions.
Auto–transmitter modeWhen a channel receiver pushes an Xoff character into the RxFIFO,
the channel transmitter will finish transmission of the current
character and then stop transmitting. A transmitter so idled can be
restarted by the receipt of an Xon character by the receiver, or by a
hardware or software reset. The last option results in the loss of the
un–transmitted contents of the TxFIFO. When operating in this
mode the Command Register commands for the transmitter are not
effective.
While idle data may be written to the TxFIFO and it continues to
present its fill level to the interrupt arbiter and maintains the integrity
of its status registers.
Use of ’00’ as an Xon/Xoff character is complicated by the Receiver
break operation which pushes a ’00’ character on the RxFIFO. The
Xon/Xoff character detectors do not discriminate this case from an
Xon/Xoff character received through the RxD pin.
Note: To be recognized as an Xon or Xoff character, the receiver
must have room in the RxFIFO to accommodate the character. An
Xon/Xoff character that is received resulting in a receiver overrun
does not effect the transmitter nor is it pushed into the RxFIFO,
regardless of the state of the Xon/Xoff transparency bit, MR0(7).
Note: Xon /Xoff characters The Xon/Xoff characters with errors will be accepted as valid. The
user has the option sending or not sending these characters to the
FIFO. Error bits associated with Xon/Xoff will be stored normally to
the receiver FIFO.
The channel’s transmitter may be programmed to automatically
transmit an Xoff character without host CPU intervention when the
RxFIFO fill level exceeds a fixed limit (12). In this mode, it will
conversely transmit an Xon character when the RxFIFO level drops
below a second fixed limit (8). A character from the TxFIFO that has
been loaded into the TxD shift register will continue to transmit.
Character(s) in the TxFIFO that have not been popped are
unaffected by the Xon or Xoff transmission. They will be transmitted
after the Xon/Xoff activity concludes.
If the fill level condition that initiates Xon activity negates before the
flow control character can begin transmission, the transmission of
the flow control character will not occur, i.e. either of the following
sequences may be transmitted depending on the timing of the FIFO
level changes with respect to the normal character times:
Character Xoff Xon Character
Character Character
Hardware keeps track of Xoff characters sent that are not rescinded
by an Xon. This logic is reset by writing MR0(3) to ’0’. If the user
drops out of Auto–receiver mode while the XISR shows Xon as the
last character sent, the Xon/Xoff logic will not automatically send the
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
activity of the Xon/Xoff logic is initiated by commands to the CRx
command forces the transmitter to disable exactly as though an Xoff
character had been received by the RxFIFO. The transmitter will
remain disabled until the chip is reset or the CR(7:3) = 10110 (Xoff
resume) command is given. In particular, reception of an Xon or
disabling or re–enabling the transmitter will NOT cause resumption
of transmission. Redundant CRTXon/off commands, i.e. CRTXon
CRTXon, are harmless, although they waste time. A CRTXon may
be used to cancel a CRTXoff (and vice versa), but both may be
transmitted depending on the timing with the transmit state machine.
The kill CRTX command can be used to cleanly terminate any
CRTX commands pending with the minimum impact on the
transmitter.
Note: In no case will an Xon/Xoff character transmission be aborted.
Once the character is loaded into the TX Shift Register, transmission
continues until completion or a chip reset is encountered.
The kill CRTX command has no effect in either of the Auto modes.
Mode controlXon/Xoff mode control is accomplished via the MR0. Bits 3 and 2
reset to zero resulting in all Xon/Xoff processing being disabled. If
MR0[2] is set, the transmitter may be gated by Xon/Xoff characters
received. If MR0[3] is set, the transmitter will transmit Xon and Xoff
when triggered by attainment of fixed fill levels in the channel
RxFIFO. The MR0[7] bit also has an Xon/Xoff function control. If
this bit is set, a received Xon or Xoff character is not pushed into the
RxFIFO. If cleared, the power–on and reset default, the received
Xon or Xoff character is pushed onto the RxFIFO for examination by
the host CPU. The MR0(7) function operates regardless of the
value in MR0(3:2)
Xon/Xoff InterruptsThe Xon/Xoff logic generates interrupts only in response to
recognizing either of the characters in the XonCR or XoffCR (Xon or
Xoff Character Registers). The transmitter activity initiated by the
Xon/Xoff logic or any CR command does not generate an interrupt.
The character comparators operate regardless of the value in
MR0(3:2). Hence the comparators may be used as general purpose
character detectors by setting MR0(3:2)=’00’ and enabling the
Xon/Xoff interrupt in the IMR.
The Octal UART can present the Xon/Xoff recognition event to the
interrupt arbiter for IRQN generation. The IRQN generation may be
masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid
level of an Xon/Xoff recognition event is controlled by the Bidding
Control Register X, BCRX, of the channel. The interrupt status can
be examined in ISR[4]. If cleared, no Xon/Xoff recognition event is
interrupting. If set, an Xon or Xoff recognition event has been
detected. The X Interrupt Status Register, XISR, can be read for
details of the interrupt and to examine other, non–interrupting, status
of the Xon/Xoff logic. Refer to the XISR in the Register
Descriptions.
The character recognition function and the associated interrupt
generation is disabled on hardware or software reset
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
REGISTER DEFINITIONSThe operation of the Octal UART is programmed by writing control
words into the appropriate registers. Operational feedback is
provided via status registers which can be read by the host CPU.
The Octal UART addressing is loosely divided, by the address bit
A(7), into two parts:
1) That part which is concerned with the configuration of the chip
interface and communication modes.
This part controls the elements of host interface setup, interrupt
arbitration, I/O Port Configuration that part of the UART channel
definitions that do not change in normal data handling. This section
is listed in the ”Register Map, Control”.
2) That part concerned with the transmission and reception of the bit
streams.
This part concerns the data status, FIFO fill levels, data error
conditions, channel status, data flow control (hand shaking). This
section is listed in the ”Register Map, Data”.
The Global Configuration Control Register (GCCR) sets the type of
bus cycle, interrupt vector modification and the power up or down
mode.
Table 2. GCCR – Global Configuration Control Register
THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION.ÁÁÁÁÁÁ
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GCCR(7): This bit is reserved for future versions of this device. Ifnot set to zero most internal addressing will be disabled!
GCCR(6): Bus cycle selectionControls the operation of the host interface logic. If reset, the power
on/reset default, the host interface can accommodate arbitrarily long
bus I/O cycles. If the bit is set, the Octal UART expects four Sclk
cycle bus I/O operations similar to those produced by an i80386
processor in non–pipelined mode. The major differences in these
modes are observed in the DACKN pin function. In Sync mode, no
negation of CEN is required between cycles.
GCCR(2:1): Interrupt vector configurationThe IVC field controls if and how the assertion of IACKN (the
interrupt acknowledge pin) will form the interrupt vector for the Octal
UART. If b’00, no vector will be presented during an IACKN cycle.
The bus will be driven high (xFF). If the field contains a b’01, the
contents of the IVR, Interrupt Vector Register, will be presented as
the interrupt vector without modification. If IVC = b’10, the channel
code will replace the 3 LSBs of the IVR; if IVC = b’11 then a modified
interrupt type and channel code replace the 5 LSBs of the IVR.
Note: The modified type field IVR(4:3) is: Receiver w/o error Receiver with error Transmitter All remaining sources
GCCR(0): Power down controlControls the power down function. During power down the internal
oscillator is disabled, interrupt arbitration and all data
transmission/reception activities cease, and all processing for input
change detection, BRG counter/timers and Address/Xon./Xoff
recognition is disabled.
Note: For maximum power savings it is recommended that all
switching inputs be stopped and all input voltage levels be within 0.5
volt of the Vcc and Vss power supply levels.
To switch from the asynchronous to the synchronous bus cycle
mode, a single write operation to the GCCR, terminated by a
negation of the CEN pin, is required. This cycle may be 4 cycles
long if the setup time of the CEN edge to Sclk can be guaranteed.
The host CPU must ensure that a minimum of two Sclk cycles
elapse before the initiation of the next (synchronous) bus cycle(s).
A hardware or software reset is recommended for the unlikely
requirement of returning to the asynchronous bus cycling mode.
MR – Mode RegistersThe user must exercise caution when changing the mode of running
receivers, transmitters or BRG counter/timers. The selected mode
will be activated immediately upon selection, even if this occurs
during the reception or transmission of a character. It is also
possible to disrupt internal controllers by changing modes at critical
times, thus rendering later transmission or reception faulty or
impossible. An exception to this policy is switching from auto–echo
or remote loop back modes to normal mode. If the deselection
occurs just after the receiver has sampled the stop bit (in most
cases indicated by the assertion of the channel’s RxRDY bit) and
the transmitter is enabled, the transmitter will remain in auto–echo
mode until the end of the transmission of the stop bit.
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
Table 3. MR0– Mode Register 0ÁÁÁÁÁÁÁÁ
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* If these bits are not 0 the characters will be stripped regardless of
bits (3:2) or (1:0)
MR0[7:6] – Control the handling of recognized Xon/Xoff or Addresscharacters. If set, the character codes are placed on the RxFIFO
along with their status bits just as ordinary characters are. If the
character is not pushed onto the RxFIFO, its received status will be
lost unless the receiver is operating in the block error mode, see
MR1[5] and the general discussion on receiver error handling.
Interrupt processing is not effected by the setting of these bits. See
Character recognition section.
MR0[5:4] – Controls the fill level at which a transmitter begins topresent its interrupt number to the interrupt arbitration logic. Use of
a low fill level minimizes the number of interrupts generated and
maximizes the number of transmit characters per interrupt cycle. It
also increases the probability that the transmitter will go idle for lack
of characters in the TxFIFO.
MR0[3:2] – Controls the Xon/Xoff processing logic. AutoTransmitter flow control allows the gating of Transmitter activity by
Xon/Xoff characters received by the Channel’s receiver. Auto
Receiver flow control causes the Transmitter to emit an Xoff
character when the RxFIFO has loaded to a depth of 12 characters.
Draining the RxFIFO to a level of 8 or less causes the Transmitter to
emit an Xon character. All transmissions require no host
involvement. A setting other than b’00 in this field precludes the use
of the command register to transmit Xon/Xoff characters.
Note: Interrupt generation in Xon/Xoff processing is controlled by the
IMR (Interrupt Mask Register) of the individual channels. The
interrupt may be cleared by a read of the XISR, the Xon/Xoff
Interrupt Status Register. Receipt of a flow control character will
always generate an interrupt if the IMR is so programmed. The
MR0[3:2] bits have effect on the automatic aspects of flow control
only, not the interrupt generation.
MR0[1:0] – This field controls the operation of the Addressrecognition logic. If the device is not operating in the special or
“wake–up” mode, this hardware may be used as a general purpose
character detector by choosing any combination except b’00.
Interrupt generation is controlled by the channel IMR. The interrupt
may be cleared by a read of the XISR, the Xon/Xoff Interrupt Status
Register. See further description in the section on the Wake Up
mode.
Table 4. MR1 – Mode Register 1ÁÁÁÁ
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MR1[7]: Receiver Request to Send ControlThis bit controls the deactivation of the RTSN output (I/O2) by the
receiver. This output is asserted and negated by commands applied
via the command register. MR1[7] = 1 causes RTSN to be
automatically negated upon receipt of a valid start bit if the receiver
FIFO is
level falls below
members of Philips (Signets)’ UART families where the RTSN
function triggered on FIFO full. This behavior caused problems with
PC UARTs that could not stop transmission at the proper time. .
The RTSN feature can be used to prevent overrun in the receiver, by
This bit controls the readout mode of the Interrupt Status Register,
ISR. If set, the ISR reads the current status masked by the IMR, i.e.
only interrupt sources enabled in the IMR can ever show a ’1’ in the
ISR. If cleared, the ISR shows the current status of the interrupt
source without regard to the Interrupt Mask setting.
MR1[5]: Error Mode SelectThis bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break). In the character mode, status is provided
on a character by character basis; the status applies only to the
character at. the bottom of the FIFO. In the block mode, the status
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
If ’with parity’ or ’force parity’ is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the channel to operate in the
special wake up mode.
MR1[2]: Parity Type SelectThis bit sets the parity type (odd or even) if the ’with parity’ mode is
programmed by MR1[4:3], and the polarity of the forced parity bit if
the ’force parity’ mode is programmed. It has no effect if the ’no
parity’ mode is programmed. In the special ’wake up’ mode, it
selects the polarity of the A/D bit. The parity bit is used to an
address or data byte in the ’wake up’ mode.
MR1[1:0]: Bits per Character SelectThis field selects the number of data bits per character to be
transmitted and received. This number does not include the start,
parity, or stop bits.
Table 5. MR2 – Mode Register 2The MR2 register provides basic channel setup control that may need more frequent updating.
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MR2[7:6] – Mode SelectThe Octal UART can operate in one of four modes: MR2[7:6] = b’00
is the normal mode, with the transmitter and receiver operating
independently.
MR2[7:6] = b’01 places the channel in the automatic echo mode,
which automatically re transmits the received data. The following
conditions are true while in automatic echo mode:
Received data is re–clocked and re–transmitted on the TxD
output.
The receive clock is used for the transmitter.
The receiver must be enabled, but the transmitter need not be
enabled.
The TxRDY and TxEMT status bits are inactive.
The received parity is checked, but is not regenerated for
transmission,
i.e., transmitted parity bit is as received.
Character framing is checked, but the stop bits are re-transmitted
as received.
A received break is echoed as received until the next valid start
bit is detected
. CPU to receiver communication continues normally, but the CPU
to transmitter link is disabled.
Two diagnostic modes can also be selected.
MR2[7:6] = b’10 selects local loop back mode. In this mode:
The transmitter output is internally connected to the receiver
input.
The transmit clock is used for the receiver.
The TxD output is held high.
The RxD input is ignored.
The transmitter must be enabled, but the receiver need not be
enabled.
CPU to transmitter and receiver communications continue
normally.
The second diagnostic mode is the remote loop back mode,
selected by MR2[7:6] = b’11. In this mode:
Received data is re–clocked and re–transmitted on the TxD
The received parity is not checked and is not regenerated for
transmission, i.e., the transmitted parity bit is as received.
The receiver must be enabled, but the transmitter need not be
enabled.
Character framing is not checked, and the stop bits are
re-transmitted as received.
A received break is echoed as received until the next valid start
bit is detected.
MR2[5] – Transmitter Request to Send ControlThis bit controls the deactivation of the RTSN output (I/O2) by the
transmitter. This output is manually asserted and negated by
appropriate commands issued via the command register. MR2[5] =
1 causes RTSN to be reset automatically one bit time after the
characters in the transmit shift register and in the TxFIFO (if any)
are completely transmitted (includes the programmed number of
stop bits if the transmitter is not enabled). This feature can be used
to automatically terminate the transmission of a message as follows:
Program auto reset mode: MR2[5]= 1.
Enable transmitter.
Assert RTSN via command.
Send message.
After the last character of the message is loaded to the TxFIFO,
disable the transmitter. Before disabling the transmitter be sure
the Status Register TxEMT bit is NOT set (i.e., the transmitter is
not underrun). The underrun condition is indicated by the
TxEMT bit in the SR being set. The condition occurs
immediately upon enabling the transmitter and persists until a
character is loaded to the TxFIFO. The Underrun condition will
not be a problem as long as the controlling processor keeps up
with the transmitter data flow. The proper operation of this
feature assumes that the transmitter is busy (not underrun) when
the disable is issued.
The last character will be transmitted and RTSN will be reset one
bit time after the last stop bit.
NOTE: When the transmitter controls the RTSN pin, the meaning of
the pin is COMPLETELY changed. It has nothing to do with the
normal RTSN/CTSN “handshaking”. It is usually used to mean “end
of message” and to “turn the line around” in simplex
communications.
MR2[4] – Clear to Send Control
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
asserted (low), the character is transmitted. If it is negated (high),
the TxD output remains in the marking state and the transmission is
delayed until CTSN goes low. Changes in CTSN, while a character
is being transmitted, do not affect the transmission of that character.
This feature can be used to prevent overrun of a remote receiver.
MR2[3:2] – RxINT control fieldControls when interrupt arbitration for a receiver begins based on
RxFIFO fill level. This field allows interrupt arbitration to begin when
the RxFIFO is full, 3/4 full, 1/2 full or when it contains at least 1
character.
MR2[1:0] – Stop Bit Length SelectThis field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16, 1, 1.5 and 2 bits can
be programmed for character lengths of 6, 7, and 8 bits. For a
character length of 5 bits, 1, 1.5 and 2 stop bits can be programmed.
In all cases, the receiver only checks for a mark condition at the
center of the first stop bit position (one bit time after the last data bit,
or after the parity bit if parity is enabled). If an external 1X clock is
used for the transmitter, MR2[1] = 0 selects one stop bit and MR2[1]
= 1 selects two stop bits to be transmitted.
Table 6. RxCSR and TxCSR – Receiver and Transmitter Clock Select RegistersBoth registers consist of single 5 bit field that selects the clock source for the receiver and transmitter, respectively. The unused bits in this
register read b’111. The baud rates shown in the table below are based on the x1 crystal frequency of 3.6864MHz. The baud rates shown
below will vary as the X1 crystal clock varies. For example, if the X1 rate is changed to 7.3728 MHz all the rates below will double.
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Table 7. Data Clock MuxCCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.
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Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
Table 8. CR – Command RegisterCR is used to write commands to the Octal UART.
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CR[2] – Lock TxD and RxFIFO enablesIf set, the transmitter and receiver enable bits, CR[1:0] are not
significant. The enabled/disabled state of a receiver or transmitter
can be changed only if this bit is at zero during the time of the write
to the command register. WRITES TO THE UPPER BITS OF THE
CR WOULD USUALLY HAVE CR[2] AT 1 to maintain the conditionof the receiver and transmitter. The bit provides a mechanism for
writing commands to a channel, via CR[7:3], without the necessity of
keeping track of or reading the current enable status of the receiver
and transmitter.
CR[1] – Enable TransmitterA one written to this bit enables operation of the transmitter. The
TxRDY status bit will be asserted. When disabled by writing a zero
to this bit, the command terminates transmitter operation and resets
the TxRDY and TxEMT status bits. However, if a character is being
transmitted or if characters are loaded in the TxFIFO when the
transmitter is disabled, the transmission of the all character(s) is
completed before assuming the inactive state.
CR[0] – Enable ReceiverA one written to this bit enables operation of the receiver. If not in
the special wake up mode, this also forces the receiver into the
search for start bit state. If a zero is written, this command
terminates operation of the receiver immediately – a character being
received will be lost. The command has no effect on the receiver
status bits or any other control registers. If the special wake–up
mode is programmed, the receiver operates even if it is disabled
(see Wake–up Mode).
CR[7:3] – Miscellaneous Commands ( See Table below)The encoded value of this field can be used to specify a single
command as follows:
00000 No command.
00001 Reserved
00010 Reset receiver. Resets the receiver as if a hardware reset
had been applied. The receiver is disabled and the FIFO
pointer is reset to the first location effectively discarding all
unread characters in the FIFO.
00011 Reset transmitter. Resets the transmitter as if a hardware
reset had been applied.
00100 Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register
(SR[7:4]). Used in character mode to clear overrun error
status (although RB, PE and FE bits will also be cleared),
and in block mode to clear all error status after a block of
data has been received.
00101 Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be
cleared to zero.
00110 Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will be
be true before break begins). The transmitter must be
enabled to start a break.
00111 Stop break. The TxD line will go high (marking) within two
bit times. TxD will remain high for one bit time before the
next character, if any, is transmitted.
01000 Assert RTSN. Causes the RTSN output to be asserted
(low).
01001 Negate RTSN. Causes the RTSN output to be negated
(high).
Note: The two commands above actually reset and
set, respectively, the I/O2 or I/O1 pin associated with
the I/OPIOR register.01010 Reserved
01011 Reserved
01100 Reserved
01101 Block error status mode. Upon reset of the device or an
individual receiver, the block mode of receiver error status
accumulates as each character moves to the bottom of
the RxFIFO, the position from which it will be read. In this
mode of operation, the RxFIFO may contain a character
with non–zero error status for some time. The status will
not reflect the error character’s presence until it is ready to
be popped from the RxFIFO. Command 01101 allows the
error status to be updated as each character is pushed
into the RxFIFO. This allows the earliest detection of a
problem character, but complicates the determination of
exactly which character is causing the error. This mode of
block error accumulation may be exited only by resetting
the chip or the individual receiver.
01111 Reserved.
10000 Transmit an Xon Character
10001 Transmit an Xoff Character
10010 Reserved for channels b–h, for channel a: enables a
Gang Write of Xon Character Registers. After this
command is issued, a write to the channel A Xon
Character Register will result in a write to all channel’s
Xon character registers. This command provides a
mechanism to initialize all the Xon Character registers
with one write. A write to channel A Xon Character
Register returns the Octal UART to the individual Xon
write mode.
10011 Reserved for channels b–h, for channel a: enables Gang
Write of Xoff Character Registers. After this command is
issued, a write to the channel A Xoff Character Register
will result in a write to all channel’s Xoff character
registers. This command provides a mechanism to
initialize all the Xoff Character registers with one write. A
write to channel A Xoff Character Register returns the
Octal UART to the individual Xoff write mode.
Note: Gang writing of Xon/Xoff Character Commands: Issuing
command causes the next write to Xon/Xoff Character Register
A to effect a simultaneous write into the other 3 Xon/Xoff
character registers. After the Xon/Xoff Character Register A is
written, the 28L198 returns to individual write mode for the
Xon/Xoff Character Registers. Other intervening reads and
writes are ignored. The device resets to individual write mode.10100 Reserved for channels b-h, for channel a: executes a Gang
Load of Xon Character Registers. Executing this
command causes a write of the value x’11 to all channel’s
Xon character registers. This command provides a
mechanism to initialize all the Xon Character registers to a
default value with one write. Execution of this command
is immediate and does not effect the timing of subsequent
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
mechanism to initialize all the Xoff Character registers to a
default value with one write. Execution of this command
is immediate and does not effect the timing of subsequent
host I/O operations.
10110 Xoff resume command (CRXoffre; not active in
“Auto-Transmit Mode”). A command to cancel a previous
Host Xoff command. Upon receipt, the channel’s
transmitter will transfer a character, if any, from the
TxFIFO and begin transmission.
10111 Host Xoff command (CRXoff). This command allows tight
host CPU control of the flow control of the channel
transmitter. When interrupted for receipt of an Xoff
character by the receiver, the host may stop transmission
of further characters by the channel transmitter by issuing
the Host Xoff command. Any character that has been
transferred to the TxD shift register will complete its
transmission, including the stop bit.
11000 Cancel Host transmit flow control command. Issuing this
command will cancel a previous transmit command if the
flow control character is not yet loaded into the TxD Shift
Register. If there is no character waiting for transmission
or if its transmission has already begun, then this
command has no effect.
Reserved
11011 Reset Address Recognition Status. This command clears the
interrupt status that was set when an address character
was recognized by a disabled receiver operating in the
special mode.
Reserved
11110 Resets all UART channel registers. This command
provides a means to zero all the UART channels that are
not reset to x’00 by a reset command or a hardware reset.
11111 Reserved for channels b-h, for channel a: executes a chip
wide reset. Executing this command in channel a is
equivalent to a hardware reset with the RESETN pin.
Executing in channel b-h, has no effect.
Table 9. Command Register CodeCommands x’12, x13, x’14, x’15, x’1f (marked with*) are global and exist only in channel A’s register space.
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Table 10. SR – Channel Status RegisterÁÁÁÁÁ
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SR[7] – Received BreakThis bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received; further entries to the
FIFO are inhibited until the RxD line returns to the marking state for
at least one half bit time (two successive edges of the internal or
received character. However, if a break begins in the middle of a
character, it must last until the end of the next character in order for
it to be detected.
SR[6] – Framing Error (FE)This bit, when set, indicates that a stop bit was not detected when
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
This bit is set when the ’with parity’ or ’force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity. In the special ’wake up mode’, the
parity error bit stores the received A/D bit.
SR[4] – Overrun Error (OE)This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the RxFIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost. This bit is
cleared by a reset error status command.
SR[3] – Transmitter Empty (TxEMT)This bit is set when the transmitter underruns, i.e., both the TxFIFO
and the transmit shift register are empty.
It is set after transmission of the last stop bit of a character, if no
character is in the TxFIFO awaiting transmission. It is reset when
the TxFIFO is loaded by the CPU, or when the transmitter is
disabled.
SR[2] – Transmitter Ready (TxRDY)This bit, when set, indicates that the TxFIFO is ready to be loaded
with a character. This bit is cleared when the TxFIFO is loaded by
the CPU and is set when the last character is transferred to the
transmit shift register. TxRDY is reset when the transmitter is
disabled and is set when the transmitter is first enabled, e.g.,
characters loaded in the TxFIFO while the transmitter is disabled will
not be transmitted.
SR[1] – RxFIFO Full (RxFULL)This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all sixteen RxFIFO positions are occupied. It is
reset when the CPU reads the RxFIFO and that read leaves one
empty byte position. If a character is waiting in the receive shift
register because the RxFIFO is full, RxFULL is not reset until the
second read of the RxFIFO since the waiting character is
immediately loaded to the RxFIFO.
SR[0] – Receiver Ready (RxRDY)This bit indicates that a character has been received and is waiting
in the RxFIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the RxFIFO and reset
when the CPU reads the RxFIFO, and no more characters are in the
RxFIFO.
Table 11. ISR – Interrupt Status RegisterÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
This register provides the status of all potential interrupt sources for
a UART channel. When generating an interrupt arbitration value,
the contents of this register are masked by the interrupt mask
register (IMR). If a bit in the ISR is a ’1’ and the corresponding bit in
the IMR is also a ’1’, interrupt arbitration for this source will begin. If
the corresponding bit in the IMR is a zero, the state of the bit in the
ISR can have no affect on the IRQN output. Note that the IMR may
or may not mask the reading of the ISR as determined by MR1[6].
If MR1[6] is cleared, the reset and power on default, the ISR is read
without modification. If MR1[6] is set, the a read of the ISR gives a
value of the ISR ANDed with the IMR.
ISR[7] – Input Change of StateThis bit is set when a change of state occurs at the I/O1 or I/O0
input pins. It is reset when the CPU reads the Input Port Register,
IPR.
ISR[6] Watch-dog Time–outThis bit is set when the receiver’s watch-dog timer has counted
more than 64 bit times since the last RxFIFO event. RxFIFO events
are a read of the RxFIFO or GRxFIFO, or the push of a received
character into the FIFO. The interrupt will be cleared automatically
upon the push of the next character received or when the RxFIFO or
GRxFIFO is read. The receiver watch-dog timer is included to allow
detection of the very last characters of a received message that may
be waiting in the RxFIFO, but are too few in number to successfully
initiate an interrupt. Refer to the watch-dog timer description for
details of how the interrupt system works after a watch-dog
time–out.
is negated by a write to the CR with command x11011, Reset
Address Recognition Status.
ISR[4] – Xon/Xoff Status ChangeThis bit is set when an Xon/Xoff character being received from an
external source. The bit is negated by a read of the channel Xon
Interrupt Status Register, XISR.
ISR[3] – Reserved Always reads a 0
ISR[2] – Change in Channel Break StatusThis bit, when set, indicates that the receiver has detected the
beginning or the end of a received break. It is reset when the CPU
issues a reset break change interrupt command via the CR.
ISR[1] – Receiver ReadyThe general function of this bit is to indicate that the RxFIFO has
data available. The particular meaning of this bit is programmed by
MR2[3:2]. If programmed as receiver ready(MR2[3:2] = 00), it
indicates that at least one character has been received and is
waiting in the RxFIFO to be read by the host CPU. It is set when the
character is transferred from the receive shift register to the RxFIFO
and reset when the CPU reads the last character from the RxFIFO.
If MR2[3:2] is programmed as FIFO full, ISR[1] is set when a
character is transferred from the receive holding register to the
RxFIFO and the transfer causes the RxFIFO to become full, i.e. all
sixteen FIFO positions are occupied. It is reset when ever RxFIFO
is not full. If there is a character waiting in the receive shift register
because the FIFO is full, the bit is set again when the waiting
character is transferred into the FIFO.
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
Note: This bit must be at a one (1) for the receiver to enter the
arbitration process. It is the fact that this bit is zero (0) when the
RxFIFO is empty that stops an empty FIFO from entering the
interrupt arbitration. Also note that the meaning if this bit is not quite
the same as the similar bit in the status register (SR).
ISR[0] – Transmitter ReadyThe general function of this bit is to indicate that the TxFIFO has an
at least one empty space for data. The particular meaning of the bit
is controlled by MR0[5:4] indicates the TxFIFO may be loaded with
one or more characters. If MR0[5:4] = 00 (the default condition) this
bit will not set until the TxFIFO is empty – sixteen bytes available. If
the fill level of the TxFIFO is below the trigger level programmed by
the TxINT field of the Mode Register 0, this bit will be set. A one in
this position indicates that at least one character can be sent to the
TxFIFO. It is turned off as the TxFIFO is filled above the level
programmed by MR0[5:4. This bit turns on as the FIFO empties; the
RxFIFO bit turns on as the FIFO fills. This often a point of confusion
in programming interrupt functions for the receiver and transmitter
FIFOs.
Note: This bit must be at a one (1) for the transmitter to enter the
arbitration process. It is the fact that this bit is zero (0) when the
RxFIFO is full that stops a full FIFO from entering the interrupt
arbitration. Also note that the meaning if this bit is not quite the
same as the similar bit in the status register (SR).
Table 12. IMR – Interrupt Mask RegisterÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
The programming of this register selects which bits in the ISR cause
an interrupt output. If a bit in the ISR is a ’1’ and the corresponding
bit in the IMR is a ’1’, the interrupt source is presented to the internal
interrupt arbitration circuits, eventually resulting in the IRQN output
being asserted (low). If the corresponding bit in the IMR is a zero,
the state of the bit in the ISR has no affect on the IRQN output.
IMR[7] – Controls if a change of state in the inputs equipped withinput change detectors will cause an interrupt.
IMR[6] – Controls the generation of an interrupt by the watch-dogtimer event. If set, a count of 64 idle bit times in the receiver will
begin interrupt arbitration.
IMR[5] – Enables the generation of an interrupt in response tochanges in the Address Recognition circuitry of the Special Mode
(multi-drop or wake–up mode).
IMR[4] – Enables the generation of an interrupt in response torecognition of an in–band flow control character.
IMR[3] – Reserved
IMR[2] – Enables the generation of an interrupt when a Breakcondition has been detected by the channel receiver.
IMR[1] – Enables the generation of an interrupt when servicing forthe RxFIFO is desired.
IMR[0] – Enables the generation of an interrupt when servicing forthe TxFIFO is desired.
Table 13. RxFIFO Receiver FIFOÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
The FIFO for the receiver is 11 bits wide and 16 ”words” deep. The
status of each byte received is stored with that byte and is moved
along with the byte as the characters are read from the FIFO. The
upper three bits are presented in the STATUS register and they
change in the status register each time a data byte is read from the
FIFO. Therefor the status register should be read BEFORE the byte
is read from the RxFIFO if one wishes to ascertain the quality of the
byte
The forgoing applies to the ”character error” mode of status
reporting. See MR1[5] and ”RxFIFO Status” descriptions for ”block
error” status reporting. Briefly ”Block Error” gives the accumulated
error of all bytes received in the RxFIFO since the last “Reset Error”
command was issued. (CR = x’04)
Table 14. TxFIFO – Transmitter FIFOÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 15. BCRBRK – Bidding Control Register –
Break ChangeÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
This register provides the 3 MSBs of the Interrupt Arbitration number
for a break change interrupt.
Table 16. BCRCOS – Bidding Control Register –
Change of StateÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
This register provides the 3 MSBs of the Interrupt Arbitration number
for a Change of State, COS, interrupt.
Table 17. BCRx – Bidding Control Register – XonÁÁÁÁÁÁÁ
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
Table 18. BCRA – Bidding Control Register –
AddressÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
This register provides the 3 MSBs of the Interrupt Arbitration number
for an address recognition event interrupt.
Table 19. XonCR – Xon Character RegisterÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
An 8 bit character register that contains the compare value for an
Xon character.
Table 20. XoffCR – Xoff Character RegisterÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
An 8 bit character register that contains the compare value for an
Xoff character.
Table 21. ARCR – Address Recognition Character
RegisterÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
An 8 bit character register that contains the compare value for the
wake–up address character
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
Table 22. XISR – Xon–Xoff Interrupt Status RegisterÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
XISR[7:6] – Received X Character Status. This field can be read todetermine if the receiver has encountered an Xon or Xoff character
in the incoming data stream. These bits are maintained until a read
of the XISR. The field is updated by X character reception
regardless of the state of MR0(7, 3:2) or IMR(4). The field can
therefore be used as a character detector for the bit patterns stored
in the Xon and Xoff Character Registers.
XISR[5:4] – Automatic transmission Status. This field indicates thelast flow control character sent in the Auto Receiver flow control
mode. If Auto Receiver mode has not been enabled, this field will
always read b’00. It will likewise reset to b’00 if MR0(3) is reset. If
the Auto Receiver mode is exited while this field reads b’10, it is the
user’s responsibility to transmit an Xon, when appropriate.
XISR[3:2] – TxD flow Status. This field tracks the transmitter’s flowstatus as follows:
00 – normal. The flow control is under host control.
01 – TxD halt pending. After the current character finishes the
transmitter will stop. The status will then change to b’00.
10 – re–enabled. The transmitter had been halted and restarted.
It is sending data characters. After a read of the XISR, it will
return to ”normal” status.
11 – disabled. The transmitter is flow controlled.
XISR[1:0] – TxD character Status. This field allows determination ofthe type of character being transmitted. If XISR(1:0) is b’01, the
channel is waiting for a data character to transfer from the TxFIFO.
This condition will only occur for a bit time after an Xon or Xoff
character transmission unless the TxFIFO is empty.
Table 23. WDTRCR – Watch-dog Timer Enable
RegisterÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
This register enables the watch-dog Timer for each of the 8
receivers on the Octal UART.
Table 24. BRGTRU – BRG Timer Reload
Registers, UpperÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This is the upper byte of the 16 bit value used by the BRG timer in
generating a baud rate clock
Table 25. BRGTRL – BRG Timer Reload
Registers, LowerÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This is the lower byte of the 16 bit value used by the BRG timer in
generating a baud rate clock.
Table 26. BRGTCR – BRG Timer Control Register (BRGTCR)ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Start/Stop control and clock select register for the two BRG
counters. The clock selection is for the input to the counters. It is
that clock divided by the number represented by the BRGTU and
BRGTL the will be used as the 16x clock for the receivers and
transmitters. When the BRG timer Clock is selected for the
receiver(s) or transmitter(s) the receivers and transmitters will
consider it as a 16x clock and further device it by 16. In other words
the receivers and transmitters will always be in the 16x ode of
operation when the internal BRG timer is selected for their clock.
Philips Semiconductors Product specification
SC28L198Octal UART for 3.3V and 5V supply voltage
Table 27. ICR – Interrupt Control RegisterÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This register provides a single 7 bit field called the interrupt
threshold for use by the interrupt arbiter. The field is interpreted as a
single unsigned integer. The interrupt arbiter will not generate an
external interrupt request, by asserting IRQN, unless the value of
the highest priority interrupt exceeds the value of the interrupt
threshold. If the highest bidder in the interrupt arbitration is lower
than the threshold level set by the ICR, the Current Interrupt
Register, CIR, will contain x’00. Refer to the functional description of
interrupt generation for details on how the various interrupt source
bid values are calculated.
Note: While a watch-dog Timer interrupt is pending, the ICR is not
used and only receiver codes are presented for interrupt arbitration.
This allows receivers with very low count values (perhaps below the
threshold value) to win interrupt arbitration without requiring the user
to explicitly lower the threshold level in the ICR. These bits are the
upper seven (7) bits of the interrupt arbitration system. The lower
three (3) bits represent the channel number.
UCIR – Update CIRA command based upon a decode of address x’8C. ( UCIR is not a
register!) A write (the write data is not important; a “don’t care”) to
this ’register’ causes the Current Interrupt Register to be updated
with the value that is winning interrupt arbitration. The register
would be used in systems that poll the interrupt status registers
rather than wait for interrupts. Alternatively, the CIR is normally
updated during an Interrupt Acknowledge Bus cycle in interrupt
driven systems.
Table 28. CIR – Current Interrupt RegisterÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
The Current Interrupt Register is provided to speed up the
the current interrupt information remains frozen in the CIR until
another IACKN cycle or Update CIR command occurs. The LSBs of
the CIR provide part of the addressing for various Global Interrupt
registers including the GIBCR, GICR, GITR and the Global RxFIFO
and TxFIFO FIFO. The host CPU need not generate individual
addresses for this information since the interrupt context will remain
stable at the fixed addresses of the Global Interrupt registers until
the CIR is updated. For most interrupting sources, the data
available in the CIR alone will be sufficient to set up a service
routine.
The CIR may be processed as follows:
If CIR[7] = 1, then a receiver interrupt is pending and the count is
CIR[5:3], channel is CIR[2:0]
Else If CIR[6] = 1 then a transmitter interrupt is pending and the
count is CIR[5:3], channel is CIR[2:0]
Else the interrupt is another type, specified in CIR[5:3]
Note: The GIBCR, Global Interrupting Byte Count Register, may be
read to determine an exact character count if 9 or less characters
are indicated in the count field of the CIR.
Table 29. IVR – Interrupt Vector RegisterÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
The IVR contains the byte that will be placed on the data bus during
an IACKN cycle when the GCCR bits (2:1) are set to binary ‘01’.
This is the unmodified form of the interrupt vector.
Table 30. Modification of the IVR ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
The table above indicates how the IVR may be modified by the
interrupting source. The modification of the IVR as it is presented to
the data bus during an IACK cycle is controlled by the setting of the
bits (2:1) in the GCCR (Global Chip Configuration Register)
Table 31. GICR – Global Interrupting Channel
RegisterÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
