SC26C92C1A ,Dual universal asynchronous receiver/transmitter DUARTPIN CONFIGURATIONSINDEXA0 1 40VCCCORNER61 40IP3 2 39 IP444347 39A1 3 38 IP5133IP1 4 37 IP6A2 5 36 I ..
SC26C92C1B ,Dual universal asynchronous receiver/transmitter (DUART)features and deeper FIFOs. Its– 27 fixed rates: 50 to 230.4k baudconfiguration on power up is that ..
SC26C92C1N ,Dual universal asynchronous receiver/transmitter (DUART)INTEGRATED CIRCUITSSC26C92Dual universal asynchronousreceiver/transmitter (DUART)Product specifica ..
SC26C92C1N ,Dual universal asynchronous receiver/transmitter (DUART)applications• 8 character FIFOs for each receiver and transmitter• Start-end break interrupt/status ..
SC26C94C1A ,Quad universal asynchronous receiver/transmitter QUART
SC26C94C1A ,Quad universal asynchronous receiver/transmitter QUART
SDMG0340LA-7 , SURFACE MOUNT SCHOTTKY BARRIER DIODE
SDMG0340LC-7-F , SURFACE MOUNT SCHOTTKY BARRIER DIODE
SDMP0340LCT-7 , SURFACE MOUNT SCHOTTKY BARRIER DIODE
SDMP0340LCT-7-F , SURFACE MOUNT SCHOTTKY BARRIER DIODE
SDMP0340LST-7-F , SURFACE MOUNT SCHOTTKY BARRIER DIODE
SDMP0340LT , SURFACE MOUNT SCHOTTKY BARRIER DIODE
SC26C92C1A-SC26C92C1B-SC26C92C1N
Dual universal asynchronous receiver/transmitter (DUART)
Product specification
Supersedes data of 1998 Nov 09
IC19 Data Handbook
2000 Jan 31
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
DESCRIPTIONThe SC26C92 is a pin and function replacement for the SCC2692
and SCN2681 with added features and deeper FIFOs. Its
configuration on power up is that of the 2692. Its differences from
the 2692 are: 8 character receiver, 8 character transmit FIFOs,
watch dog timer for each receiver, mode register 0 is added,
extended baud rate and overall faster speeds, programmable
receiver and transmitter interrupts. (The SCC2692 is not being
discontinued.)
The Philips Semiconductors SC26C92 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
CMOS-LSI communications device that provides two full-duplex
asynchronous receiver/transmitter channels in a single package. It
interfaces directly with microprocessors and may be used in a polled
or interrupt driven system and provides modem and DMA interface.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of 27 fixed baud
rates, a 16X clock derived from a programmable counter/timer, or an
external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver and transmitter is buffered by eight character FIFOs
to minimize the potential of receiver overrun, transmitter underrun
and to reduce interrupt overhead in interrupt driven systems. In
addition, a flow control capability is provided via RTS/CTS signaling
to disable a remote transmitter when the receiver buffer is full.
Also provided on the SC26C92 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
The SC26C92 is available in three package versions: 40-pin 0.6”
wide DIP , a 44-pin PLCC and 44–pin plastic quad flat pack (PQFP).
FEATURES Dual full-duplex independent asynchronous receiver/transmitters 8 character FIFOs for each receiver and transmitter Programmable data format
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16-bit increments 16-bit programmable Counter/Timer Programmable baud rate for each receiver and transmitter
selectable from:
27 fixed rates: 50 to 230.4k baud
Other baud rates to 230.4k baud at 16X
Programmable user-defined rates derived from a
programmable counter/timer
External 1X or 16X clock Parity, framing, and overrun error detection False start bit detection Line break detection and generation Programmable channel mode
Normal (full-duplex)
Automatic echo
Local loopback
Remote loopback
Multidrop mode (also called ‘wake-up’ or ‘9-bit’) Multi-function 7-bit input port
Can serve as clock, modem, or control inputs
Change of state detection on four inputs
Inputs have typically >100k pull-up resistors Multi-function 8-bit output port
Individual bit set/reset capability
Outputs can be programmed to be status/interrupt signals
FIFO states for DMA and modem interface Versatile interrupt system
Single interrupt output with eight maskable interrupting
conditions
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
Each FIFO can be programmed for four different interrupt levels
Watch dog timer for each receiver Maximum data transfer rates:
1X – 1Mb/sec, 16X – 1Mb/sec Automatic wake-up mode for multidrop applications Start-end break interrupt/status Detects break which originates in the middle of a character On-chip crystal oscillator Power down mode Receiver timeout mode Single +5V power supply Powers up to emulate SCC2692
ORDERING INFORMATION
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
NOTE: Commercial devices are tested for the –40 to +85�C.
PIN CONFIGURATIONS
Figure 1. Pin Configurations
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
BLOCK DIAGRAM
Figure 2. Block Diagram
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
PIN DESCRIPTION
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
ABSOLUTE MAXIMUM RATINGS1
NOTES: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. Parameters are valid over specified temperature range.
DC ELECTRICAL CHARACTERISTICS1, 2 VCC = 5V ± 10%, TA = –40�C to 85�C, unless otherwise specified.
NOTES: Parameters are valid over specified temperature range. Typical values are at +25°C, typical supply voltages, and typical processing parameters. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7KΩ to VCC. All outputs are disconnected. Inputs are switching between CMOS levels of VCC -0.2V and VSS + 0.2V. See UART application note for power down currents of 5μA or less.
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
AC CHARACTERISTICS1, 2, 4VCC = 5V ± 10%, TA = –40�C to 85�C, unless otherwise specified.
NOTES: Parameters are valid over specified temperature range. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate. Typical values are at +25°C, typical supply voltages, and typical processing parameters. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7KΩ to VCC. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
Block DiagramThe SC26C92 DUART consists of the following eight major sections:
data bus buffer, operation control, interrupt control, timing,
communications Channels A and B, input port and output port.
Refer to the Block Diagram.
Data Bus BufferThe data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
allow read and write operations to take place between the controlling
CPU and the DUART.
Operation ControlThe operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus.
Interrupt ControlA single active-Low interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR). The IMR can be
programmed to select only certain conditions to cause INTRN to be
asserted. The ISR can be read by the CPU to determine all
currently active interrupting conditions.
Outputs OP3-OP7 can be programmed to provide discrete interrupt
outputs for the transmitter, receivers, and counter/timer.
When OP3 to OP7 are programmed as interrupts, their output
buffers are changed to the open drain active low configuration.
These pins may be used for DMA and modem control.
TIMING CIRCUITS
Crystal ClockThe timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and four clock
selectors. The crystal oscillator operates directly from a crystal
connected across the X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may be connected to
X1/CLK. The clock serves as the basic timing reference for the
Baud Rate Generator (BRG), the counter/timer, and other internal
circuits. A clock signal within the limits specified in the
specifications section of this data sheet must always be supplied to
the DUART.
If an external is used instead of a crystal, X1 should be driven using
a configuration similar to the one in Figure 7.
BRGThe baud rate generator operates from the oscillator or external
clock input and is capable of generating 27 commonly used data
communications baud rates ranging from 50 to 38.4K baud.
Programming bit 0 of MR0 to a “1” gives additional baud rates to
230.4kB. These will be in the 16X mode. A 3.6864MHz crystal or
external clock must be used to get the standard baud rates. The
clock outputs from the BRG are at 16X the actual baud rate. The
counter/timer can be used as a timer to produce a 16X clock for any
other baud rate by counting down the crystal clock or an external
Counter–TimerThe Counter/Timer is a programmable 16–bit divider that is used for
generating miscellaneous clocks or generating timeout periods.
These clocks may be used by any or all of the receivers and trans-
mitters in the DUART or may be directed to an I/O pin for miscella-
neous use.
Counter/Timer programmingThe counter timer is a 16–bit programmable divider that operates in
one of three modes: counter, timer, and time out. Timer mode generates a square wave. Counter mode generates a time delay. Time out mode counts time between received characters.
The C/T uses the numbers loaded into the Counter/Timer Lower
Register (CTPL) and the Counter/Timer Upper Register (CTPU) as
its divisor. The counter timer is controlled with six commands: Start/
Stop C/T, Read/Write Counter/Timer lower register and Read/Write
Counter/Timer upper register. These commands have slight differ-
ences depending on the mode of operation. Please see the detail of
the commands under the CTPL/CTPU register descriptions.
Baud Rate Generation with the C/TWhen the timer is selected as baud rates for receiver or transmitter
via the Clock Select register their output will be configured as a 16x
clock. Therefore one needs to program the timer to generate a
clock 16 times faster than the data rate. The formula for calculating
’n’, the number loaded to the CTPU and CTPL registers, based on a
particular input clock frequency is shown below.
For the timer mode the formula is as follows: Clockinputfrequency 16� Baudratedesired
NOTE: ‘n’ may not assume values of 0 and 1.The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and receiv-
er state machines include divide by 16 circuits, which provide the
final frequency and provide various timing edges used in the qualify-
ing the serial data bit stream. Often this division will result in a non–
integer value: 26.3 for example. One may only program integer
numbers to a digital divider. There for 26 would be chosen. If 26.7
were the result of the division then 27 would be chosen. This gives
a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage
error of 1.14% or 1.12% respectively, well within the ability of the
asynchronous mode of operation. Higher input frequency to the
counter reduces the error effect of the fractional division
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is com-
municating may also have a small error in the precise baud rate. In
a ”clean” communications environment using one start bit, eight data
bits and one stop bit the total difference allowed between the trans-
mitter and receiver frequency is approximately 4.6%. Less than
eight data bits will increase this percentage.
Communications Channels A and B
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
operating frequency for each receiver and transmitter can be
selected independently from the baud rate generator, the
counter/timer, or from an external input.
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD
output pin.
The receiver accepts serial data on the RxD pin, converts this serial
input to parallel format, checks for start bit, stop bit, parity bit (if any),
or break condition and sends an assembled character to the CPU
via the receive FIFO. Three status bits (Break Received, Framing
and Parity Errors) are also FIFOed with each data character.
Input PortThe inputs to this unlatched 7-bit port can be read by the CPU by
performing a read operation at address H’D’. A High input results in
a logic 1 while a Low input results in a logic 0. D7 will always read
as a logic 1. The pins of this port can also serve as auxiliary inputs
to certain portions of the DUART logic or modem and DMA control.
Four change-of-state detectors are provided which are associated
with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High
transition of these inputs, lasting longer than 25 - 50μs, will set the
corresponding bit in the input port change register. The bits are
cleared when the register is read by the CPU. Any change-of-state
can also be programmed to generate an interrupt to the CPU.
The input port pulse detection circuitry uses a 38.4KHz sampling
clock derived from one of the baud rate generator taps. This results
in a sampling period of slightly more than 25μs (this assumes that
the clock input is 3.6864MHz). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples at the new logic level be observed. As a
consequence, the minimum duration of the signal change is 25μs if
the transition occurs “coincident with the first sample pulse”. The
50μs time refers to the situation in which the change-of-state is “just
missed” and the first change-of-state is not detected until 25μs later.
All the IP pins have a small pull-up device that will source 1 to 4 �A
of current from VCC. These pins do not require pull-up devices or
VCC connections if they are not used.
Output PortThe output ports are controlled from five places: the OPCR register,
SOPR, ROPR, the MR registers and the command register (CR).
The OPCR register controls the source of the data for the output
ports OP2 through OP7. The data source for output ports OP0 and
OP1 is controlled by the MR and CR registers. Normally the data
source for the OP pins is from the OPR register. The OP pin drive
the inverted level (complement) of the OPR register. Example:
when the SOPR is used to set the OPR bit to a logical 1 then the
associated OP pin will drive a logical 0.
The content of the OPR register is controlled by the “Set Output Port
Bits Command” and the “Reset Output Bits Command”. These com-
mands are at E and F, respectively. When these commands are
used, action takes place only at the bit locations where ones exist.
For example, a one in bit location 5 of the data word used with the
“Set Output Port Bits” command will result in OPR(5) being set to
one. The OP5 would then be set to zero (VSS ). Similarly, a one in
bit position 5 of the data word associated with the “Reset Output
Ports Bits” command would set OPR(5) to zero and, hence, the pin
RxRDY) they will be switched to an open drain configuration. In this
configuration an external pull–up device will be required
OPERATION
TransmitterThe SC26C92 is conditioned to transmit data when the transmitter is
enabled through the command register. The SC26C92 indicates to
the CPU that it is ready to accept a character by setting the TxRDY
bit in the status register. This condition can be programmed to
generate an interrupt request at OP0, OP1 and INTRN. When the
transmitter is initially enabled the TxRDY and TxEMT bits will be set
in the status register. When a character is loaded to the transmit
FIFO the TxEMT bit will be reset. The TxEMT will not set until: 1)
the transmit FIFO is empty and the transmit shift register has
finished transmitting the stop bit of the last character written to the
transmit FIFO, or 2) the transmitter is disabled and then re–enabled.
The TxRDY bit is set whenever the transmitter is enabled and the
TxFIFO is not full. Data is transferred from the holding register to
transmit shift register when it is idle or has completed transmission
of the previous character. Characters cannot be loaded into the
TxFIFO while the transmitter is disabled.
The transmitter converts the parallel data from the CPU to a serial
bit stream on the TxD output pin. It automatically sends a start bit
followed by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new
character is not available in the TxFIFO, the TxD output remains
High and the TxEMT bit in the Status Register (SR) will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character into the TxFIFO.
If the transmitter is disabled, it continues operating until the charac-
ter currently being transmitted and any characters in the TxFIFO
including parity and stop bit(s) have been completed.
Note the differences between the transmitter disable and the trans-
mitter reset: reset stops all transmission immediately, effectively
clears the TxFIFO and resets all status and Tx interrupt conditions.
Transmitter disable clears all Tx status and interrupts BUT allows
the Tx to complete the transmission of all data in the TxFIFO and in
the shift register. While the Tx is disabled the TxFIFO can not be
loaded with data.
The transmitter can be forced to send a continuous Low condition by
issuing a send break command from the command register. The
transmitter output is returned to the normal high with a stop break
command.
The transmitter can be reset through a software command. If it is
reset, operation ceases immediately and the transmitter must be
enabled through the command register before resuming operation.
If the CTS option is enabled (MR2[4] = 1), the CTSN input at IP0 or
IP1 must be low in order for the character to be transmitted. The
transmitter will check the state of the CTS input at the beginning of
each character transmitted. If it is found to be High, the transmitter
will delay the transmission of any following characters until the CTS
has returned to the low state. CTS going high during the serializa-
tion of a character will not affect that character.
Transmitter “RS485 turnaround”The transmitter can also control the RTSN outputs, OP0 or OP1 via
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
This feature may be used automatically “turnaround” a transceiver
when operating in a simplex system.
Transmitter Disable Note (W.R.T. Turnaround)When the TxEMT bit is set the sequence of instructions: enable
transmitter — load transmit holding register — disable transmitter
will often result in nothing being sent. In the condition of the TxEMT
being set do not issue the disable until the TxRDY bit goes active
again after the character is loaded to the TxFIFO. The data is not
sent if the time between the end of loading the transmit holding
register and the disable command is less that 3/16 bit time in the
16x mode. One bit time in the 1x mode.
This is sometimes the condition when the RS485 automatic “turn-
around” is enabled . It will also occur when only one character is to
be sent and it is desired to disable the transmitter immediately after
the character is loaded.
In general, when it is desired to disable the transmitter before the
last character is sent AND the TxEMT bit is set in the status register
be sure the TxRDY bit is active immediately before issuing the
transmitter disable instruction. (TxEMT is always set if the transmit-
ter has underrun or has just been enabled), TxRDY sets at the end
of the “start bit” time. It is during the start bit that the data in the
transmit holding register is transferred to the transmit shift register.
Transmitter Flow controlThe transmitter may be controlled by the CTSN input when enabled
by MR2(4). The CTSN input would be connected to RTSN output of
the receiver to which it is communicating. See further description in
the MR 1 and MR2 register descriptions.
ReceiverThe SC26C92 is conditioned to receive data when enabled through
the command register. The receiver looks for a High-to-Low
(mark-to-space) transition of the start bit on the RxD input pin. If a
transition is detected, the state of the RxD pin is sampled each 16X
clock for 7-1/2 clocks (16X clock mode) or at the next rising edge of
the bit time clock (1X clock mode). If RxD is sampled High, the start
bit is invalid and the search for a valid start bit begins again. If RxD
is still Low, a valid start bit is assumed and the receiver continues to
sample the input at one bit time intervals at the theoretical center of
the bit, until the proper number of data bits and parity bit (if any)
have been assembled, and one stop bit has been detected. The
least significant bit is received first. The data is then transferred to
the Receive FIFO and the RxRDY bit in the SR is set to a 1. This
condition can be programmed to generate an interrupt at OP4 or
OP5 and INTRN. If the character length is less than 8 bits, the most
significant unused bits in the RxFIFO are set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (framing error) and RxD remains Low for one half
of the bit period after the stop bit was sampled, then the receiver
operates as if a new start bit transition had been detected at that
point (one-half bit time after the stop bit was sampled).
The parity error, framing error, and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set. If a break condition is detected (RxD is Low for the
entire character including the stop bit), a character consisting of all
zeros will be loaded into the RxFIFO and the received break bit in
the SR is set to 1. The RxD input must return to high for two (2)
edges since the clock of the controller is not synchronous to
the X1 clock.
Receiver FIFOThe RxFIFO consists of a First-In-First-Out (FIFO) stack with a
capacity of eight characters. Data is loaded from the receive shift
register into the topmost empty position of the FIFO. The RxRDY bit
in the status register is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all eight stack
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RxFIFO outputs the data at the top
of the FIFO. After the read cycle, the data FIFO and its associated
status bits (see below) are ‘popped’ thus emptying a FIFO position
for new data.
Receiver Status BitsThere are five (5) status bits that are evaluated with each byte (or
character) received: received break, framing error, parity error, over-
run error, and change of break. The first three are appended to
each byte and stored in the RxFIFO. The last two are not necessar-
ily related to the byte being received or a byte that is in the RxFIFO.
They are however developed by the receiver state machine.
The received break, framing error, parity error and overrun error (if
any) are strobed into the RxFIFO at the received character bound-
ary, before the RxRDY status bit is set. For character mode (see
below) status reporting the SR (Status Register) indicates the condi-
tion of these bits for the character that is the next to be read from the
FIFO
The ”received break” will always be associated with a zero byte in
the RxFIFO. It means that zero character was a break character
and not a zero data byte. The reception of a break condition will
always set the ”change of break” (see below) status bit in the Inter-
rupt Status Register (ISR). The Change of break condition is reset
by a reset error status command in the command register
Break DetectionIf a break condition is detected (RxD is Low for the entire character
including the stop bit), a character consisting of all zeros will be
loaded into the RxFIFO and the received break bit in the SR is set to
1. The change of break bit also sets in the ISR The RxD input must
return to high for two (2) clock edges of the X1 crystal clock for the
receiver to recognize the end of the break condition and begin the
search for a start bit.
This will usually require a high time of one X1 clock period or 3
X1 edges since the clock of the controller is not synchronous
to the X1 clock.
Framing ErrorA framing error occurs when a non–zero character whose parity bit
(if used) and stop; bit are zero. If RxD remains low for one half of
the bit period after the stop bit was sampled, then the receiver
operates as if the start bit of the next character had been detected.
The parity error indicates that the receiver–generated parity was not
the same as that sent by the transmitter.
The framing, parity and received break status bits are reset when
the associated data byte is read from the RxFIFO since these “error”
conditions are attached to the byte that has the error
Overrun Error
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
seen. At this point the host has approximately 6/16–bit time to read
a byte from the RxFIFO or the overrun condition will be set. The
10th character then overruns the 9th and the 11th the 10th and so on
until an open position in the RxFIFO is seen. (“seen” meaning at
least one byte was read from the RxFIFO.)
Overrun is cleared by a use of the “error reset” command in the
command register.
The fundamental meaning of the overrun is that data has been lost.
Data in the RxFIFO remains valid. The receiver will begin placing
characters in the RxFIFO as soon as a position becomes vacant.
Note: Precaution must be taken when reading an overrun FIFO.
There will be 8 valid characters in the receiver FIFO. There will
be one character in the receiver shift register. However it will
NOT be known if more than one “over–running” character has
been received since the overrun bit was set. The 9th character
is received and read as valid but it will not be known how many
characters were lost between the two characters of the 8th and
9th reads of the RxFIFOThe ”Change of break” means that either a break has been detected
or that the break condition has been cleared. This bit is available in
the ISR. The break change bit being set in the ISR and the received
break bit being set in the SR will signal the beginning of a break. At
the termination of the break condition only the change of break in
the ISR will be set. After the break condition is detected the ter-
mination of the break will only be recognized when the RxD input
has returned to the high state for two successive edges of the 1x
clock; 1/2 to 1 bit time (see above).
The receiver is disabled by reset or via CR commands. A disabled
receiver will not interrupt the host CPU under any circumstance in
the normal mode of operation. If the receiver is in the multi–drop or
special mode, it will be partially enabled and thus may cause an
interrupt. Refer to section on Wake–Up and the register description
for MR1 for more information.
Receiver Status Modes (block and character)In addition to the data word, three status bits (parity error, framing
error, and received break) are also appended to each data character
in the FIFO (overrun is not). Status can be provided in two ways, as
programmed by the error mode control bit in the mode register. In
the ‘character’ mode, status is provided on a character–by–charac-
ter basis; the status applies only to the character at the top of the
FIFO. In the ‘block’ mode, the status provided in the SR for these
three bits is the logical–OR of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command was issued.
In either mode reading the SR does not affect the FIFO. The FIFO
is ‘popped’ only when the RxFIFO is read. Therefore the status
register should be read prior to reading the FIFO.
Receiver Flow ControlThe receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
becomes available, the RTSN output will be re–asserted automati-
cally. This feature can be used to prevent an overrun, in the receiv-
er, by connecting the RTSN output to the CTSN input of the
transmitting device.
Note: The transmitter may also control the “RTSN” pin. WhenIf the receiver is disabled, the FIFO characters can be read. Howev-
er, no additional characters can be received until the receiver is
enabled again. If the receiver is reset, the FIFO and all of the re-
ceiver status, and the corresponding output ports and interrupt are
reset. No additional characters can be received until the receiver is
enabled again.
Receiver Reset and DisableReceiver disable stops the receiver immediately – data being
assembled in the receiver shift register is lost. Data and status in
the FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected. A receiver reset will discard
the present shift register date, reset the receiver ready bit (RxRDY),
clear the status of the byte at the top of the FIFO and re-align the
FIFO read/write pointers.
A ‘watchdog timer’ is associated with each receiver. Its interrupt is
enabled by MR0[7]. The purpose of this timer is to alert the control
processor that characters are in the RxFIFO which have not been
read and/or the data stream has stopped. This situation may occur
at the end of a transmission when the last few characters received
are not sufficient to cause an interrupt.
This counter times out after 64 bit times. It is reset each time a
character is transferred from the receiver shift register to the
RxFIFO or a read of the RxFIFO is executed.
Receiver Timeout ModeIn addition to the watch dog timer described in the receiver section,
the counter/timer may be used for a similar function. Its
programmability, of course, allows much greater precision of time
out intervals.
The timeout mode uses the received data stream to control the
counter. Each time a received character is transferred from the shift
register to the RxFIFO, the counter is restarted. If a new character
is not received before the counter reaches zero count, the counter
ready bit is set, and an interrupt can be generated. This mode can
be used to indicate when data has been left in the RxFIFO for more
than the programmed time limit. Otherwise, if the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU may not know
there is data left in the FIFO. The CTU and CTL value would be
programmed for just over one character time, so that the CPU would
be interrupted as soon as it has stopped receiving continuous data.
This mode can also be used to indicate when the serial line has
been marking for longer than the programmed time limit. In this
case, the CPU has read all of the characters from the FIFO, but the
last character received has started the count. If there is no new
data during the programmed time interval, the counter ready bit will
get set, and an interrupt can be generated.
The timeout mode is enabled by writing the appropriate command to
the command register. Writing an ‘Ax’ to CRA or CRB will invoke
the timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will
disable the timeout mode. The timeout mode should only be used
by one channel at once, since it uses the C/T. If, however, the
timeout mode is enabled from both receivers, the timeout will occur
only when both receivers have stopped receiving data for the
timeout period. CTU and CTL must be loaded with a value greater
than the normal receive character period. The timeout mode
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
the value in CTU and CTL and then restarted on the next C/T clock.
If the C/T is allowed to end the count before a new character has
been received, the counter ready bit, ISR[3], will be set. If IMR[3] is
set, this will generate an interrupt. Receiving a character after the
C/T has timed out will clear the counter ready bit, ISR[3], and the
interrupt. Invoking the ‘Set Timeout Mode On’ command, CRx = ‘Ax’,
will also clear the counter ready bit and stop the counter until the
next character is received.
Time Out Mode CautionWhen operating in the special time out mode, it is possible to
generate what appears to be a “false interrupt”, i.e., an interrupt
without a cause. This may result when a time-out interrupt occurs
and then, BEFORE the interrupt is serviced, another character is
received, i.e., the data stream has started again. (The interrupt
latency is longer than the pause in the data stream.) In this case,
when a new character has been receiver, the counter/timer will be
restarted by the receiver, thereby withdrawing its interrupt. If, at this
time, the interrupt service begins for the previously seen interrupt, a
read of the ISR will show the “Counter Ready” bit not set. If nothing
else is interrupting, this read of the ISR will return a x’00 character.
The CTS, RTS, CTS Enable Tx signalsCTS (Clear To Send) is usually meant to be a signal to the transmit-
ter meaning that it may transmit data to the receiver. The CTS input
is on pin IP0 or IP1 for the transmitter. The CTS signal is active low;
thus, it is called CTSN. RTS is usually meant to be a signal from the
receiver indicating that the receiver is ready to receive data. It is
also active low and is, thus, called RTSN. RTSN is on pin OP0 or
OP1. A receiver’s RTS output will usually be connected to the CTS
input of the associated transmitter. Therefore, one could say that
RTS and CTS are different ends of the same wire!
MR2(4) is the bit that allows the transmitter to be controlled by the
CTS pin ( IP0 or IP1). When this bit is set to one AND the CTS
input is driven high, the transmitter will stop sending data at the end
of the present character being serialized. It is usually the RTS out-
put of the receiver that will be connected to the transmitter’s CTS
input. The receiver will set RTS high when the receiver FIFO is full
AND the start bit of the ninth character is sensed. Transmission
then stops with nine valid characters in the receiver. When MR2(4)
is set to one, CTSN must be at zero for the transmitter to operate. If
MR2(4) is set to zero, the IP0 or IP1 pin will have no effect on the
operation of the transmitter.
MR1(7) is the bit that allows the receiver to control OP0 or OP1.
When OP0 or OP1 is controlled by the receiver, the meaning of that
pin will be RTS. However, a point of confusion arises in that these
pins may also be controlled by the transmitter. When the transmit-
ter is controlling them the meaning is not RTS at all. It is, rather, that
the transmitter has finished sending its last data byte.
Programming the OP0 or OP1 pin to be controlled by the receiver
and the transmitter at the same time is allowed, but would usually be
incompatible.
RTS can also be controlled by the commands 1000 and 1001 in the
command register. RTS is expressed at the OP0 or OP1 pin which
is still an output port. Therefore, the state of OP0 or OP1 should be
set low (either by commands of the CR register or by writing to the
SOPR or ROPR (Set or Reset Output Port Registers) for the receiv-
er to generate the proper RTS signal. The logic at the output is
the MR registers) will return the OP pins pin to the control of the
OPR register.
Multidrop Mode (9-bit or Wake-Up)The DUART is equipped with a wake up mode for multidrop
applications. This mode is selected by programming bits MR1A[4:3]
or MR1B[4:3] to ‘11’ for Channels A and B, respectively. In this
mode of operation, a ‘master’ station transmits an address character
followed by data characters for the addressed ‘slave’ station. The
slave stations, with receivers that are normally disabled, examine
the received data stream and ‘wakeup’ the CPU (by setting RxRDY)
only upon receipt of an address character. The CPU compares the
received address to its station address and enables the receiver if it
wishes to receive the subsequent data characters. Upon receipt of
another address character, the CPU may disable the receiver to
initiate the process again.
A transmitted character consists of a start bit, the programmed
number of data bits, and Address/Data (A/D) bit, and the
programmed number of stop bits. The polarity of the transmitted
A/D bit is selected by the CPU by programming bit
MR1A[2]/MR1B[2]. MR1A[2]/MR1B[2] = 0 transmits a zero in the
A/D bit position, which identifies the corresponding data bits as data
while MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position,
which identifies the corresponding data bits as an address. The
CPU should program the mode register prior to loading the
corresponding data bits into the TxFIFO.
In this mode, the receiver continuously looks at the received data
stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RxFIFO if the
received A/D bit is a one (address tag), but discards the received
character if the received A/D bit is a zero (data tag). If enabled, all
received characters are transferred to the CPU via the RxFIFO. In
either case, the data bits are loaded into the data FIFO while the
A/D bit is loaded into the status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing error, overrun error, and
break detect operate normally whether or not the receive is enabled.
PROGRAMMINGThe operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Each channel has 3 mode registers (MR0, 1, 2) which control the
basic configuration of the channel. Access to these registers is
controlled by independent MR address pointers. These pointers are
set to 0 or 1 by MR control commands in the command register
“Miscellaneous Commands”. Each time the MR registers are
accessed the MR pointer increments, stopping at MR2. It remains
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions. The reserved
registers at addresses H‘02’ and H‘0A’ should never be read during
normal operation since they are reserved for internal diagnostics.
Table 1. SC26C92 Register Addressing
NOTE:The three MR Registers are accessed via the MR Pointer and Commands 1xh and Bxh. (Where “x” represents receiver and transmitter enable/
disable control)
Table 2. Register Bit Formats
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
Table 2. Register Bit Formats (Continued)
Philips Semiconductors Product specification
SC26C92Dual universal asynchronous receiver/transmitter (DUART)
REGISTER DESCRIPTIONS Mode RegistersMR0 is accessed by setting the MR pointer to 0 via the command
register command B.
MR0A
MR0[7] – This bit controls the receiver watch dog timer. 0 = disable,1 = enable. When enabled, the watch dog timer will generate a
receiver interrupt if the receiver FIFO has not been accessed within
64 bit times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
MR0[6] – Bit 2 of receiver FIFO interrupt level. This bit along with Bit6 of MR1 sets the fill level of the 8 byte FIFO that generates the
receiver interrupt.
Table 3. Receiver FIFO Interrupt Fill LevelFor the receiver these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
MR0[5:4] – Tx interrupt fill level.
Table 4. Transmitter FIFO Interrupt Fill LevelFor the transmitter these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
transmit FIFO has 8 bytes empty. It will then attempt to interrupt as
soon as the transmitter is enabled. The default setting of the MR0
bits (00) condition the transmitter to attempt to interrupt only when it
is completely empty. As soon as one byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
MR0[3] – Not used. Should be set to 0.100 Extended mode II
Other combinations should not be used
Note: MR0[3:0] are not used in channel B and should be set to 0.
MR1AMR1A is accessed when the Channel A MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CR command 1. After reading or writing MR1A, the
pointer will point to MR2A.
MR1A[7] – Channel A Receiver Request-to-Send Control
(Flow Control)This bit controls the deactivation of the RTSAN output (OP0) by the
receiver. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0].
MR1A[7] = 1 causes RTSAN to be negated (OP0 is driven to a ‘1’
[VCC]) upon receipt of a valid start bit if the Channel A FIFO is full.
This is the beginning of the reception of the ninth byte. If the FIFO is
not read before the start of the tenth byte, an overrun condition will
occur and the tenth byte will be lost. However, the bit in OPR[0] is
not reset and RTSAN will be asserted again when an empty FIFO
position is available. This feature can be used for flow control to
prevent overrun in the receiver by using the RTSAN output signal to
control the CTSN input of the transmitting device.
MR1[6] – Bit 1 of the receiver interrupt control. See descriptionunder MR0[6].
MR1A[5] – Channel A Error Mode SelectThis bit select the operating mode of the three FIFOed status bits
(FE, PE, received break) for Channel A. In the ‘character’ mode,
status is provided on a character-by-character basis; the status
applies only to the character at the top of the FIFO. In the ‘block’
mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last ‘reset error’ command for Channel
A was issued.
MR1A[4:3| – Channel A Parity Mode SelectIf ‘with parity’ or ‘force parity’ is selected a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data MR1A[4:3] = 11 selects Channel A to operate in the
special multidrop mode described in the Operation section.
MR1A[2] – Channel A Parity Type SelectThis bit selects the parity type (odd or even) if the ‘with parity’ mode
is programmed by MR1A[4:3], and the polarity of the forced parity bit
if the ‘force parity’ mode is programmed. It has no effect if the ‘no
parity’ mode is programmed. In the special multidrop mode it
selects the polarity of the A/D bit.
