SC16C750BIB64 ,5 V, 3.3 V and 2.5 V UART with 64-byte FIFOsFeatures■ Single channel■ 5 V, 3.3 V and 2.5 V operation■ 5 V tolerant inputs■ Industrial temperatu ..
SC16C750BIBS ,5 V, 3.3 V and 2.5 V UART with 64-byte FIFOsLimiting values”.SC16C750BNXP Semiconductors5 V, 3.3 V and 2.5 V UART with 64-byte FIFOsn Four sele ..
SC16C752B ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
SC16C752BIBS ,5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOsFeatures■ Dual channel■ Pin compatible with SC16C2550 with additional enhancements■ Up to 5 Mbit/s ..
SC16C754BIA68 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
SC16C754BIA68 ,5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOsFeaturesn 4 channel UARTn 5 V, 3.3 V and 2.5 V operationn Pin compatible with SC16C654IA68, TL16C75 ..
SDB105 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SDB107 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SDB107 , 1 Amp Single Phase Glass Passivated Bridge Rectifier 50 to 1000 Volts
SDB10A40 , Schottky Barrier Rectifier
SDB20S30 ,Silicon Carbide Schottky DiodeSDP20S30Preliminary dataSDB20S30Silicon Carbide Schottky Diode
SC16C750BIA44-SC16C750BIB64
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
SC16C750BV , 3.3 V and 2.5 V UART with 64-byte FIFOs
Rev. 03 — 13 December 2004 Product data General descriptionThe SC16C750B is a Universal Asynchronous Receiver and T ransmitter (UART)
used for serial data communications. Its principal function is to convert parallel data
into serial data, and vice versa. The UART can handle serial data ratesupto3 Mbit/s.
The SC16C750B is pin compatible with the TL16C750 and it will power-up to be
functionally equivalent to the 16C450. Programming of control registers enables the
added features of the SC16C750B. Some of these added features are the 64-byte
receive and transmit FIFOs, automatic hardware flow control. The selectable
auto-flow control feature significantly reduces software overload and increases
system efficiency while in FIFO mode by automatically controlling serial data flow
using RTS output and CTS input signals. The SC16C750B also provides DMA mode
data transfers through FIFO trigger levels and the TXRDY and RXRDY signals.
On-board status registers provide the user with error indications, operational status,
and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The SC16C750B operates at 5 V, 3.3 V and 2.5 V, the industrial temperature range
and is available in plastic PLCC44, LQFP64, and HVQFN32 packages.
Features Single channel5 V, 3.3 V and 2.5 V operation5 V tolerant inputs Industrial temperature range (−40 °C to +85 °C) After reset, all registers are identical to the typical 16C450 register set Capable of running with all existing generic 16C450 software Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550. Software compatible with SC16C750 and TL16C750 Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3V , and 1 Mbit/sat
2.5V 64 byte transmit FIFO 64 byte receive FIFO with error flags Programmable auto-RTS and auto-CTS In auto-CTS mode, CTS controls transmitter In auto-RTS mode, RxFIFO contents and threshold control RTS Automatic hardware flow control Software selectable Baud Rate Generator Four selectable Receive interrupt trigger levels
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs Standard modem interface Sleep mode Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break) Independent receiver clock input Transmit, Receive, Line Status, and Data Set interrupts independently controlled Fully programmable character formatting: 5, 6, 7, or 8-bit characters Even, Odd, or No-Parity formats 1, 11 ⁄2, or 2-stop bit Baud generation (DC to 3 Mbit/s) False start-bit detection Complete status reporting capabilities 3-State output TTL drive capabilities for bi-directional data bus and control bus Line Break generation and detection Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).
Ordering information
Table 1: Ordering informationIndustrial: VCC= 2.5 V, 3.3 V or 5V ± 10%; Tamb= −40 °C to +85 °C.
SC16C750BIA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
SC16C750BIB64 LQFP64 plastic low profile quad flat package; 64 leads; 10×10× 1.4 mm SOT314-2
SC16C750BIBS HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; terminals; body 5×5× 0.85 mm
SOT617-1
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs Block diagram
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs Pinning information
5.1 Pinning
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
5.2 Pin description
Table 2: Pin description
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Table 2: Pin description…continued
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Table 2: Pin description…continued
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs[1] In sleep mode, XTAL2 is left floating.
Table 2: Pin description…continued
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs Functional descriptionThe SC16C750B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data thatis required with digital data systems. Synchronizationfor
the serial data stream is accomplished by adding start and stop bits to the transmit
datato forma data character (character orientated protocol). Data integrityis insured attachinga paritybitto the data character. The paritybitis checkedby the receiver
for any transmission bit errors. The SC16C750B is fabricated with an advanced
CMOS process to achieve low drain power and high speed requirements.
The SC16C750Bisan upward solution that provides64 bytesof transmit and receive
FIFO memory, insteadof nonein the 16C450,or16in the 16C550. The SC16C750B
is designed to work with high speed modems and shared network environments that
require fast data processing time. Increased performance is realized in the
SC16C750B by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levels of FIFO trigger interrupt and automatic hardware flow control is
uniquely provided for maximum data throughput performance, especially when
operating in a multi-channel environment. The combination of the above greatly
reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C750B is capable of operation up to 3 Mbit/s with a 48 MHz external clock
input (at 5 V).
The rich feature set of the SC16C750B is available through internal registers.
Automatic hardware flow control, selectable transmit and receive FIFO trigger level,
selectable TX and RX baud rates, modem interface controls, and a sleep mode are
some of these features.
6.1 Internal registersThe SC16C750B provides 12 internal registers for monitoring and control. These
registers are shown in Table 3. These twelve registers are similar to those already
available in the standard 16C550. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Register functions are more fully
described in the following paragraphs.
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs[1] These registers are accessible only when LCR[7] is a logic0.
[2] These registers are accessible only when LCR[7] is a logic1.
6.2 FIFO operationThe 64-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). The receiver FIFO section includes a time-out function to
ensure datais deliveredto the external CPU. An interruptis generated whenever the
Receive Holding Register (RHR) has not been read following the loading of a
character or the receive trigger level has not been reached.
Table 3: Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1] 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register Line Control Register 0 0 Modem Control Register Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)[2] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch
Table 4: Flow control mechanism
16-byte FIFO 1 0 4 0 8 0 14 14 0
64-byte FIFO 1 0 16 16 0 32 32 0 56 56 0
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
6.3 Hardware flow controlWhen automatic hardware flow controlis enabled, the SC16C750B monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting MCR[5] (RTS) and
MCR[1] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, the SC16C750B will suspend TX transmissions as soon as the
stop bit of the character in process is shifted out. Transmission is resumed after the
CTS input returns to a logic 0, indicating more data may be sent.
With the Auto-RTS function enabled,an interruptis generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is emptied. However, under the
above described conditions, the SC16C750B will continue to accept data until the
receive FIFO is full.
6.4 Time-out interruptsWhen two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C750B FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
6.5 Programmable baud rate generatorThe SC16C750B supports high speed modem technologies that have increased
input data ratesby employing data compression schemes. For example,a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate. 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of accepting an input clock up to 48 MHz, as required for supporting a Mbit/s data rate. The SC16C750B can be configured for internal or external clock
operation. For internal clock oscillator operation,an industry standard microprocessor
crystal (parallel resonant/22-33 pF load) is connected externally between the XTAL1
and XTAL2 pins (see Figure 5). Alternatively, an external clock can be connected to
the XTAL1 pin to clock the internal baud rate generator for standard or custom rates
(see Table5).
The generator divides the input 16× clock by any divisor from 1 to 216− 1. The
SC16C750B divides the basic crystal or external clock by 16. The frequency of the
BAUDOUT output pin is exactly 16× (16 times) of the selected baud rate
(BAUDOUT=16 Baud Rate). Customized baud rates can be achieved by selecting
the proper divisor values for the MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 5 shows selectable baud rates when using a 1.8432 MHz crystal.
For custom baud rates, the divisor value can be calculated using the following
equation:
(1)
Divisor (in decimal) XTAL1 clock frequency
serial data rate 16× -----------------------------------------------------------=
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
6.6 DMA operationThe SC16C750B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the stateof the RXRDY and TXRDY
output pins. Tables 6 and 7 show this.
Table 5: Baud rates using 1.8432 MHz or 3.072 MHz crystal
Table 6: Effect of DMA mode on state of RXRDY pin= FIFO empty 0-to-1 transition when FIFO empties= at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level, time-out occurs
Table 7: Effect of DMA mode on state of TXRDY pin= at least 1 byte in FIFO 0-to-1 transition when FIFO becomes full= FIFO empty 1-to-0 transition when FIFO becomes empty
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
6.7 Sleep modeThe SC16C750Bis designedto operate with low power consumption.A special sleep
mode is included to further reduce power consumption when the chip is not being
used. With IER[4] enabled (set to a logic 1), the SC16C750B enters the sleep mode,
but resumes normal operation whena startbitis detected,a changeof stateof RXor anyof the modem input pins RI, CTS, DSR, DCD,ora transmit datais providedby
the user.If the sleep modeis enabled and the SC16C750Bis awakenedby oneof the
conditions described above,it will returnto the sleep mode automatically after the last
character is transmitted or read by the user. In any case, the sleep mode will not be
entered whilean interrupt(s)is pending. The SC16C750B will stayin the sleep mode
of operation until it is disabled by setting IER[4] to a logic0.
6.8 Loop-back modeThe internal loop-back capability allows on-board diagnostics.In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally. MCR[0:3] register bits are usedfor controlling loop-back diagnostic testing.
In the loop-back mode, OUT1 and OUT2 in the MCR register (bits 2-3) control the
modem RI and DCD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are
usedto control the modem DSR and CTS inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see Figure 6). The CTS, DSR,
DCD, and RI are disconnected from their normal modem control input pins, and
instead are connected internallyto RTS, DTR, OUT2 and OUT1. Loop-back test data
is entered into the transmit holding register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the serial data to the receive
UART via the internal loop-back connection. The receive UART converts the serial
data back into parallel data that is then made available at the user data interface
D0-D7. The user optionally compares the received datato the initial transmitted data
for verifying error-free operation of the UART TX/RX circuits. this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read
using lower four bits of the Modem Status Register (MSR[0:3]) instead of the four
Modem Status Register bits 4-7. The interrupts are still controlled by the IER.
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs Register descriptionsTable8 details the assignedbit functionsfor the fifteen SC16C750B internal registers.
The assignedbit functions are more fully definedin Section 7.1 through Section 7.10.
[1] The value shown represents the register’s initialized HEX value; X= n/a.
[2] These registers are accessible only when LCR[7]=0.
[3] The Special Register set is accessible only when LCR[7] is set to a logic1.
Table 8: SC16C750B internal registers
General Register Set[2]
Special Register Set[3]
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.1 Transmit (THR) and Receive (RHR) Holding RegistersThe serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR
register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic0= FIFO full; logic1= at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive datais removed from the SC16C750B and receive FIFOby reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting
clocks at the 16× clock rate. After 7-1 ⁄2 clocks, the start bit time should be shifted to
the center of the start bit. At this time the start bit is sampled, and if it is still a logic0
it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INT output pin.
Table 9: Interrupt Enable Register bits description7:6 IER[7],
IER[6]
Not used. IER[5] Low power mode.
Logic0= Disable low power mode (normal default condition).
Logic1= Enable low power mode. IER[4] Sleep mode.
Logic0= Disable sleep mode (normal default condition).
Logic1= Enable sleep mode. See Section 6.7 “Sleep mode” for details. IER[3] Modem Status Interrupt.
Logic0= Disable the modem status register interrupt (normal default
condition).
Logic1= Enable the modem status register interrupt. IER[2] Receive Line Status interrupt. This interrupt willbe issued whenevera fully
assembled receive character is transferred from RSR to the RHR/FIFO,
i.e., data ready, LSR[0].
Logic0= Disable the receiver line status interrupt (normal default
condition).
Logic1= Enable the receiver line status interrupt.
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.2.1 IER versus Receive FIFO interrupt mode operationWhen the receive FIFO (FCR[0]= logic 1), and receive interrupts (IER[0]= logic1)
are enabled, the receive interrupts and register status will reflect the following:
The receive data available interrupts are issued to the external CPU when the
FIFO has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the
FIFO trigger level is reached. Both the ISR register status bit and the interrupt will
be cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the
shift register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus Receive/Transmit FIFO polled mode operationWhen FCR[0]= logic 1, resetting IER[0:3] enables the SC16C750B in the FIFO
polled modeof operation. Since the receiver and transmitter have separate bitsin the
LSR, eitheror both canbe usedin the polled modeby selecting respective transmitor
receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
LSR[7] will indicate any FIFO data errors. IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever
the THR is empty, and is associated with LSR[1].
Logic0= Disable the transmitter empty interrupt (normal default
condition).
Logic1= Enable the transmitter empty interrupt. IER[0] Receive Holding Register interrupt. This interrupt will be issued when the
FIFO has reached the programmed trigger level, or is cleared when the
FIFO drops below the trigger level in the FIFO mode of operation.
Logic0= Disable the receiver ready interrupt (normal default condition).
Logic1= Enable the receiver ready interrupt.
Table 9: Interrupt Enable Register bits description…continued
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.3 FIFO Control Register (FCR)This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1 DMA mode
Mode 0 (FCR bit 3= 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) willtoa logic0 wheneveran empty transmit spaceis availablein the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3= 1): Set and enable the interruptina block mode operation. The
transmit interrupt is set when the transmit FIFO is below the programmed trigger
level. The receive interrupt is set when the receive FIFO fills to the programmed
trigger level. However, the FIFO continues to fill regardless of the programmed level
until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
7.3.2 FIFO mode
Table 10: FIFO Control Register bits description7:6 FCR[7]
(MSB),
FCR[6]
(LSB)
RCVR trigger. These bits are usedtoset the trigger levelfor the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equalsthe programmed trigger level. However, the FIFOwill continueto
be loaded until it is full. Refer to Table 11. FCR[5] Logic0= 16-byte mode (normal default condition).
Logic1= 64-byte mode. FCR[4] Reserved. FCR[3] DMA mode select.
Logic0= Set DMA mode ‘0’ (normal default condition).
Logic1= Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C750B is in the16C450 mode (FIFOs disabled; FCR[0]= logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0]= logic1; FCR[3]= logic0), and when there are
no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C750B is in 16C450mode, or in the FIFO mode (FCR[0]= logic 1; FCR[3]= logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin willa logic0. Once active, the RXRDYpin willgotoa logic1 when there
are no more characters in the receiver.
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Transmit operation in mode ‘1’: When the SC16C750B is in FIFOmode (FCR[0]= logic 1; FCR[3]= logic 1), the TXRDY pin will be a
logic1 whenthe transmit FIFOis completely full.It willbea logic0 when
the FIFO is emptied.
Receive operation in mode ‘1’: When the SC16C750B is in FIFOmode (FCR[0]= logic1; FCR[3]= logic1) and the trigger level has been
reached,ora Receive Time-Out has occurred, the RXRDYpin willgoto
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO. FCR[2] XMIT FIFO reset.
Logic0= No FIFO transmit reset (normal default condition).
Logic1= Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO. FCR[1] RCVR FIFO reset.
Logic0= No FIFO receive reset (normal default condition).
Logic1= Clears the contentsofthe receive FIFO and resetsthe FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
Logic0= Disable the transmit and receive FIFO (normal default
condition).
Logic1= Enable the transmit and receive FIFO.
Table 11: RCVR trigger levels001 1
014 16
108 32
1114 56
Table 10: FIFO Control Register bits description…continued
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.4 Interrupt Status Register (ISR)The SC16C750B provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performinga read cycleon the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits.T able12 “Interrupt source” shows the data values
(bits 0-4) for the four prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 12: Interrupt source 0110 LSR (Receiver Line Status Register) 0100 RXRDY (Received Data Ready) 1100 RXRDY (Receive Data time-out) 0010 TXRDY (Transmitter Holding Register
Empty) 0000 MSR (Modem Status Register)
Table 13: Interrupt Status Register bits description7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
Logic 0 or cleared= default condition. ISR[5] 64-byte FIFO enable.
Logic0= 16-byte operation.
Logic1= 64-byte operation. ISR[4] Not used.
3:1 ISR[3:1] INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 12).
Logic 0 or cleared= default condition. ISR[0] INT status.
Logic0= An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic1= No interrupt pending (normal default condition).
Philips Semiconductors SC16C750B V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.5 Line Control Register (LCR)The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 14: Line Control Register bits description LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhance
Feature mode enable.
Logic0= Divisor latch disabled (normal default condition).
Logic1= Divisor latch and enhanced feature register enabled. LCR[6] Set break. When enabled, the Break controlbit causesa break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic0.
Logic0= no TX break condition (normal default condition).
Logic1=forcesthe transmitter output (TX)toa logic0for alerting the
remote receiver to a line break condition. LCR[5] Set parity. If the parity bit is enabled, LCR[5] selects the forced parity
format. Programs the parity conditions (see Table 15).
Logic0= parity is not forced (normal default condition).
LCR[5]= logic1 and LCR[4]= logic0: paritybitis forcedtoa logical1
for the transmit and receive data.
LCR[5]= logic1 and LCR[4]= logic1: paritybitis forcedtoa logical0
for the transmit and receive data. LCR[4] Even parity. If the parity bit is enabled with LCR[3] set to a logic1,
LCR[4] selects the even or odd parity format.
Logic0= ODD Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format (normal default condition).
Logic1= EVEN Parity is generated by forcing an even number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format. LCR[3] Parity enable. Parity or no parity can be selected via this bit.
Logic0= no parity (normal default condition).
Logic1=a parity bit is generated during the transmission, receiver
checks the data and parity for transmission errors. LCR[2] Stop bits. The lengthof stopbitis specifiedby thisbitin conjunction with
the programmed word length (see Table 16).
Logic 0 or cleared= default condition.
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 17).
Logic 0 or cleared= default condition.
