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SC16C554DIA68-SC16C554DIB64-SC16C554IB64
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
SC16C554/554DQuad UART with 16-byte FIFO and infrared (IrDA)
encoder/decoder
Rev. 05 — 10 May 2004 Product data DescriptionThe SC16C554/554D is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. It comes with an Intel or Motorola interface.
The SC16C554/554Dis pin compatible with the ST16C554 and TL16C554 andit will
power-up to be functionally equivalent to the 16C454. Programming of control
registers enables the added features of the SC16C554/554D. Some of these added
features are the 16-byte receive and transmit FIFOs, automatic hardwareor software
flow control and Infrared encoding/decoding. The selectable auto-flow control feature
significantly reduces software overload and increases system efficiency whilein FIFO
mode by automatically controlling serial data flow using RTS output and CTS input
signals. The SC16C554/554D also provides DMA mode data transfers through FIFO
trigger levels and the TXRDY and RXRDY signals. On-board status registers provide
the user with error indications, operational status, and modem interface control.
System interrupts may be tailored to meet user requirements. An internal loop-back
capability allows on-board diagnostics.
The SC16C554/554D operatesat5V, 3.3V and 2.5V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, and LQFP80 packages.
Features5 V, 3.3 V and 2.5 V operation Industrial temperature range The SC16C554/554D is pin compatible with the industry-standard
ST16C454/554, ST68C454/554, ST16C554, TL16C554 Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5V 16-byte transmit FIFO 16-byte receive FIFO with error flags Automatic software/hardware flow control Programmable Xon/Xoff characters Software selectable Baud Rate Generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface or infrared IrDA encoder/decoder interface Sleep mode Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break) Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder Fully programmable character formatting: 5, 6, 7, or 8-bit characters Even, Odd, or No-Parity formats 1, 11 ⁄2, or 2-stop bit Baud generation (DC to 5 Mbit/s) False start-bit detection Complete status reporting capabilities 3-State output TTL drive capabilities for bi-directional data bus and control bus Line Break generation and detection Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).
Ordering information
Table 1: Ordering informationSC16C554DIA68 PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
SC16C554DIB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10×10× 1.4 mm SOT314-2
SC16C554IB64 LQFP64 plastic low profile quad flat package; 64 leads; body 10×10× 1.4 mm SOT314-2
SC16C554IB80 LQFP80 plastic low profile quad flat package; 80 leads; body 12×12× 1.4 mm SOT315-1
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder Block diagram
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder Pinning information
5.1 Pinning
5.1.1 PLCC68
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
5.1.2 LQFP64
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
5.1.3 LQFP80
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
5.2 Pin description
Table 2: Pin description
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 2: Pin description…continued
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 2: Pin description…continued
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 2: Pin description…continued
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder Functional descriptionThe SC16C554/554D provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data thatis required with digital data systems. Synchronizationfor
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character. Data integrity is insured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex,
especially when manufactured on a single integrated silicon chip. The
SC16C554/554D represents suchan integration with greatly enhanced features. The
SC16C554/554Dis fabricated withan advanced CMOS processto achieve low drain
power and high speed requirements.
The SC16C554/554D is an upward solution that provides 16 bytes of transmit and
receive FIFO memory, instead of none in the 16C454. The SC16C554/554D is
designed to work with high speed modems and shared network environments that
require fast data processing time. Increased performance is realized in the
SC16C554/554D by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levels of FIFO trigger interrupt and automatic hardware/software flow
control is uniquely provided for maximum data throughput performance, especially
when operatingina multi-channel environment. The combinationof the above greatly
reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C554/554DAI68 combines the package interface modesof the 16C454/554
and 68C454/554 series on a single integrated chip. The 16 mode interface is
designed to operate with the Intel-type of microprocessor bus, while the 68 mode is
intended to operate with Motorola and other popular microprocessors. Following a
reset, the SC16C554/554DAI68is downward compatible with the 16C454/554or the
68C454/554, dependent on the state of the interface mode selection pin, 16/68.
The SC16C554/554Dis capableof operationto 1.5 Mbit/s witha24 MHz crystal and
up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the maximum
speed is 3 Mbit/s).
The rich feature set of the SC16C554/554D is available through internal registers.
Automatic hardware/software flow control, selectable transmit and receive FIFO
trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface,
modem interface controls, and a sleep mode are all standard features. In the mode, INTSEL and MCR[3] can be configured to provide a software controlled or
continuous interrupt capability. Due to pin limitations of the 64-pin package, this
feature is offered by two different LQFP64 packages. The SC16C554D operates in
the continuous interrupt enable mode by bonding INTSEL to VCC internally. The
SC16C554 operates in conjunction with MCR[3] by bonding INTSEL to GND
internally.
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6.1 Interface optionsTwo user interface modes are selectable for the PLCC68 package. These interface
modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature
corresponds to the early 16C454/554 and 68C454/554 package interfaces
respectively.
6.2 The 16 mode interfaceThe 16 mode configures the package interface pins for connection as a standard series (Intel) device and operates similar to the standard CPU interface available the 16C454/554.In the16 mode (pin 16/68= logic1), each UARTis selected with
individual chip select (CSx) pins, as shown in Table3.
6.3 The 68 mode interfaceThe68 mode configures the package interface pinsfor connection with Motorola, and
other popular microprocessor bus types. The interface operates similar to the
68C454/554. In this mode, the SC16C554/554D decodes two additional addresses,
A3-A4, to select one of the four UART ports. The A3-A4 address decode function is
used only when in the 68 mode (16/68 = logic 0), and is shown in Table4.
Table 3: Serial port channel selection, 16 mode interface1111 none
0111A
1011B
1101C
1110D
Table 4: Serial port channel selection, 68 mode interface n/a n/a none
000A
001B
010C
011D
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6.4 Internal registersThe SC16C554/554D provides17 internal registersfor monitoring and control. These
registers are shown in Table 5. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C554
features and capabilities, the SC16C554/554D offers an enhanced feature register
set (EFR, Xon/Xoff1-2) that provides on-board hardware/software flow control.
Register functions are more fully described in the following paragraphs.
[1] These registers are accessible only when LCR[7] is a logic0.
[2] These registers are accessible only when LCR[7] is a logic1.
[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF’ (HEX).
6.5 FIFO operationThe 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. With SC16C554 devices, the user can set the receive trigger
level, but not the transmit trigger level. The receiver FIFO section includesa time-out
function to ensure data is delivered to the external CPU. An interrupt is generated
whenever the Receive Holding Register (RHR) has not been read following the
loading of a character or the receive trigger level has not been reached.
Table 5: Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1] 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register Line Control Register 0 0 Modem Control Register Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)[2] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)[3] 1 0 Enhanced Feature Register Enhanced Feature Register 0 0 Xon1 word Xon1 word 0 1 Xon2 word Xon2 word 1 0 Xoff1 word Xoff1 word 1 1 Xoff2 word Xoff2 word
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6.6 Hardware flow controlWhen automatic hardware flow controlis enabled, the SC16C554/554D monitors the
CTS pin for a remote buffer overflow indication and controls the RTS pin for local
buffer overflows. Automatic hardware flow controlis selectedby setting EFR[6] (RTS)
and EFR[7] (CTS)toa logic1.If CTS transitions froma logic0toa logic1 indicating
a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C554/554D will suspend TX transmissions as soon as the stop bit of the
character in process is shifted out. T ransmission is resumed after the CTS input
returns to a logic 0, indicating more data may be sent.
With the Auto RTS function enabled,an interruptis generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will returntoa logic0 after the data buffer (FIFO)is unloadedto the next trigger level
below the programmed trigger. However, under the above described conditions, the
SC16C554/554D will continue to accept data until the receive FIFO is full.
6.7 Software flow controlWhen software flow control is enabled, the SC16C554/554D compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2
character value(s). If received character(s) match the programmed values, the
SC16C554/554D will halt transmission (TX) as soon as the current character(s) has
completed transmission. Whena match occurs, the receive ready(if enabled via Xoff
IER[5]) flags willbe set and the interrupt output pin(if receive interruptis enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C554/554D will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C554/554D will resume operation
and clear the flags (ISR[4]).
Reset initially sets the contentsof the Xon/Xoff 8-bit flow control registerstoa logic0.
Following reset, the user can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
the SC16C554/554D compares two consecutive receive characters with two software
flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described flow control mechanisms, flow control
characters are not placed (stacked) in the user accessible RX data buffer or FIFO. the event that the receive bufferis overfilling and flow control needstobe executed,
the SC16C554/554D automatically sends an Xoff message (when enabled) via the
Table 6: Flow control mechanism 4 1 8 4 8 12 8 14 14 10
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decodercharacters as soon as received data passes the programmed trigger level. To clear
this condition, the SC16C554/554D will transmit the programmed Xon1,2 characters
as soon as receive data drops below the programmed trigger level.
6.8 Special feature software flow controlA special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software flow control shouldbe turnedoff when using this special
mode by setting EFR[0-3] to a logic0.
The SC16C554/554D compares each incoming receive character with Xoff2 data.Ifa
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table 8) shows each X-Register with eight bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or bits. The word length selected by LCR[0-1] also determine the number of bits that
willbe usedfor the special character comparison.Bit0in the X-registers corresponds
with the LSB bit for the receive character.
6.9 Hardware/software and time-out interruptsThree special interrupts have been addedto monitor the hardware and software flow
control. The interrupts are enabled by IER[5-7]. Care must be taken when handling
these interrupts. Following a reset, if the transmitter interrupt is enabled, the
SC16C554/554D will issuean interruptto indicate that the Transmit Holding Register
is empty. This interrupt must be serviced prior to continuing operations. The LSR
register provides the current singular highest priority interrupt only. It could be noted
that CTS and RTS interrupts have lowest interrupt priority. A condition can exist
where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s).
Only after servicing the higher pending interrupt will the lower priority CTS/TRS
interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C554/554D FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-State interrupt operation. This is accomplished by
INTSEL and MCR[3]. When INTSEL interface pin is left open or made a logic0,
MCR[3] controls the 3-State interrupt outputs, INTA-INTD. When INTSELisa logic1,
MCR[3] has no effect on the INTA-INTD outputs, and the package operates with
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6.10 Programmable baud rate generatorThe SC16C554/554D supports high speed modem technologies that have increased
input data ratesby employing data compression schemes. For example,a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate. 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as
requiredfor supportinga5 Mbit/s data rate. The SC16C554/554D canbe configured
for internal or external clock operation. For internal clock oscillator operation, an
industry standard microprocessor crystal (parallel resonant/22-33 pF load) is
connected externally between the XTAL1 and XTAL2 pins (see Figure7).
Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (see Table7).
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate.
Table 7: Baud rate generator programming table using a 7.3728 MHz clock200 2304 900 09 00
1200 384 180 01 80
2400 192 C0 00 C0
4800 96 60 00 60
9600 48 30 00 30
19.2k 24 18 00 18
38.4k 12 0C 00 0C
76.8k 6 06 00 06
153.6k 3 03 00 03
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
6.11 DMA operationThe SC16C554/554D FIFO trigger level provides additional flexibility to the user for
block mode operation. LSR[5,6] provide an indication when the transmitter is empty hasan empty location(s). The user can optionally operate the transmit and receive
FIFOsin the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled
and the DMA modeis de-activated (DMA Mode 0), the SC16C554/554D activates the
interrupt output pin for each data transmit or receive operation. When DMA mode is
activated (DMA Mode 1), the user takes the advantage of block mode operation by
loading or unloading the FIFO in a block sequence determined by the preset trigger
level.In this mode, the SC16C554/554D sets the interrupt output pin when characters
in the transmit FIFOs are below the transmit trigger level, or the characters in the
receive FIFOs are above the receive trigger level.
6.12 Sleep modeThe SC16C554/554D is designed to operate with low power consumption. A special
sleep mode is included to further reduce power consumption when the chip is not
being used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C554/554D
enters the sleep mode, but resumes normal operation when a start bit is detected, a
changeof stateon anyof the modem input pins RX, RI, CTS, DSR, CD,ora transmit
datais providedby the user.If the sleep modeis enabled and the SC16C554/554Dis
awakened by one of the conditions described above, it will return to the sleep mode
automatically after the last character is transmitted or read by the user. In any case,
the seep mode will not be entered while an interrupt(s) is pending. The
SC16C554/554D will stayin the sleep modeof operation untilitis disabledby setting
IER[4] to a logic 0.
6.13 Loop-back modeThe internal loop-back capability allows on-board diagnostics.In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally. MCR[0-3] register bits are usedfor controlling loop-back diagnostic testing.
In the loop-back mode, OP1 and OP2 in the MCR register (bits 2-3) control the
modem RI and CD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are
usedto control the modem DSR and CTS inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see Figure 8). The CTS, DSR,
CD, andRI are disconnected from their normal modem control input pins, and instead
are connected internallyto RTS, DTR, OP2 and OP1. Loop-back test datais entered
into the transmit holding register via the user data bus interface, D0-D7. The transmit
UART serializes the data and passes the serial data to the receive UART via the
internal loop-back connection. The receive UART converts the serial data back into
parallel data that is then made available at the user data interface D0-D7. The user
optionally compares the received data to the initial transmitted data for verifying
error-free operation of the UART TX/RX circuits. this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read
using lower four bits of the Modem Status Register (MSR[0:3]) instead of the four
Modem Status Register bits 4-7. The interrupts are still controlled by the IER.
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder Register descriptionsTable 8 details the assigned bit functions for the SC16C554/554D internal registers.
The assignedbit functions are more fully definedin Section 7.1 through Section 7.11.
[1] The value shown represents the register’s initialized HEX value; X= n/a.
[2] These registers are accessible only when LCR[7]=0.
[3] The Special Register set is accessible only when LCR[7] is set to a logic1.
Table 8: SC16C554/554D internal registersShaded bits are only accessible when EFR[4] is set.
General Register Set[2]
Special Register Set[3]
Enhanced Register Set[4]
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.1 Transmit (THR) and Receive (RHR) Holding RegistersThe serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR
register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic0= FIFO full; logic1= at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive datais removed from the SC16C554/554D and receive FIFOby reading the
RHR register. The receive section provides a mechanism to prevent false starts. On
the falling edgeofa startor false start bit,an internal receiver counter starts counting
clocks at the 16× clock rate. After 7-1 ⁄2 clocks, the start bit time should be shifted to
the center of the start bit. At this time the start bit is sampled, and if it is still a logic0
it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA-INTD output pins in the 16 mode, or on wire-OR IRQ
output pin in the 68 mode.
Table 9: Interrupt Enable Register bits description IER[7] CTS interrupt.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C554/554D issues an
interrupt when the CTS pin transitions from a logic 0 to a logic1. IER[6] RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C554/554D issues an
interrupt when the RTS pin transitions from a logic 0 to a logic1. IER[5] Xoff interrupt.
Logic 0 = Disable the software flow control, receive Xoff interrupt
(normal default condition).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See
Section 6.7 “Software flow control” for details. IER[4] Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic1= Enable sleep mode. See Section 6.12 “Sleep mode”for details. IER[3] Modem Status Interrupt.
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.2.1 IER versus Receive FIFO interrupt mode operationWhen the receive FIFO (FCR[0]= logic 1), and receive interrupts (IER[0]= logic1)
are enabled, the receive interrupts and register status will reflect the following:
The receive data available interrupts are issued to the external CPU when the
FIFO has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the
FIFO trigger level is reached. Both the ISR register status bit and the interrupt will
be cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the
shift register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus Receive/Transmit FIFO polled mode operationWhen FCR[0]= logic 1, resetting IER[0:3] enables the SC16C554/554D in the FIFO
polled modeof operation. Since the receiver and transmitter have separate bitsin the
LSR, eitheror both canbe usedin the polled modeby selecting respective transmitor
receive control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
LSR[7] will indicate any FIFO data errors. IER[2] Receive Line Status interrupt.
Logic 0 = Disable the receiver line status interrupt (normal default
condition).
Logic 1 = Enable the receiver line status interrupt. IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever
the THR is empty, and is associated with LSR[1].
Logic 0 = Disable the transmitter empty interrupt (normal default
condition).
Logic 1 = Enable the transmitter empty interrupt. IER[0] Receive Holding Register interrupt. This interrupt will be issued when the
FIFO has reached the programmed trigger level, or is cleared when the
FIFO drops below the trigger level in the FIFO mode of operation.
Logic 0 = Disable the receiver ready interrupt (normal default condition).
Logic 1 = Enable the receiver ready interrupt.
Table 9: Interrupt Enable Register bits description…continued
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.3 FIFO Control Register (FCR)This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive
FIFO trigger levels, and select the DMA mode.
7.3.1 DMA mode
Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C454 mode. Transmit Ready (TXRDY) willtoa logic0 wheneveran empty transmit spaceis availablein the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3 = 1): Set and enable the interruptina block mode operation. The
transmit interrupt is set when there are one or more FIFO locations empty. The
receive interrupt is set when the receive FIFO fills to the programmed trigger level.
However, the FIFO continuestofill regardlessof the programmed level until the FIFO
is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the
programmed trigger level.
7.3.2 FIFO mode
Table 10: FIFO Control Register bits description7:6 FCR[7:6] RCVR trigger. These bits are usedtoset the trigger levelfor the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equalsthe programmed trigger level. However, the FIFOwill continueto
be loaded until it is full. Refer to Table 11.
5:4 FCR[5:4] Not used; initialized to logic0. FCR[3] DMA mode select.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C554/554D is in the16C450 mode (FIFOs disabled; FCR[0]= logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0]= logic1; FCR[3]= logic0), and when there are
no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C554/554D is inmode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic1;
FCR[3]= logic0) and thereisat least one characterin the receive FIFO,
the RXRDYpin willbea logic0. Once active, the RXRDYpin willgotoa
logic 1 when there are no more characters in the receiver.
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Transmit operationin mode ‘1’: When the SC16C554/554Disin FIFO
mode (FCR[0] = logic 1; FCR[3]= logic 1), the TXRDY pin will be a
logic1 whenthe transmit FIFOis completely full.It willbea logic0if one
or more FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C554/554D is in FIFOmode (FCR[0]= logic1; FCR[3]= logic1) and the trigger level has been
reached,ora Receive Time-Out has occurred, the RXRDYpin willgoto
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO. FCR[2] XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO. FCR[1] RCVR FIFO reset.
Logic 0 = No FIFO receive reset (normal default condition).
Logic1= Clearsthe contentsof the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO.
This bit must be a
‘1’ when other FCR bits are written to, or they will not be
programmed.
Table 11: RCVR trigger levelsTable 10: FIFO Control Register bits description…continued
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.4 Interrupt Status Register (ISR)The SC16C554/554D provides six levelsof prioritized interruptsto minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performinga read cycleon the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits.T able12 “Interrupt source” shows the data values
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 12: Interrupt source 0 00110LSR (Receiver Line Status
Register) 0 00100 RXRDY (Received Data
Ready) 0 01100 RXRDY (Receive Data
time-out) 0 00010 TXRDY (T ransmitter
Holding Register Empty) 0 00000 MSR (Modem Status
Register) 0 10000 RXRDY (Received Xoff
signal) / Special character 1 00000CTS, RTS change of state
Table 13: Interrupt Status Register bits description7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
Logic 0 or cleared = default condition.
5:4 ISR[5:4] INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that oncesettoa logic1, the ISR[4]bit will staya
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
3:1 ISR[3:1] INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 12).
Logic 0 or cleared = default condition. ISR[0] INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Philips Semiconductors SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
7.5 Line Control Register (LCR)The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 14: Line Control Register bits description LCR[7] Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch and enhanced feature register enabled. LCR[6] Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic0
state). This condition exists until disabled by setting LCR[6] to a
logic0.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition. LCR[5] Set parity. If the parity bit is enabled, LCR[5] selects the forced
parity format. Programs the parity conditions (see Table 15).
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a
logical 1 for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a
logical 0 for the transmit and receive data. LCR[4] Even parity. If the parity bit is enabled with LCR[3] set to a logic1,
LCR[4] selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be
programmed to check the same format (normal default
condition).
Logic 1 = EVEN Parity is generated by forcing an even number
of logic 1s in the transmitted data. The receiver must be
programmed to check the same format. LCR[3] Parity enable. Parity or no parity can be selected via this bit.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during the transmission,
receiver checks the data and parity for transmission errors. LCR[2] Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see Table 16).
Logic 0 or cleared = default condition.
1:0 LCR[1:0] Word length bits1,0. These two bits specify the word lengthtobe
transmitted or received (see Table 17).
Logic 0 or cleared = default condition.
