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SC16C2550PHIN/a72avaiDual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
SC16C2550IB48PHILIPSN/a2avaiDual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
SC16C2550IN40PHN/a376avaiDual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder


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SC16C2550-SC16C2550IB48-SC16C2550IN40
Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs
and infrared (IrDA) encoder/decoder
Rev. 03 — 19 June 2003 Product data Description

The SC16C2550 is a 2 channel Universal Asynchronous Receiver and T ransmitter
(UART) used for serial data communications. Its principal function is to convert
parallel data into serial data and vice versa. The UART can handle serial data rates
up to 5 Mbits/s.
The SC16C2550 is pin compatible with the ST16C2550. It will power-up to be
functionally equivalent to the 16C2450. The SC16C2550 provides enhanced UART
functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The
DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and
RXRDY signals. On-board status registers provide the user with error indications and
operational status. System interrupts and modem control features maybe tailoredby
software to meet specific user requirements. An internal loop-back capability allows
on-board diagnostics. Independent programmable baud rate generators are provided
to select transmit and receive baud rates.
The SC16C2550 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature
range, and is available in plastic PLCC44, LQFP48 and DIP40 packages. Features 2 channel UART5 V, 3.3 V and 2.5 V operation Industrial temperature range Pin and functionally compatible to 16C2450 and software compatible with
INS8250, SC16C550 Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbits/s at 2.5V 16 byte transmit FIFO to reduce the bandwidth requirement of the external CPU 16 byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU Independent transmit and receive UART control Four selectable Receive FIFO interrupt trigger levels Automatic software/hardware flow control Programmable Xon/Xoff characters Software selectable Baud Rate Generator Sleep mode Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break) Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Fully programmable character formatting: 5-, 6-, 7-, or 8-bit characters Even-, Odd-, or No-Parity formats 1-, 11 ⁄2-, or 2-stop bit Baud generation (DC to 1.5 Mbit/s) False start-bit detection Complete status reporting capabilities 3-State output TTL drive capabilities for bi-directional data bus and control bus Line Break generation and detection Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, DCD). Ordering information
Table 1: Ordering information

SC16C2550IN40 DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
SC16C2550IA44 PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
SC16C2550IB48 LQFP48 plastic low profile quad flat package; 48 leads; body 7×7× 1.4 mm SOT313-2
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder Block diagram
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder Pinning information
5.1 Pinning
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
5.2 Pin description
Table 2: Pin description
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Table 2: Pin description…continued
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Table 2: Pin description…continued
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder Functional description

The SC16C2550 provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data thatis required with digital data systems. Synchronizationfor
the serial data stream is accomplished by adding start and stop bits to the transmit
datato forma data character (character orientated protocol). Data integrityis insured attachinga paritybitto the data character. The paritybitis checkedby the receiver
for any transmissionbit errors. The electronic circuitryto provideall these functionsis
fairly complex, especially when manufacturedona single integrated silicon chip. The
SC16C2550 represents such an integration with greatly enhanced features. The
SC16C2550 is fabricated with an advanced CMOS process.
The SC16C2550 is an upward solution that provides a dual UART capability with bytesof transmit and receive FIFO memory, insteadof nonein the 16C2450. The
SC16C2550 is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performance is
realized in the SC16C2550 by the transmit and receive FIFOs. This allows the
external processorto handle more networking tasks withina given time. For example,
the ST16C2450 without a receive FIFO, will require unloading of the RHR in microseconds (this example usesa character lengthof11 bits, including start/stop
bits at 115.2 kbits/s). This means the external CPU will have to service the receive
FIFO less than every 100 microseconds. However, with the 16 byte FIFO in the
SC16C2550, the data buffer will not require unloading/loading for 1.53 ms. This
increases the service interval, giving the external CPU additional time for other
applications and reducing the overall UART interrupt servicing time. In addition, the
four selectable receive FIFO trigger interrupt levelsis uniquely providedfor maximum
data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the
external controlling CPU, increases performance, and reduces power consumption.
The SC16C2550 is capable of operation up to 5 Mbits/s with a 80 MHz clock. With a
crystal or external clock input of 7.3728 MHz, the user can select data rates up to
460.8 kbits/s.
The rich feature set of the SC16C2550 is available through internal registers.
Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem
interface controls areall standard features. Followinga power-on resetoran external
reset, the SC16C2550 is software compatible with the previous generation,
ST16C2450.
6.1 UART A-B functions

The UART provides the user with the capabilityto bi-directionally transfer information
betweenan external CPU, the SC16C2550 package, andan external serial device.A
logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data,
and/or receive data via UART channels A-B. Individual channel select functions are
shown in Table3.
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
6.2 Internal registers

The SC16C2550 provides two sets of internal registers (A and B) consisting of registers each for monitoring and controlling the functions of each channel of the
UART . These registers are shown in Table 4. The UART registers function as data
holding registers (THR/RHR), interrupt status and control registers (IER/ISR),a FIFO
control register (FCR), line status and control registers (LCR/LSR), modem status
and control registers (MCR/MSR), programmable data rate (clock) control registers
(DLL/DLM), and a user accessible scratchpad register (SPR).
[1] These registers are accessible only when LCR[7] is a logic0.
[2] These registers are accessible only when LCR[7] is a logic1.
[3] Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF(HEX)’.
Table 3: Serial port selection

CSA-CSB=1 none
CSA=0 UART channel A
CSB=0 UART channel B
Table 4: Internal registers decoding
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
[1] 0 0 Receive Holding Register Transmit Holding Register 0 1 Interrupt Enable Register 1 0 Interrupt Status Register FIFO Control Register 1 1 Line Control Register 0 0 Modem Control Register 0 1 Line Status Register n/a 1 0 Modem Status Register n/a 1 1 Scratchpad Register Scratchpad Register
Baud rate register set (DLL/DLM)
[2] 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 1 MSB of Divisor Latch MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)
[3] 1 0 Enhanced Feature Register Enhanced Feature Register 0 0 Xon1 word Xon1 word 0 1 Xon2 word Xon2 word 1 0 Xoff1 word Xoff1 word 1 1 Xoff2 word Xoff2 word
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
6.3 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but
not the transmit trigger level. The receiver FIFO section includes a time-out function
to ensure data is delivered to the external CPU. An interrupt is generated whenever
the Receive Holding Register (RHR) has not been read following the loading of a
character or the receive trigger level has not been reached.
6.4 Hardware flow control

When automatic hardware flow controlis enabled, the SC16C2550 monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C2550 will suspend TX transmissionsas soonas the stopbitof the characterin
process is shifted out. T ransmission is resumed after the CTS input returns to a
logic 0, indicating more data may be sent.
With the Auto RTS function enabled,an interruptis generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will returntoa logic0 after the data buffer (FIFO)is unloadedto the next trigger level
below the programmed trigger. However, under the above described conditions, the
SC16C2550 will continue to accept data until the receive FIFO is full.
6.5 Software flow control

When software flow control is enabled, the SC16C2550 compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2
character value(s). If received character(s) match the programmed values, the
SC16C2550 will halt transmission (TX) as soon as the current character(s) has
completed transmission. Whena match occurs, the receive ready(if enabled via Xoff
IER[5]) flags willbe set and the interrupt output pin(if receive interruptis enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C2550 will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C2550 will resume operation and
clear the flags (ISR[4]).
Reset initially sets the contentsof the Xon/Xoff 8-bit flow control registerstoa logic0.
Following reset, the user can write any Xon/Xoff value desired for software flow
Table 5: Flow control mechanism
4 1 8 4 8 12 8 14 14 10
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder

the SC16C2550 compares two consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described flow control mechanisms, flow control
characters are not placed (stacked) in the user accessible RX data buffer or FIFO. the event that the receive bufferis overfilling and flow control needstobe executed,
the SC16C2550 automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C2550 sends the Xoff1,2 characters as
soon as received data passes the programmed trigger level. To clear this condition,
the SC16C2550 will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.
6.6 Special feature software flow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software flow control shouldbe turnedoff when using this special
mode by setting EFR[0-3] to a logic0.
The SC16C2550 compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table 7) shows each X-Register with eight bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or bits. The word length selected by LCR[0-1] also determine the number of bits that
willbe usedfor the special character comparison.Bit0in the X-registers corresponds
with the LSB bit for the receive character.
6.7 Hardware/software and time-out interrupts

The interrupts are enabled by IER[0-3]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit1= 1, the
SC16C2550 will issue a Transmit Holding Register interrupt. This interrupt must be
serviced prior to continuing operations. The LSR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts
have lowest interrupt priority. A condition can exist where a higher priority interrupt
may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher
pending interrupt will the lower priority CTS/RTS interrupt(s)be reflectedin the status
register. Servicing the interrupt without investigating further interrupt conditions can
result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C2550 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder

receive holding register (RHR) is read. The actual time-out value is 4 character time,
including data information length, start bit, parity bit, and the size of stop bit, i.e., 1×,
1.5×, or 2× bit times.
6.8 Programmable baud rate generator

The SC16C2550 supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate. 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s. The SC16C2550 can support a standard data rate of
921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capableof operating witha frequencyofupto80 MHz.To obtain maximum data rate,
it is necessary to use full rail swing on the clock input. The SC16C2550 can be
configured for internal or external clock operation. For internal clock oscillator
operation, an industry standard microprocessor crystal is connected externally
between the XTAL1 and XT AL2 pins. Alternatively, an external clock can be
connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates (see Table6).
The generator divides the input 16× clock by any divisor from 1 to 216− 1. The
SC16C2550 divides the basic external clock by 16. The basic 16× clock provides
table rates to support standard and custom applications using the same system
design. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for
the MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 6 shows the selectable baud rate table available when using a 1.8432 MHz
external clock input.
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
6.9 DMA operation

The SC16C2550 FIFO trigger level provides additional flexibility to the user for block
mode operation. LSR[5,6] provide an indication when the transmitter is empty or has empty location(s). The user can optionally operate the transmit and receive FIFOs
in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and
the DMA modeis de-activated (DMA Mode0), the SC16C2550 activates the interrupt
output pin for each data transmit or receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the receive trigger level and
the transmit FIFO.In this mode, the SC16C2550 sets the TXRDY (or RXRDY) output
pin when charactersin the transmit FIFOis below 16,or the charactersin the receive
FIFOs are above the receive trigger level.
6.10 Loop-back mode

The internal loop-back capability allows on-board diagnostics.In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally (see Figure 6). MCR[0-3] register bits are used for controlling loop-back
diagnostic testing.In the loop-back mode, the transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally. The CTS, DSR, CD, and RI are disconnected from
their normal modem control inputs pins, and instead are connected internallyto RTS,
DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the
transmit holding register via the user data bus interface, D0-D7. The transmit UART
Table 6: Baud rate generator programming table using a 1.8432 MHz clock
2304 900 09 00 1536 600 06 00
110 1047 417 04 17
150 768 300 03 00
300 384 180 01 80
600 192 C0 00 C0
1200 96 60 00 60
2400 48 30 00 30
3600 32 20 00 20
4800 24 18 00 18
7200 16 10 00 10
9600 12 0C 00 0C
19.2k 6 06 00 06
38.4k 3 03 00 03
57.6k 2 02 00 02
115.2k 1 01 00 01
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder

data thatis then made availableat the user data interface D0-D7. The user optionally
compares the received data to the initial transmitted data for verifying error-free
operation of the UART TX/RX circuits. this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
Fig 6. Internal loop-back mode diagram.

TXA, TXB RXA, RXB
XTAL2XTAL1
D0–D7
IOR
IOW
RESET
A0–A2
CSA, CSB
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
CTSA, CTSB
RTSA, RTSB
DSRA, DSRB
DTRA, DTRB
RIA, RIB
(OP1A, OP1B)
CDA, CDB
(OP2A, OP2B)
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder Register descriptions

Table 7 details the assigned bit functions for the SC16C2550 internal registers. The
assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
[1] The value shown in represents the register’s initialized HEX value; X= n/a.
[2] Accessible only when LCR[7] is logic0.
Table 7: SC16C2550 internal registers

Shaded bits are only accessible when EFR[4] is set.
General Register Set
[2]
Special Register Set
[3]
Enhanced Register Set
[4]
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the TSR and UART via the THR, providing that the THR is empty. The THR empty
flag in the LSR register will be set to a logic 1 when the transmitter is empty or when
datais transferredto the TSR. Note thata write operation canbe performed when the
THR empty flag is set (logic0= at least one byte in FIFO/THR, logic1= FIFO/THR
empty).
The serial receive section also containsan 8-bit Receive Holding Register (RHR) and Receive Serial Shift Register (RSR). Receive datais removed from the SC16C2550
and receive FIFO by reading the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge of a start or false start bit, an
internal receiver counter starts counting clocks at the 16× clock rate. After 7-1⁄2
clocks, the startbit time shouldbe shiftedto the centerof the start bit.At this time the
start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assemblinga false character. Receiver status
codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA, INTB output pins.
Table 8: Interrupt Enable Register bits description
IER[7] CTS interrupt.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C2550 issues an
interrupt when the CTSpin transitions froma logic0toa logic1. IER[6] RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C2550 issues an
interrupt when the RTSpin transitions froma logic0toa logic1. IER[5] Xoff interrupt.
Logic0= Disable the software flow control, receive Xoff interrupt
(normal default condition).
Logic1= Enable the software flow control, receive Xoff interrupt. IER[4] Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. IER[3] Modem Status Interrupt. This interrupt will be issued whenever
there is a modem status change as reflected in MSR[0-3].
Logic 0 = Disable the modem status register interrupt (normal
default condition).
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0]= logic 1), and receive interrupts (IER[0]= logic1)
are enabled, the receive interrupts and register status will reflect the following: The receive RXRDY interrupt (Level2 ISR interrupt)is issuedto the external CPU
when the receive FIFO has reached the programmed trigger level.It willbe cleared
when the receive FIFO drops below the programmed trigger level. Receive FIFO status will alsobe reflectedin the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit
and the interrupt will be cleared when the FIFO drops below the trigger level. The receive data ready bit (LSR[0]) is set as soon as a character is transferred
from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is
empty. When the T ransmit FIFO and interrupts are enabled, an interrupt is generated
when the transmit FIFO is empty due to the unloading of the data by the TSR and
UART for transmission via the transmission media. The interrupt is cleared either
by reading the ISR register, or by loading the THR with new data characters. IER[2] Receive Line Status interrupt. This interrupt will be issued
whenever a receive data error condition exists as reflected in
LSR[1-4].
Logic 0 = Disable the receiver line status interrupt (normal
default condition).
Logic 1 = Enable the receiver line status interrupt. IER[1] T ransmit Holding Register interrupt. In the 16C450 mode, this
interrupt will be issued whenever the THR is empty, and is
associated with LSR[5]. In the FIFO modes, this interrupt will be
issued whenever the FIFO is empty.
Logic0= Disable the Transmit Holding Register Empty (TXRDY)
interrupt (normal default condition).
Logic 1 = Enable the TXRDY (ISR level 3) interrupt. IER[0] Receive Holding Register. In the 16C450 mode, this interrupt will
be issued when the RHR has data, or is cleared when the RHR is
empty. In the FIFO mode, this interrupt will be issued when the
FIFO has reached the programmed trigger leveloris cleared when
the FIFO drops below the trigger level.
Logic 0 = Disable the receiver ready (ISR level 2, RXRDY)
interrupt (normal default condition).
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
Table 8: Interrupt Enable Register bits description…continued
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0]= logic 1, resetting IER[0-3] enables the SC16C2550 in the FIFO
polled mode of operation. In this mode, interrupts are not generated and the user
must poll the LSR register for TX and/or RX data status. Since the receiver and
transmitter have separate bits in the LSR either or both can be used in the polled
mode by selecting respective transmit or receive control bit(s). LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. LSR[1-4] will provide the type of receive errors, or a receive break, if encountered. LSR[5] will indicate when the transmit FIFO is empty. LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty. LSR[7] will show if any FIFO data errors occurred.
7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1 DMA mode
Mode 0 (FCR bit 3 = 0):
Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) on
PLCC44 and LQFP48 packages willgotoa logic0 whenever the FIFO (THR,if FIFO
is not enabled) is empty. Receive Ready (RXRDY) on PLCC44 and LQFP48
packages willgotoa logic0 whenever the Receive Holding Register (RHR)is loaded
with a character.
Mode 1 (FCR bit 3 = 1):
Set and enable the interruptina block mode operation. The
transmit interrupt is set when the transmit FIFO is empty. TXRDY on PLCC and
LQFP48 packages remainsa logic0as longas one empty FIFO locationis available.
The receive interrupt is set when the receive FIFO fills to the programmed trigger
level. However, the FIFO continuestofill regardlessof the programmed level until the
FIFO is full. RXRDY on PLCC44 and LQFP48 packages transitions LOW when the
FIFO reaches the trigger level, and transitions HIGH when the FIFO empties.
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
7.3.2 FIFO mode
Table 9: FIFO Control Register bits description

7-6 FCR[7]
(MSB),
FCR[6]
(LSB)
RCVR trigger. These bits are used to set the trigger level for the
receive FIFO interrupt.
Logic 0 (or cleared) = normal default condition.
Logic 1 = RX trigger level.
An interrupt is generated when the number of characters in the
FIFO equals the programmed trigger level. However, the FIFO will
continue to be loaded until it is full. Refer to Table 10.
5-4 FCR[5-4] Not used; initialized to logic0. FCR[3] DMA mode select.
Logic 0 = Set DMA mode ‘0’
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C2550 is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO
mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and
when there are no characters in the transmit FIFO or transmit
holding register, the TXRDY pin in PLCC44 or LQFP48 packages
will be a logic 0. Once active, the TXRDY pin will go to a logic1
after the first character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C2550 is in

mode‘0’ (FCR[0]= logic0),orin the FIFO mode (FCR[3]= logic0)
and there is at lease one character in the receive FIFO, the
RXRDY pin will be a logic 0. Once active, the RXRDY pin on
PLCC44 and LQFP48 packageswillgotoa logic1 when there are
no more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C2550 is in

FIFO mode (FCR[0]= logic1; FCR[3]= logic1), the TXRDYpinon
PLCC44 and LQFP48 packages willbea logic1 when the transmit
FIFO is completely full. It will be a logic 0 if one or more FIFO
locations are empty.
Receive operationin mode ‘1’:
When the SC16C2550isin FIFO
mode (FCR[0]= logic1; FCR[3]= logic1) and the trigger level has
been reached, or a Receive Time-Out has occurred, the RXRDY
pin on PLCC44 and LQFP48 packages will go to a logic 0. Once
activated,it willgotoa logic1 after there areno more charactersin
the FIFO. FCR[2] XMIT FIFO reset.
Logic 0 = Transmit FIFO not reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets
the FIFO counter logic (the transmit shift register is not cleared altered). Thisbitwill returntoa logic0 after clearing the FIFO.
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
7.4 Interrupt Status Register (ISR)

The SC16C2550 provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performinga read cycleon the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. A lower level interrupt may be seen after
servicing the higher level interrupt and re-reading the interrupt status bits. Table 11
“Interrupt source” shows the data values (bits 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels. FCR[1] RCVR FIFO reset.
Logic 0 = Receive FIFO not reset (normal default condition).
Logic1= Clears the contentsofthe receive FIFO and resets the
FIFO counter logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO. FCR[0] FIFOs enabled.
Logic0= Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must
be a ‘1’ when other FCR bits are written to, or they will not
be programmed.
Table 10: RCVR trigger levels

Table 9: FIFO Control Register bits description…continued
Table 11: Interrupt source 0 00110LSR (Receiver Line Status
Register) 0 00100 RXRDY (Received Data
Ready) 0 01100 RXRDY (Receive Data
time-out) 0 00010 TXRDY (T ransmitter
Holding Register Empty) 0 00000 MSR (Modem Status
Register) 0 10000 RXRDY (Received Xoff
signal) / Special character
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 12: Interrupt Status Register bits description

7-6 ISR[7-6] FIFOs enabled. These bits aresettoa logic0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic1
when the FIFOs are enabled in the SC16C2550 mode.
Logic 0 or cleared = default condition.
5-4 ISR[5-4] INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that oncesettoa logic1, the ISR[4]bit will staya
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
3-1 ISR[3-1] INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 11).
Logic 0 or cleared = default condition. ISR[0] INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
Table 13: Line Control Register bits description
LCR[7] Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled. LCR[6] Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic0
state). This condition exists until disabled by setting LCR[6] to a
logic0.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
5-3 LCR[5-3] Programs the parity conditions (see Table 14). LCR[2] Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see Table 15).
Logic 0 or cleared = default condition.
1-0 LCR[1-0] Word length bits1,0. These two bits specify the word lengthtobe
transmitted or received (see Table 16).
Logic 0 or cleared = default condition.
Philips Semiconductors SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
Table 14: LCR[5-3] parity selection
X 0 no parity 0 1 ODD parity 1 1 EVEN parity
001forced parity ‘1’
111forced parity ‘0’
Table 15: LCR[2] stop bit length
5, 6, 7, 8 1 1-1⁄2 6, 7, 8 2
Table 16: LCR[1-0] word length

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