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SC14404BFLAGNSN/a30avaiComplete Baseband Processor for DECT Handsets
SC14404BFLBCNSCN/a17avaiComplete Baseband Processor for DECT Handsets


SC14404BFLAG ,Complete Baseband Processor for DECT HandsetsGeneral Descriptionn 3V upto 5.0V battery monitor input.The SC14404 is a CMOS chip optimized to han ..
SC14404BFLBC ,Complete Baseband Processor for DECT HandsetsFeatureswhich supports 1.152 MHz, 0.576 MHz and 0.288 MHzbit rates.n Integrated DECT Baseband trans ..
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SC14404BFLAG-SC14404BFLBC
Complete Baseband Processor for DECT Handsets
SC14404
Complete Baseband Processor for DECT Handsets
General Description

The SC14404 is a CMOS chip optimized to handle all the
audio, signal and data processing needed within a DECT
handset. An ADPCM transcoder, a very low power CO-
DEC and Analog Frontend is integrated. Direct connec-
tions towards microphone and a (dynamical) loudspeaker
are provided. Duplex quality handsfree operation is inte-
grated.
The SC14404 is designed to fit to any radio design.
A dedicated TDMA controller handles all physical layer
slot formats and radio control.
National Semiconductors standard CompactRISCTM
CR16B 16 bit microcontroller takes care of all the higher
protocol stack. 4 kilobyte Flash is integrated for parameter
and number storage.
Features
Integrated DECT Baseband transceiver optimized for
GAP handsets according to ETS 300 175-2, 175-3 &
175-8. Two on board low drop voltage regulators with 2.85V
and 3.0- 3.8V (with external resistors the voltage can be
determined) output. 2V upto 3.6V battery input with onboard step up con-
verter. 3V upto 5.0V battery monitor input. Advanced battery management unit Very low power in active and paging mode. Embedded 16 bit CompactRISCTM Micro Controller.
(CR16B) with programmable clock speeds. 4k byte memory mapped Flash 320 kbyte Flash or factory programmed ROM FLASH. ACCESSBUSTM or MICROWIRETM interfaces 5,5 kilobyte on-chip Data Memory. One full duplex ADPCM transcoder. On-chip 14-bit linear CODEC. 14 upto 44 dB gain differential microphone input buffer. 100 Ω loudspeaker driver. Software controlled gain on audio input and output. Peak hold ADC for RSSI measurement. Five general purpose inputs can be multiplexed on an
8 bit ADC with selectable ranges. On-chip dedicated TDMA instruction co-processor
which supports 1.152 MHz, 0.576 MHz and 0.288 MHz
bit rates. Seven programmable control signals for radio front
end. Full a nd double slot, protected and unprotected B-
fields. Duplex quality handsfree operation. Tone generator. Tones consisting of 3 frequencies can
be programmed Linear PCM interface for external codec.
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System Diagram
PRELIMINARY

FEBRUARY 2000
440
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