SC11372CQ ,V(dd): 6V; 10mA; 500mW; mobile radio analog processorapplications. Application of the IC will allow equip-
ment makers to use the same baseband circuit ..
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SC11487CV , HiCOLOR-16 Color Palette
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SD46520 ,stock - 400KHZ 2A STEP-DOWN DC-DC CONVERTER
SD46520 ,stock - 400KHZ 2A STEP-DOWN DC-DC CONVERTER
SD46520 ,stock - 400KHZ 2A STEP-DOWN DC-DC CONVERTER
SD4701 , RF & MICROWAVE TRANSISTORS CELLULAR BASE STATION APPLICATIONS
SD4870TR ,stock - CURRENT MODE PWM CONTROLLER
SD5001N , HIGH SPEED DMOS FET ANALOG SWITCHES AND SWITCH ARRAYS
SC11372CQ
V(dd): 6V; 10mA; 500mW; mobile radio analog processor
NNational Semiconductor
SC11372
Mobile Radio Analog Processor
General Description
The $011372 is a CMOS integrated circuit designed to per-
form the baseband signal processing for multi-standard mo-
bile radio applications. Application of the IC will allow equip-
ment makers to use the same baseband circuitry in a range
of PMR products and therefore reduce device inventory.
The main function of the IC is the processing of audio sig-
nals, however, low frequency signaling functions used for
control and data transmission are also included. Additional
functions such as clock generation, A to D and D to A con-
versions are added to further enhance the system flexibility
of the device. To limit the power consumption, many of the
circuit blocks can be powered down until required. Circuitry
for a variety of different trunk messaging systems is inte.
grated which makes the IC especially suited to low power,
multi-standard equipment.
An RC serial bus interface is provided for simple control by
an external microprocessor allowing the circuit configuration
and gain control circuits to be user programmed and moni-
tored.
Features
I: All receive and transmit filtering plus gain control for
half duplex audio communications
Automatic level control
DTMF transmitter
Programmable clock generator with CPU output
8-bit DAC output
l2C Bus Interface
6/8-bit ADC on board
FFSK 12/400 modem
CTCSS transceiver
SELCALL transceiver
NR2 sub-audio transceiver for DCS systems
Low power 5V CMOS
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$011372
DESCRIPTION
FEATURES
BLOCK DIAGRAM
CONNECTION DIAGRAM
PIN CONNECTIONS
1.0 INTRODUCTION
2.0 ABSOLUTE MAXIMUM RATINGS
2.1 Operating Conditions
2.2 DC Electrical Characteristics
3.0 AUDIO SIGNAL
3.1 Inputs and Outputs
3.2 Gain Control Circuits
3.3 Microphone Amplifiers
3.4 Pre-Emphasis
3.5 Automatic Level Control
3.6 High Pass Filter F5
3.7 Limiter
3.8 Low Pass Filter F8
3.9 Gain Control GC7
3.10 Da-Emphasis Circuit
Table of Contents
4.0 SIGNALING (TRANSMIT)
4.1 Sub-Audio Encoder
NR2 Mode
CTCSS Mode
. Example
4.2 Tone Generators for SELCALL and DTMF
4.3 FSSK Transmitter
Control of FFSK Signal Generation
4.4 Alert Tone Generator
5.0 SIGNALING (RECEIVE)
5.1 FFSK Receiver/Detector
Circuit Configurations
FFSK Receiver
Received Data Buffer
FFSK Detector
5.2 Sub-Audio Detection
NR2 Detection
CTCSS Detection
5.3 SELCALL Detection
6.0 MISCELLANEOUS
6.1 Reference Buffers
6.2 DA Convertor
6.3 AD Convertor and Rectifier
6.4 Crystal Oscillator and Clock Circuitry
7.0 SERIAL BUS INTERFACE AND LOGIC CONTROL
8.0 $011372 REGISTER MAP
REVISION CHANGES
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List of Figures
FIGURE I. Pre-Emphasis Frequency Response (F6, F7)
FIGURE 2. ALC Circuit Characteristics
I FIGURE 3. Filter F5a Frequency Response
- FIGURE 4. Response of F5 (both sections)
FIGURE 5. Filter F8 Frequency Response
FIGURE 6. De-Emphasis Frequency Response
FIGURE 7. Synchronization of NR2 Signal
FIGURE 8. Timing of FFSK Transmit Signals
FIGURE 9. Timing of RXCLK and RXDAT Signals
FIGURE 10. Timing of Signals in FIFO Mode
FIGURE 11. Control of DA Converter
FIGURE 12. Control of AD Convertor
List of Tables
TABLE I Absolute Maximum Ratings
TABLE II Operating Conditions
TABLE Iil DC Characteristics
TABLE IV Current Consumption (IVDD + IAVD) in p.A
TABLE V Audio Signal Level? and Characteristics
TABLE VI Gain Control Programming Table
TABLE VII Microphone Amplifier Specification
TABLE VIII Automatic Level Control Circuit Characteristics
TABLE IX Limiter Clipping Levels
TABLE X
TABLE XI Tone Generators
TABLE XII FFSK Signal Specification
TABLE XIII
TABLE XIV
TABLE XV Reference Offset Voltage Programming
TABLE XVI Sub-Audio Detection
TABLE XVII SELCALL Detector Specification
TABLE XVIII Reference Circuit Specification
TABLE XIX DA Convertor Specification
TABLE XX Specification of ADC and Rectifier
TABLE XXI CLKOUT Frequencies
TABLE XXII Specification of Oscillator and CLOCKOUT Signal
TABLE XXIII Characteristics of SDA and SCL Inputs/Outputs
TABLE XXIV Interrupt Source Selection
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SC11372
NIC1_IN
MIC2_0
MIC2_IN
SU8_l/0
MIC1-0
CONVIN YC
LIMO LIM! COMPEX
CONTROL
0-+12d8
52(0) 53
3 °‘_l 25‘ +0
016 dB I *0
‘ +8dB
0-+12dB
‘ TONE-G1 —%~
0-+12d9
sums 6?
0-+12d9
‘ Ljum
+ SUMZ If
°.— AVD
Block Diagram
— REFZ
"- REF1
-3915d8
TONE-GZ
L532 F7
0-+12dB
-39 tGdH
AL ERT
F FSKUT
51s [(«-| Z§——~Rxoun
_ s ccm
[0"““' " ‘ —»Rxou12
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TXCIJ< rrsx
TXDATA
D . SERIAL
A INTERFACE
W~Tx0u12
TXOUT 1
CONTROL DlVlDER
BIAS 0P_0UT 0P_POS
DEMOD TXS TX DAT
DTOA SCL SDA SEL
RESETB TEST
CLKOUT
TL/W/12625-1
Connection Diagram
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1-:lii.tg'isiiiiirs,i?iliit-,
I I I l I I I I I I
-f" 43 42 4140 39 38 37 36 35 34
SCL 1 33 - XRX
SOh - 2 32 - RXIN
RXCLK - 3 31 - VMID
RXOAT - 4 50 F-- REFI
CLKOUT -1 5 29 - REF2
SEL - 6 SC11372CQ 28 - Ixoun
V00_ 7 27 - TXOUTZ
l/ss - 8 25 - Rxoun
XIN - 9 25 - Txourz
TEST - 10 24 - TC
SUB_i/o - 11 23 - CONVIN
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Pin Connections
Pin ' Name Type Description
1 SCL l Clock Line for Serial Bus
2 SDA I/O Data Line for Serial Bus
3 FIXCLK vo FFSK Clock Output/FIFO Control Input
4 RXDAT O FFSK Data Output
5 CLKOUT 0 Output of Programmable Clock Generator
6 SEL t Select Input for Bit A[1] of the IC Address
7 Von S Positive Power Supply for Logic Circuits
8 Vss S Negative Power Supply Pin for Logic Circuits
9 XIN I Connection for Crystal/Input for Clock Signal
10 TEST l Test Mode Select Input
1 1 SUB__|/O l/O Input/Output of Sub-Audio Circuit
12 CD 0 Output of FFSK Detector
13 TXDAT I Data Input of FFSK Transmitter/Auxiliary Analog Input
14 BIAS I Input for Reference Voltage for Comparators
15 OP_POS I Input for External Phase Equalizer
16 OP_OUT C) Output for External Filter
17 AVS S Negative Power Supply for Analog Circuitry
18 AVD s Positive Power Supply for Analog Circuitry
19 DEMOD O Output of Low Pass Filter F12
20 CEXT I/O Connection for External Capacitor of FFSK Detector
21 TXS O TXCLK from FFSK Transmitter/SELCALL
22 DTOA C) DAC Output
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$011372
Pin Connections (Continued)
Pin ' Name Type Description
23 CONVIN I ' Input for ADC
24 TC l/O Connection for External Capacitor for Rectifier Time Constant
25 RXOUT2 0 Output to Loudspeaker Amplifier
26 RXOUT1 . 0 Output to Loudspeaker Amplifier
27 TXOUT2 0 Output to Modulator
28 TXOUT1 0 Output to Modulator
29 REF2 0 Connection for Reference Voltage Decoupling
30 REF1 0 Connection for Reference Voltage Decoupling
31 VMID I/O Mid Supply Unbuffered Reference Voltage
32 RXIN I input for Demodulated Signal
33 XRX l/O Input to Pre-Emphasis, Rectifier/Output of Received Signal
34 EXP1 I Input for Expanded Audio Signal
35 COMPI I Input for Compressed Audio Signal
36 COMPEX 0 Output for Audio Expander/Output for Audio Compressor
37 MIC1_O 0 Output for Microphone Pre-Amplifier Opamp
38 MIC1_IN I Negative Input of Microphone Pre-Amplifier Opamp
39 MIC2_|N l Negative Input of Microphone Pre-Amplifier' Opamp
40 MIC2_O _ 0 Output of Microphone Pre-Amplifier Opamp
41 LIMI l Input of Internal Limiter
42 LIMO 0 Output for Additional External Limiter
43 RESETB _ l Reset Input
44 INTB O Interrupt Output
1.0 Introduction
This datasheet is divided up into sections corresponding to the functional blocks of the tC.
In the specifications of the circuit blocks described, it is assumed that the operating conditions of Table II are met. Where
absolute voltages, frequencies and delays are specified, it is assumed that. the typical operation conditions are met (e.g.,
V00 = W). . .
Register locations are referred to in this document using codes like reg.KL, blz:xl, which means that the bits 2, y and x of the
register with hexadecimal address KL are addressed. Another notation used is: reg. KL:FFH. This means that hex code FF is
written into register KL. _
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2.0 Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Ottitte/
Distributors for availability and specifications.
TABLE I. Absolute Maximum Ratings
Description Condition Min Max Units
Power Supply Voltage VDD-Vss. AVD-Avs 6 V
Voltage on Any Pin Vss-0.3 VDD+ 0.3 V
Current at Any Pin Except Power Supply Pins 10 mA
Storage Temperature - 65 + 150 I
Package Power Dissipation @25''C 500 mW
2.1 OPERATING CONDITIONS
TABLE II. Operating Conditions
Description Condition Min Typ Max Units
Ambient Temperature (TA) - 25 25 85 "C
Positive Supply Voltage VDD, AVD Referred to RESP Vss, AVS 4.75 5 5.25 V
Frequency at XIN Pin 11.0592 MHz
2.2 DC ELECTRICAL CHARACTERISTICS
The current consumption of the $011372 is mostly depen-
dent on the parts of the circuit which are activated using
power control register OB. Table III specifies the current
consumption after power-on reset (sleep mode: register OB
is programmed to 00H), the current at full circuit operation
and the minimum active mode current. Minimum active
mode current, is the minimum current needed if functions
other than the basic IC functions are activated after power-
on reset. This current-which includes lD0--should be add-
ed to the current consumption of the activated blocks ac-
cording to Table IV.
Sleep Mode Functions:
Active Mode Functions:
TABLE III. DC Characteristics
- Crystal oscillator.
- Divider (in + 2 mode) and
clock driver of CLOCKOUT pin.
- Serial interface.
- Switches.
- All sleep mode functions.
- Both reference voltage buffers.
...-. Gain control GC2.
- De-emphasis circuit Fl,
- DC-biasing circuits.
ZASl-l-OS
Description Condition Min Typ Max Units
Digital High Level (Vm. VOH) Inputs and Outputs 0.7'VDD V
Digital Low Level (VIL, VOL) Inputs and Outputs 0.3'VDD V
Sleep Mode Current (ld0) Fteg. 13: A8H (IVDD + IAVD) 950 1200 ”A
Min Active Mode Current (Ids) (IVDD + IAVD) 1550 1900 p.A
Max Supply Current' (IVDD + IAVD) 14.5 mA
'Note: Registers programmed as follows: Reg OB:FFH, Reg OC,b[4]:1
TABLE IV. Current Consumption (IVDD + IAVD) in pA
Progr. Code Function(s) Min Typ Max
reg.OB: 01H Sub-Audio rx 600 750
reg.0B: 02H FFSK Dt + F11 850 1000
reg.0B: 04H FFSK Detect + F11 1250 1500
reg.OB: 08H Audio Processing 5500 6800
reg.OB: 10H Alert and Tone Generators 950 1150
reg.0B: 20H Sub-Audio tx 1350 1650
reg.0B: 40H FFSK tx 800 1000
reg.OB: 80H DAC, ADC, Rectifier 1600 1900
reg.OC, b4:1 Selcall rx 400 500
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$011372
3.0 Audio Signal Processing
In this section the main characteristics of the different audio
signal processing functions of the IC are described and
specified.
Note: Except where otherwise stated, all signal levels and other characteris-
tits reler to inputs and outputs of the described blocks (see Block
Diagram, page 4).
3.1 INPUTS AND OUTPUTS
Because the circuit is intended for half duplex systems,
there is a common signal path for both transmit and receive
mode. In transmit mode a signal path containing micro-
phone amplifiers, gain control and filtering can be selected.
Two outputs (T XOUT1, TXOUT2) with independent level
controls for line setting of the frequency deviation are avail.
able for connection to the modulator of the radio. One of
these outputs (TXOUT2) has the option to invert the signal.
Using both outputs, it is possible to set up dual point modu-
lation.
The received signal can be filtered using the filter sections
provided. Two outputs (RXOUT1, RXOUT2) are also avail-
able for connection to loudspeaker amplifiers. Although
both outputs can share the same gain control circuit (GC7),
the signal levels at RXOUT1 and RXOUT2 can be set inde-
pendently in 6 dB and 12 dB ranges respectively.
A number of audio inputs and outputs are available to con-
nect external circuitry like a scrambler/descrambler or a
compander:
.- COMPEX, output to connect a scrambler or compander
- COMPI, input for scrambled or compressed signal.
- LIMO, output for external Iimiter circuit.
- LlMl, input for off chip processed signal.
- EXPI, input for descrambled or expanded signal.
- TXDAT, additional analog input combined with data input
pin of FFSK transmitter.
All analog inputs have integrated high ohmic paralleI-resis-
ters to permit easy AC coupling of signals. Input for RXIN
has a special option. The input resistance can be set to a
tow value of 2 kn. This feature can be used for fast dis-
charging of the input coupling capacitor under serial bus
control if large DC voltage shifts occur. The outputs are low-
ohmic. Buffers at the output pins are capable of driving load
resistances as jow as 2 kn without introducing significant
signal distortion.
Table V specifies the characteristics of the analog input and
output pins and the signal quality characteristics. Noise and
distortion levels are specified for a typical transmit configu-
ration as well as a typical receive configuration for the IC. To
calculate the S/N, it is assumed that the nominal signal lev-
el at the RXIN input is 50 mVrms in the receive mode In
transmit mode a nominal signal level of 24 mVrms at the
input of GOD is assumed. These nominal levels correspond
to 60% deviation of the RF signal.
circuit.
TABLE V. Audio Signal Levels and Characteristics i
Description Condition/Pin Min Typ Max Units
Input Resistance MIC1_in MIC2_in 100 Mit
DC Level MIC1_in, MIC2_in vss VDD V
Input Resistance COMPI, EXPI, LIMI, TXDAT (Notes1, 6) 200 k0
DC Level COMPI, EXPI, LlMl, TXDAT (Notes 1, 6) 2.4 2.5 2.6 V
Load Resistance COMPEX, RTXOUT1-2. RXOUT1-2 2 kn
Load Resistance LIMO 100 _ kn
Load Capacitance _ COMPEX, TXOUT1-2, RXOUT1-2 100 pF
Load Capacitance LIMO 2O _ pF
_ Input DC Flange All Audio Inputs and Gain Controls 0.5 3.5 _ V
Output DC Range All Audio Outputs 0.75 4.25 V
_S/N, Pre-Emphasized (Note 2) GC0 _ TXOUT1, CCITT Weighted 52 . 58 dB
S/N, No Pre-Emphasized (Note 2) G00 - TXOUT1, CCITT Weighted 54 60 dB
S/N, De-Emphasize" (Note 3) RXIN - RXOUTI, CCITT Weighted 60 66. dB
S/N, No De-Emphasized (Note 3) RXIN - RXOUT1, CCITT Weighted I 62 68 dB
Distortion (THD) . Signal at TXOUT1: 1 Vrms, 1 kHz (Note 4) 0.5 %
Distortion (T HD) Signal at RXOUT1: 1. 25 Vrms, 1 kHz (the 5) 0.5 %
Note i.. Pin TXDAT is only an analog input if selected using switch s8 (reg. OB, b[6]).
Note 5: Signal path and gain settings as in Note 3, except for G011. GG11
Note 6: II summlng circuit is selected trom LIMI or EXPl pin, then Rm > 35 kn.
Note 2: At TXOUT1. GCO = 5.6 dB, 601 = 3.2 dB, F5a and F8 active G07 = 0 dB, 608 = 2.2 dB. TXOUT1: 267 mVrms.
Note 3. At HXOUT1. G02 "'"-'' 5.6 dB, F5a and F8 active, GOT = 6 dB, GC11 -- 3.2 dB. RXOUT1: 690 mes.
Hole 4: Signal path and gain settings as in Note 2, except for 607 and GC8. 607 = 6 dB, G68 = 4 dB. Limiter disabled.
= 4 dB.
Limiter disabled.
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3.0 Audio Signal Processing (Continued)
3.2 GAIN CONTROL CIRCUITS
Four types of gain control are available to adapt the signal
levels, These gain controls can be used to set the nominal
and maximum frequency deviation of the radio unit and to
control the volume of the Ioudspeaker(s). The amplitude ra-
tio of the different signals is also adjustable using the pro-
grammable gain control circuits. Table VI shows the control
codes, ranges and tolerances of the different types of gain
controls.
3.3 MICROPHONE AMPLIFIERS
To amplify the microphone signals low noise operational
amplifiers are available on-chip. The opamp inverting inputs
and both opamp outputs are connected to IC pins. Using
external resistors, these opamps can be configured as in-
verting amplifiers. This configuration will also allow the use
of feedback capacitors to limit the bandwidth of the input
amplifiers and so minimize the aliasing of high frequency
noise in subsequent sampling circuits. In Table VII the oper-
ational amplifier specification is summarized.
TABLE VI. Galn Control Programming Table
Control Code PGAOG PGA3906 PGA04 PGA12
0dB-+6dB --39di3-+6di3 0dB-+44dB 0dB-+12dB
0000 0.0 - 39 0.0 0
0001 0.4 - 36 0.3 0.8
0010 0.8 -33 0.5 1.6
0011 1.2 -30 0.8 2.4
0100 1.6 -27 1.1 3.2
0101 2.0 -24 1.3 4.0
0110 2.4 -21 1.6 4.8
0111 2.8 -18 1.9 5.6
1000 3.2 - 1 5 2.2 6.4
1001 3.6 - 12 2.4 7.2
1010 4.0 - 9 2.7 8.0
101 1 4.4 - 6 3.0 8.8
1100 4.8 - 3 3.2 9.6
1 101 5.2 0 3.5 10.4
1 1 10 5.6 3 3.8 11 .2
1 1 1 1 6.0 6 4.0 12.0
Tolerance :to.1 dB , 0.4 dB $0.1 dB i 0.2 dB
TABLE VII. Microphone Amplifier Spettltleatlon
Description Condition Min _ Typ Max Units
Open Loop Voltage Gain HLOAD > 20 kit 100 dB
Unity Gain Bandwidth 1.5 MHz
Phase Margin CLOAD < 30 pF 60 tt
Load Resistance 20 kit
Load Capacitance Unity Gain Configuration ' 30 pF
Output Voltage RLOAD > 20 kn Avs+ 0.1 Avo-- 0.1 V
input Offset Voltage Maximum -4 4 mV
Input Noise Voltage F = 1 Hz 500 nWTz
F = 10 kHz 20 nvirTz
Power Supply Rejection F = 1 kHz 65 dB
Common Mode Rejection F = 1 kHz 100 dB
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$011372
3.0 Audio Signal Processing (Continued)
3.4 PRE-EMPHASIS
A first order high pass filter with characteristics as.dispiayed
in Pre-emphasis frequency response (F6, F7) is integrated
to pre-emphasize the signal as needed in Phase Modulation
radio systems. The filter is positioned between gain control
600 and the Automated Level Control circuit.
3.5 AUTOMATIC LEVEL CONTROL
To prevent over-deviation of the modulator, when high am-
plitude audio signals are to be transmitted, an Automatic
Level Control function is integrated. The ALC is implement-
ed as a variable gain/loss circuit that will become active if _
the input signal amplitude exceeds a certain threshold volt- _
age VTH (113 mVp). The amplitude of signals exceeding this"
threshold will be controlled to tight limits. The output ampli-
tude will stay inside an 0.6 dB wide band for the whole con-
trol range (26 dB) of the ALC circuit. Figure 2 shows the
relation between input and output signal.
Note: Gain control G00 has a limited (DC) input voltage range (see Table
IO, which limits the input signal amplitude at the input of G00 to 1 Vp
for undistorted signal ampMtratjon. GCO should therefore be set to a
suffitimtly high gain, if'the whole gain control range of the ALC is to
be used.
The gain of the ALC circut in the linear range is typically
2 dB. No external components are needed to set the attack
and decay time constants of the ALC. Under serial bus con-
trol both time constants can be set over a wide range
(reg.15). The attack time can be set between 0.46 ms and
59.3 ms while the decay-to-attack time ratio can be pro-
grammed between 4 and 8192.
Note: Decay and attack time constants are defined as the time needed tor
the output of the ALC to recover after the input signal level has
changed plus or minus 20 dB inside the active control range of the
ALC circuit.
A control bit (reg.15, b[3]) is reserved that forces the ALC
circuit to change the output level only at zero crossings of
the signal, For details about programming the time con-
stants see Section 8, register map.
20 T s-CCC']:
10 as,o'ii"
+8.5dB/5 kHz
Gain (d8)
s,,;,;;;;;';'"''''"'"
too 631 1.58k 3.98k 10k
Frequency (Hz)
TL/W/12825-4
FIGURE 1. Pre-Emphasls Frequency Response (F6, F7)
(iiffiiit) t<6.0de
g 2di? , ,
-10d8 OdB 10dB 20dB 26di)
113mVp
Input Voltage T
F TL/WM2826-6
FIGURE 2. ALC Circuit Characteristics
TABLE VIII. Automatic Level Control Circuit Characteristics
Description Condition Min Typ Max . _Units
ALC Control Threshold VTH Defined at ALC Input 100 113 125 mVp
Nominal Output Level (Note 1) VIN s VTH Inside Cohtrol Range 100 mVrms
Control Range 26 dB
Nominal Step Size 0.2 0.4 ' 0.6 tit,
Distortion (Note 1) vm < 1.6 Vrms f 0.5 %
ALC Gain VIN < VTH 1.8 2 2.2 dB
Attack Time 0.46 59.3 ms
Decay-to-Attack Time Ratio 4 8192
Note 1: input signal is 1 kHz sine wave signal.
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3.0 Audio Signal Processing (Continued)
3.6 HIGH PASS FILTER F5
Filter F5 consists of two sections, F5a and F5b. Filter F5a is
4th order with a 24 dB/octave characteristic below the cut-
off frequency. This will provide adequate attenuation of low
frequency signals in systems where no sub-audio signaling
is used. For systems where sub-audio signals are present,
more attenuation is needed at low frequencies and for this
reason filter F5b is available. When F5b is switched into the
signal path (reg.01, b[7]), the two filters in series will provide
more than 35 dB attenuation for signals below 250 Hz. The
response curves of filter F5a and the combination filter F5
are shown in filter F5a frequency response, and Response
of F5 (both sections), respectively.
At the input of filter F5, the signal is amplified 8 dB to im-
prove the signal to noise ratio and adapt the transmit audio
level to the limiter clipping voltage.
OdB/t kHz +0.5dB
-5 -O.5dB 300Hz
-23d8/
Ei" 150Hz
100 25t 631 1.58k 3.98k 10k
Frequency (Hz)
TL/W/12825-6
FILTER 3. Filter F5a Frequency Response
+idi1 OdB/l kHz
5 I -ldB/300Hz
a -35dB/
Ct 25on
38 75.4 189 475 1.19k 3k
Frequency (Hz)
TL/W/12825-7
FIGURE 4. Response of F5 (both sections)
3.7 LIMITER
A limiter with a hard limiting characteristic is positioned just
before low pass filter F8. The clipping level is chosen so
that the output voltage is limited to 1 Vpp. Over-deviation of
the modulator will be prevented, even in the case of ampli-
tude excursions which are faster than the ALC attack time, if
the limiter is in the signal path. Switch S5 (reg.0D, b[1:0])
can be used to bypass the limiter.
The LlMO/LIMI pair of pins allows external AC coupling of
the signal to the limiter circuit.
3.8 LOW PASS FILTER F8
The function of low pass filter F8 is to limit the audio band-
width to ensure that components of the modulated signal do
not appear in adjacent radio channels. The bandwidth of the
filter can be set to either 3 kHz or 2.55 kHz for narrow band
systems (reg.0D, b[7]).
+0.5dB OdB/l kHz
-5 -0.5d8 2.5kHz _
-1.8dil ,
A 3kHz
fl', EkHz
c: -2n
too 251 631 1.58k 3.98k 10k
Frequency (Hz)
TL/W/12825-8
FIGURE 5. Filter F8 Frequency Response
Filter F8 is a fourth order Iowpass with 24 dB/octave attenu-
ation at high frequencies. At the corner frequency of 3 kHz
(or 2.55 kHz) the maximum attenuation is 1.8 dB, while at
6 kHz attenuation of 20 dB is provided. In Figure 5, the filter
response for 10 kHz bandwidth is shown. A second order
low pass smoothing filter at the output of F8 removes high
frequency signal components so that the signals at the
transmit outputs TXOUTt and TXOUT2 do not require addi-
tional filters before they are applied to the modulator stages
of the radio.
3.9 GAIN CONTROL GCT
Gain control GC7 has course steps and can be used to
control the transmit signal level as well as to set the volume
level of the received audio signal. GC? has 16 steps and a
control range of -39 dB to +6 dB, The signal at the input
of GO? can also be routed directly to gain control G010 in
order to provide a constant level output signal at RXOUT2.
3.10 DE-EMPHASIS CIRCUIT
The demodulated audio signal is applied to the RXIN input.
Before the signal goes to the sampled circuits on the IC, an
on-chip anti aliasing filter removes high frequency noise.
TABLE IX. Limiter Clipping Levels
Description Condition Min Typ Max Units
Negative Clipping Level AVD-AVS = 5.00V 1.98 2 2.02 V
Positive Clipping Level Avro-Aus = 5.00V 2.97 3 3.02 V
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3.0 Audio Signal Processing (Continued)
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FIGURE 6. De-Emphasls Frequency Response
Filter FI-a first order low pass filter-is used to de-empha-
size the signal applied to the RXIN input. De-emphasis fre-
quency response shows the transfer characteristics of filter
4.0 Signaling (Transmit)
Signals for several different signaling schemes can be gen-
erated using the SC11372. Examples are:
- FFSK 1200
- FFSK 2400
- CTCSS
- SELCALL
- NR? sub-audio
To generate the required signals, four signal generators ate
integrated namely an FFSK generator, a subfaudio signal
generator and two general purpose sinewave generators.
One of the general purpose generators can be used to pro-
duce SELCALL tohes. If both generators are used, then
DTMF signals can also be generated. In addition to these
signaling circuits, a square wave generator is available
which can be used for alert tones. A pre-emphasis circuit
(F7) with characteristics identical to F6 is available to pro-
cess the generated signaling tones. In the next sections the
characteristics of the signaling circuits are described/r)
more detail.
4.1 SUB-AUDIO ENCODER
Both CTCSS tones and Non Return to Zero (NR2) signals'
can be generated by the same circuit. CTCSS signals are
generated under serial bus control only, while for NRZ sig-
nal generation the data input (SUB_.I/O pin) will be needed
to apply the data signal. The frequency of the CTCSS tones
and the. baud rate of the NR2 signals are defined using the
same 10 control bits, programmed at register locations
reg. 02, b[7: 6] and reg. 03, b[7: ol. The generated frequency
F of a CTCSS tone and the baud rate B of an NRZ signal for
a programmed number n are respectively;
F= 57600/(n+ 1) Hz and B = 115200/(n+ 1) baud
If n = o, then the output frequency will be zero.
A 4th order lowpass filter is part of the signal path of the sub
audio encoder. The bandwidth can be programmed (200 Hz
or 300 Hz) using the same control bits as filter F3; reg. 13,
bm, (see also Section 5.2 NRZ detection).
NRZ MODE
Two modes of operation are available to control NFIZ signal
generation, synchronous and asynchronous mode (reg.02,
b[3:2]). In both modes the SUB_I/O pin should be config-
ured as ah input pin (reg.02, b[4]). lf asynchronous mede is
selected, lbgie NRZ signals should be applied to the SUB_
" input. The edges of the logic signal at the SUB_I/O
input will then be shaped and the amplitude will be reduced
to 80 mVpp. Prior to signal generation, the baud rate must
be programmed in order to obtain the correct signal shap-
Data at SULI/O pin
INTb Pulses
Synchr. data signal
Shaped NRZ signal
TL/Wf12825-1 0
FIGURE 7. Synchronization of NRZ Signal
ln synchronous mode, the data signal should also be ap-
plied to the SUB_I/O input. The circuit will then synchro-
nize the signal at this pin to the programmed baud rate.
Because the interrupt pin is used in synchronous mode, the
sub-audio-tx circuit should first be selected as the interrupt
source by programming reg.13, biol, At the INTB pin, a
pulse of 8.7 us will be generated to signal that data has
been read by the circuit, on the negative edge of the INTB
signal. New data should be applied to the SUB_I/O pin
100 ps after the INTB pulse started and within the baud rate
period time. Just like in asynchronous mode the timing,
TABLE X
Description Condition Min F Typ Max Units
CTCSS Frequency Inaccuracy (Note 1) 0.2 %
Amplitude At Input of GC6 25 28.5 32 mVrms
Harmonic Distortion (< 3 kHz) at TXOUT1 GC6 = 5.6 dB, G07 and G08: 0 db -45 dB
Frequency Range t 67 250.3 Hz .
NR2 Signal Amplitude V at Input of tics 72 80 88 mVpp
Signal Components 300 Hz-3000 Hz 606 = 5.6 dB, G07 and G08: 0 dB -42 dB
Baud Rate 300 bps
Note 1: A signal frequency of exactly 11.0592 MHz is assumed at pin XlN.
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4.0 Signaling (Transmit) (Continued)
pulse shaping and amplitude control will be performed by
the circuitry on chip, Synchonization of NRZ signal shows
the relation of the signals in synchronous mode. In both
modes the baud rate is set by programming halt the baud
rate frequency in the control registers (reg.02 and 03).
CTCSS MODE
In CTCSS mode, selected by programming reg.02. b[3:2],
the circuit generates a sinewave with the programmed fre-
quency. Harmonic components in the audio band are re-
moved from the signal in the filtering sections of the CTCSS
generator. Using control bit (reg.02, b[2]). it is possible to
invert the generated signal. The signal inversion will be-
come effective at the first zero crossing of the signal after
programming of the control bit.
EXAMPLE
For a data rate of 134 baud or a CTCSS frequency of 67 Hz,
a division factor of 859 should be programmed according to
the given formulas. This is done by writing code 01011011
and It to registers 03, b[7:0] and 02, b[7:6] respectively. If
synchronous mode is selected by writing 01 to address
02[3:2]. then new data must be applied to the SUB__l/O pin
between 100 its and 7462 ps after the pulse at pin INTB
started.
4.2 TONE GENERATORS FOR SELCALL AND DTMF
A programmable, tone generator is available to generate
tones for signaling systems such as SELCALL. Two such
circuits are integrated on the SC11372. Two circuits allow
the synthesis of DTMF tones too. To add the signals, a
summing circuit is available. Because the frequency of. the
generator is freely programmable in the range from
337.5 Hz to 3000 Hz, the circuit can also be used for other
purposes like the generation of pilot tones or warning tones.
Frequencies are generated digitally using a programmable
11-bit divider. A low pass filter removes harmonic frequency
components. resulting in a clean output spectrum.
TABLE XI. Tone Generators
Description Condition Min Typ Max Units
Frequency Range 337.5 3000 Hz
Frequency Tolerance -0.2 0.2 %
Distortion (THD) No Pre-Emphasis 0.5 %
Distortion (THD) Pre-Emphasized 1 %
Output Level (Low) 63 71.5 80 mVrms
Output Level (High) 300 357.5 400 mVrms
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Note 1: DC = Don’t care, DV = Data Valid.
Note 2: Typical period time tor TXCLK: 833 us (1200 Ed). 417 us (2400 Ed).
Note 3: Delay without pro-emphasis at TXOUT1: 180 "ss-MO p5.
FIGURE 8. Timing of FFSK Transmit Slgnals
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4.0 Signaling (Transmit) (Continued)
The division factor of the tone generator(s) can be pro-
grammed using registers 04, 05 and 06. The frequency gen-
erated is calculated using formula F = 691200/(n+ 1), in
which n is the programmed division factor. There is one
exception. It n=0, then the output frequency is zero. A
change of frequency will only occur when all 11 frequency
control bits have been modified. Therefore it is important
that both registers are always written, first the MSB register,
then the LSB register. The output amplitude df both genera-
tors can be set independently to a high or a low level (regis-
ter 04).
4.3 FSSK TRANSMITTER '
The FFSK transmitter circuit can be used to generate either
1200 baud or 2400 baud FFSK signals. ireg.t2, bhl), For
1200 baud the logic 1 and 0 are represented by a full 1200
Hz period and one and a half 1800 Hi period respectively. If
the 2400 baud mode is selected, then a full 2400 Hz period
represents logic 0, while half a 1200 H2 period represents
logic 1. The circuit is built around a sinewave generator,
which is capable of changing the frequency of the generat-
ed signal at zero crossings. Therefore the genera-
a FFSK signals have low distortion with respect to both
amplitude and phase. .
CONTROL OF FFSK SIGNAL GENERATION
The generation of FFSK signals is controlled using the
TXDAT input, the TXS output and the serial interface. Be-
fore the FFSK transmitter can be used, switch s30 (reg.0C,
b[4:3]) must be programmed. The power control bit must
also be set (reg.0B, b[6]). Switch s8 automatically selects
the output of the FFSK transmitter. Internally the TXDAT
and TXS pins are connected to the TXDATA and TXCLK
connections of the FFSK transmitter circuit. -
The start of FFSK signal generation is initiated if reg.02, b[5]
is reset (FFSK transmit enable signal). The acknowledge
signal, generated by the serial interface in this condition, will
start the TXCLK signal to be used by the microcontroller to
synchronous the data signal at the TXDAT pin of the
8011372. Figure 8 shows the timing of the signals for FFSK
signal generation.
Note: The power control signal should stay high at least one bit period long-
er than the FFSK transmit enable signal, to ensure that the FFSK
signal is completed and stops at the signal zero crossing.
TABLE XII. FFSK Signal Specification
Description Condition Min . Typ Max q . Units
Baud Rate (Note 1) Reg.12, bl = 0 1200 Baud
Baud Rate(Note 1) Reg.12, b1 = 1 2400 Baud
Output Level of Sinewave At Output of s8 95 109 I 120 mVrms
Distortion (THD) Filter F8 is Active I 0.5 _ %
Distortion (THD) Filter F8 is Bypassed 1 %
Note 1: The frequency at XIN is 11.0592 MHz. The baud rate is lineany dependent on the frequency at the XIN pin.
4.4 ALERT TONE GENERATOR
A tone generator capable of producing square wave signals
is available to produce alert tones. The frequency is defined
using a 6-bit programmable divider. Register 14, bi5:0] must
be programmed for this purpose.
If a (decimal) number n is programmed, than the frequency
F = 10800/(n+1)
For n-- 0, the output frequency is zero.
TABLE XIII
Description Condition Min Typ Max Units
Frequency Range F at XIN Pin: 11.0592 MHz 168.75 5400 Hz
Amplitude at the Output of sum4 0.9 1 1.1 Vpp
Amplitude at the Output of sum5 0.85 0.95 1.05 Vpp
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5.0 Signaling (Receive)
Circuitry is integrated on the 3011372 for the detection and
decoding of signals used in different signaling systems. Be-
cause modern microcontrollers are able to do most of the
decoding by software, required analog functions like gain
blocks, filters and comparators are integrated for systems
using sub-audio signals and for the SELCALL system. Flex-
ible interfacing to the microcontroller is provided to minimize
the required hardware for different processor types and to
keep the overall power consumption as low as possible. For
systems using FFSK signaling not only is an FFSK receiver
integrated but also an FFSK detector that can detect the
presence of an FFSK carrier.
Details of the functionality and control of the signaling de-
code circuits is described in the next few sections.
5.1 FFSK RECEIVER/DETECTOR
The main function of the FFSK receiver is to demodulate
FFSK signals and to provide a bit stream at its output for
further processing. The parallel connected FFSK detector
has the task to detect if a valid FFSK signal is present. If an
FFSK signal is detected then the CD pin will assume a logic
high level. This signal can be used as an indication to the
microcontroller to start reading the bit stream from the
FFSK receiver. Because of the large time constant (typically
5 ms) needed to reliably detect an FFSK carrier, the first bits
in thistream (in 2400 baud systems) could be lost before
the microcontroller starts reading the bit stream, To prevent
this, the SC11372 features a 9-bit shift register which is
clocked at the FFSK baud rate and can be read at a higher
speed by the controller. Both the FFSK receiver and detec-
tor can be used for 1200 baud and 2400 baud FFSK signals.
The baud rate must be set by programming reg.12 b[1].
CIRCUIT CONFIGURATIONS
Although the circuits used to demodulate the FFSK signal
are essentially the same for both baud rates, the signal pre-
processing requires different circuit configurations, This is
mainly due to the wider bandwidth needed for the 2400
baud FFSK signal. After the signal at the RXIN input is
adapted and the signal is de-emphasized using filter F1, two
signal routes can be selected (s28: reg.12, bl61) before the
signal is applied to the FFSK receiver and detector:
1. For 1200 baud signals filter F11 should be selected. This
filter selects the frequency band from 900 Hz to 2100 Hz
and amplifies the signal 21 dB, This signal path is only
useful for 1200 baud signals.
2. Low pass filter F12 (3 kHz bandwidth, 2nd order re-
sponse) also provides 21 dB gain. The inverting amplifier
behind the filter can be used to implement a phase equal-
izing filter using external components. Switch s29' (reg.12,
b[7]) can select either the internal reference voltage of
the IC or an external voltage applied to the BIAS pin. It
the amplified and filtered FFSK signal has excessive DC
offset or (non signal related) very low frequency compo-
nents, then the signal at the op_out pin can be externally
low pass filtered and fed to the BIAS pin. This voltage will
then serve as signal reference for the comparators in the
FFSK detector and receiver.
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Note 1: Typical delay 1.8 ms (1200 Bd), 0.9 ms (2400 Bd),
Nate 2: For 1200 Ed: 798 ps FIGURE 9. Timing of RXCLK and RXDAT Signals
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5.0 Signaling (Receive) (Continued)
This second signal path will be the choice for 2400 Baud
signals and/or for 1200 Baud FFSK signals, which have suf-
fered from strong signal distortion during transmission.
For measurement purposes, or if external FFSK demodula-
tion is used, Schmitt trigger ST2 (specified in the SELCALL
rx block description) can also be used to digitize FFSK sig-
nals. To make use of this option, switch s29a (controlled by
the same signal as s29) must be used.
FFSK RECEIVER
In the FFSK receiver circuit, the filtered signal is damodulat-
ed. The extracted data is then synchronized to the recov-
ered clock signarusing a DPLL. The lock range of the DPLL
circuit is i 1/24 of the selected baud rate (1200 Hz or
2400 Hz). Synchronized clock and data signals are available
at the RXCLK and RXDAT pins of the IC.
Figure 9 shows the timing of the RXCLK and RXDAT signals
in relation to the FFSK signal at the input of the FFSK re-
ceiver circuit for 1200 baud and 2400 baud data rate. If this
"transparent" mode is selected, these signals are available
at the RXCLK _and RXDAT pins of the IC.
RECEIVED DATA BUFFER
By programming reg.14. b[6] the circuit changes from the
"transparent" data mode to the buffered mode, "FIFO
mode." The RXCLK and RXDAT pins have different serial
interface functions and the RXCLK pin is configured as an
input pin and the RXDAT output has two functions, status
output and data output.
The data buffer, which is implemented as a First in First Out
register, has a serial data input connected to the data output
(intRXDAT) of the FFSK receiver. On negative edges of the
synchronized clock signal coming from the FFSK receiver
(intRXCLK), data bits from the receiver are clocked into the
FIFO register. The FIFO can be read out in sequence under
control of the signal at the RXCLK' input. At the negative
going edge of the signal applied to the RXCLK pin, the
"first" data bit in the FIFO register is available at the RXDAT
pin. At the positive going edge of the RXCLK signal the
status of the FIFO is made available at the RXDAT pin:
Status = 0, the next data bit can be read from the FIFO.
Status = 1, no new data available (FIFO is "empty").
Status and Dattrinformation can be read from the RXDAT
RXCLK = o, Data can be read from the RXDAT output.
RXCLK = 1, Status can be read from the RXDAT output.
Figure to shows how data can be read from the FIFO buffer
register.
Note 1: tl, t2 < 5 ye.
Note 2: intRXCLK and intRXDAT are output ttignals of the FFSK receiver.
Signals extRXCLK and extFtXDAT appear at the RXGLK and RXDAT pins
respectively.
intRXCLK
Transparent Mode FIFO Mode
extRXCLK . J
extRXOAT X ST
TL/W/12825-13
FIGURE 10. Timing of Signals in FIFO Mode
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5.0 Signaling (Receive) (Continued)
The interrupt pin INTB can be used to make effective use of
the data buffer.
Mode 1: If reg.11, b[4] is l, then the INTB pin will output an
8.7 ’15 interrupt pulse, to signal that the FIFO buff-
er is almost full, B bits are shifted into the FlFO
register. This means that in two bit periods minus
10 us data must be read from the FIFO in order to
prevent data being shifted out of the FIFO and lost.
Because the FIFO is 9 bits wide, at least 8 data
bits can be read after the interrupt is activated.
Mode 2: If reg.11, b[4] is 0, then the INTB pin will output an
8.7 11.8 interrupt pulse, when the status signal goes
low and a data bit is shifted into the FIFO, under
the condition that the FIFO was empty.
In Section 7 the use of the interrupt pin is described in more
detail.
FFSK DETECTOR
The FFSK detector is connected in parallel to the FFSK
receiver. Output pin CD will assume a logic high level if a
1200 baud or 2400 baud FFSK signal is detected (depend-
ing on the mode selected). The value of the external capaci-
tor (nominal value: 22 nF), connected at the Cext pin, deter-
mines the time constant of the detector (nominal 5 ms).
5.2 SUB-AUDIO DETECTION
For sub-audio signal detection a low pass filter and a pro-
grammable bandpass filter are integrated. A Schmitt trigger
converts the filtered signal into a square wave signal to be
decoded by the microcontroller. The interrupt pin (INTB) can
be used to interface with the microcontroller. Three interrupt
modes are available:
Mode l. Interrupts are generated on rising edges of the
SUB_|/O output signal.
Interrupts are generated on falling edges of the
SUB_I/O output signal.
Interrupts are generated on both type of edges of
the SUB_l/0 output signal,
In Table XXIII is described how these interrupt modes can
be selected.
NRZ DETECTION
Low pass filter (F3) removes the audio spectrum from the
sub-audio signals and amplifies frequencies 14 dB. The
fourth order filter can be set to a low (200 Hz), or a high
(300 Hz) bandwidth by programming reg.13, bl71 Table
XVI). Filtered non return to zero signals (as used in DCS
systems) are then digitized by the Schmitt trigger, Because
of the small signal amplitude of sub-audio logic signals, very
low frequency signals (e.g., DC voltage shifts) can affect
signal detection. Therefore an offset compensation circuit is
integrated that can compensate for (fixed) offset voltages in
the signal path under serial bus control. By programming
reg.11, b[3:0] the reference voltage at the input of the
Schmitt trigger circuit (8T1) can be varied. The MSB bit
(bi31) defines the sign of the compensation voltage. The
offset compensation could be performed after power-up of
the SC11372 circuit. Table XV shows the typical voltage
range to be programmed.
Mode 2.
Mode 3.
TABLE XIV
Description Condition Min Typ Max Units
Input Level At RXIN, GG? = 0 dB 25 75 125 mVrms
Bit Error Rate, 1200 Ed S/N = 12 dB, VIN = 75 mVrms (Note 1) 1 x10-3
S/N = 12 dB, VIN = 38 mVrms (Note 1) 2 x10-3
Bit Error Rate, 2400 Bd S/ N = 12 dB, " = 75 mVrms (Note 2) TBD x10-3
S/N = 12 di3,)hr: = 38 mVrms (Note 2) TBD x10-3
Detect Sensitivity Pattern 1010101010, GC2 = 0 dB 50 mVrms
Load Resistance DEMOD Pin 200 kn
Output Resistance OP_OUT Pin 200 n
Input Resistance BIAS Pin 100 Mn
Load Capacitance DEMOD Pin 5 pF
Load Capacitance OP_OUT Pin 20 pF
DC Input Range OP-POS, BIAS Pins 0.5 3.5 V
Detect Response Time C at CEXT 22 nF, pat. 010101... 5 ms
Note 1: sm measured in 1200 Hz bandwidth, filter F11 in signal path, undistorted FFSK signal at input.
Note 2: S/N measured in 2400 Hz bandwidth, filter F12 in signal path, no phase equalization. undistorted FFSK signal at input.
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5.0 Signaling (Receive) (Continued)
TABLE XV. Reference Offset Voltage Programming CTCSS DETECTION
. For CTCSS detection the signal can be routed through
Code (bl2:0l) Voltage (mV) bandpass filter F9 (reg.13, bill). This high a filter removes
000 0 audio signals and noise and amplifies the signal 14 dB. The
001 25 centre frequency of the bandpass filter can be programmed
throughout the CTCSS frequency range from 67 Hz to
010 50 250.3 Hz. The filter will typically provide 6 dB attenuation for
the nearest CTCSS tone. Programming of the bandpass fil-
011 75 ter centre frequency is performed by programming the
100 100 CTCSS transmit frequency select registers reg.03, bl7:0l
and reg.02, b[726]. F
101 125
110 150 5.3 SELCALL DETECTION
For the processing of SELCALL signals, a bandpass filter
111 175 F4 and Schmitt trigger circuit (8T2) are integrated. The filter
. . (F4) has a flat response (url dB) from 450 Hz to 3000 Hz.
If a varying DC voltage (in the RXI.N, input affects the detee- At low and high frequencies the roll off is 12 dB per octave.
Pn. ps".ftyparty, then i..t IS .post.1ble to txmnettt the am?” The output pin (TXS) of the SELCALL circuit is shared with
1185 and filtered sub-audio fignal to output OP-OUT usmg the TXCLK output of the FFSK transmitter. Using switch s30
switch s27 (mg.12, p). Using external components, the DC (reg.OC, b[4:3]) the output of ST2, the filter output, the filter
component of the signal _ berestoreci ant be fed to the input or the FFSK transmitter clock output can be connect-
reference Input of the Schmitt trigger usmg input BIAS and ed to the TXS pin. The circuit is enabled if either the output
switch S26 (reg.12, M). . of filter F4 or the output of ST2 is selected using s30.
TABLE XVI. Sub-Audio Detection
Description Condition Min Typ Max Units
F3 Bandwidth -3 dB, Bandwidth Low 150 Hz
F3 Response Rel. to F ct--. 0 . F = 315 Hz, Bandwidth Low . 35 dB
F3 Bandwidth -3 dB, Bandwidth High 250 Hz
F3 Response Rel. to F = 0 F = 450 Hz, Bandwidth High 35 dB
F3 Gain , 13 15 dB
F9 Centre Frequency Tolerance 1 %
F9 Gain 13 15 dB
DC Input Range BIAS Pin 0.5 3.5 V
F Hysteresis STI Circuit 15 20 25 mV
TABLE XVII. SELCALL Detector Specification
Description Condition Min Typ _ Max Units
Filter F4 Gain -1 1 dB
Corner Frequency of F4 Lower Corner (- 1 dB) 450 Hz
I Higher Corner (-I dB) 3000 Hz
Gain at 325 Hz -3.2 -3 -2.8 dB
at 4 kHz -3.2 -3 -2.8 dB
at 220 Hz -9.5 -9 - 8.5 dB
at 6 kHz -9.5 -9 - 8.5 dB
Hysteresis ST2 Circuit 15 20 25 mV
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6.0 Miscellaneous Functions
6.1 REFERENCE BUFFERS
A mid-supply reference voltage is generated and buffered
on-chip. Two buffers Ref1 and Ref2 are provided, one for
the audio circuits and another for the signaling functions.
External capacitors are needed to decouple the reterence
voltage pins in order to prevent crosstalk between circuit
sections.
6.2 DA CONVERTOR
An 8-bit D to A convertor is integrated to perform analog
control functions in the radio under control of the systems
microcontroller through serial bus control. The output signal
of the convertor is available at the DTOA pin. Register 17 is
the control register of the DA convertor. It is possible to
continuously update the DA converter input code without
the need to send the sub address with every new data byte.
After the IC is addressed and the DA convertor subaddress
is sent followed by the first data byte, new data bytes can be
sent. To use this fast update mode, the circuit should not be
in auto increment mode. Figure ft illustrates this sequence.
TABLE XVIII. Reference Circuit Speeifieatlort
Description Condition Min Typ Max Units
Output Voltage (Note 1) VMID, REF1 and REF2 Pins 2.35 2.65 V
Load Resistance 50 k0.
Decoupling Capacitor VMID 100 nF
Decoupling Capacitor REF1, REF2 33 nF
Nate 1: Supply voltage Avo-Aus, VDD-Vssl 5.00V.
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FIGURE 11. Control of DA Converter
TL/W/12625-14
TABLE XIX. DA Converter Specification
Description Condition Min Typ Max Units
Integral Non-Linearity 1 LSB
Differential Non-Linearity 0.5 LSB
Settling Time 0.1 ms
Load Capacitance DTOA Output 250 pF
Output Voltage Range DTOA Output 0 4.9 V
ISOURCE DTOA Output 500 FA
ISINK DTOA Output 50 FA
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SC11372
6.0 Miscellaneous Functions (Continued)
6.3 AD CONVERTOR AND RECTIFIER
An A to D convertor is provided to measure voltages on chip
and external signals applied to the CONVIN pin. It is an
integrating type converter which continuously converts the
signal and automatically updates tte' tiata)wffer'register "
ter each conversion. The ADC is powered after bit 7 of pow-
er control register OB has been set and the conversion is
started using reg.14, b[7]. The A to D converter input is
connected to switch s24 (reg.D, b[3:2]). This permits con-
verting voltages from different sources on the IC or from
outside using the CONVIN input. One of the internal sources
is a full wave rectifier circuit that, in combination with the
ADC, can be used to measure the amplitude of the audio
signal in.both the receive and the transmit sighal path. An
external capacitor can be connected to output TC in order
to filterthe rectified signal. The output resistance at pin TC
in combination with the external capacitor then forms an RC
filter. The ADC has two modes of operation:
High resolution-low speed
. Low rsmolution-high speed
Register 13, MB] must be programmed to switch between
high and low resolution.
To read the ADC output code first register 16 must be set
for non-auto Increment mode. Hereafter these data bytes
can be read from the ADC in a byte after byte sequence
without the heed to address the IC for each data byte to he
read. Figure 12 shows how data can be read from the ADC.
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FIGURE 12. Control of AD Converter
TABLE XX. Specification of ADC and. Rectifier
Description Condition Min Typ Max Units
Integral Non-Linearity 1 LSB
Differential Non-Linearity 0.5 LSB
Zero Error - 50 50 mV
Input Resistance 100 kn
Input Voltage Range (Note 1) 0.05 4.95 V
Conversion Time 6-Bit Mode 0.3 ms
Conversion Time 7 B-Bit Mode 1.2 me
Max Input Frequency _ Rectifier 20 . kHz
Input Voltage Rectifier 2 Vp
Output Resistance Rosi'iiar '140 m
Offset Voltage Rectifier 1 00 mV
Note 1: Supply voltage Aim-Nts, VDD-V'ssi 5.00V.-
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6.0 Miscellaneous Functions (Continued)
6.4 CRYSTAL OSCILLATOR AND CLOCK CIRCUITRY
An 11.0592 MHz crystal should be connected between the
XIN pin of the IC and vss. Internally the XIN pin is connect-
ed to a parallel resonance crystal oscillator. If available an
11,0592 MHz clock signal can be connected to the XIN in-
put. All internal timing signals and the signal frequency at
the CLOCKOUT pin are derived from the 11.0592 MHz os-
cillator signal. A programmable frequency divider is used to
obtain the CLOCKOUT signal. The frequencies can be pro-
grammed using reg.13, b[5:3]. Switching between the differ-
ent frequencies is spike free. Therefore, the signal can be
used as a microcontroller clock signal and be a simple
means to control the power consumption of the logic control
circuitry of the radio.
TABLE XXII. Specification of Oscillator and CLOCKOUT Slgnal
TABLE XXI. CLKOUT Frequencies
Code Mode Frequency at CLOCKOUT
000 Off
001 /2 5.530 MHz
010 /8 1.382 MHz
011 /4 2.765 MHz
100 /3 3.686 MHz
101 /2 5.530 MHz
110 /1.5 7.373 MHz
111 M 11.059MHZ
Description
Condition Min Typ Max Units
Fr. (Crystal Par. Resonance Freq) Crystal Specified for Cpar = 10 pF 11.0592 MHz
CL (Capacitive Load) at XIN 10 pF
RIN (Input Resistance) XIN -50 n
cm (Input Capacitance) XIN 10 pF
Input Amplitude External Clock Signal 2.5 Vpp
Output Source Current CLOCKOUT 1.3 mA
Output Sink Current CLOCKOUT 1.6 mA
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7.0 Serial Bus Interface and Logic
Control
The 8011372 is an RC slave transceiver device which can
transmit and receive data via its serial bus. The maximum
clock frequency on the bus is 400 kHz. One input pin is
reserved to define bit Aill of the device address. This al-
lows two SC11372 devices to be used in one system.
The address is 001100X (A[1] = X).
An auto increment mode is implemented to enable sequen-
tial programming of the registers without the need to ad-
dress each register to be programmed. Registers 00 to 17
can be accessed in this mode of operation. In auto-incre-
ment mode, after location 17 has been written, the next
register addressed is reg.00. To enable _auto-intorement
mode, the three bits preceding the sub-address code must
be 0. If the three bits are 1, then non auto-increment mode
will be selected.
INTERRUPT CONTROL
One dedicated interrupt control pin (tNTB) is available to
ease communication with the microcontroller. A pulse with a
typical duration of 8.7 us is generated by the interrupt con-
trol logic if the interrupt condition is fulfilled. Different sourc-
es of interrupt can be selected using the serial bus:
1. Sub-audio signal generator in synchronous mode.
2. Sub-audio signal detector (3 interrupt modes).
3. FFSK receiver with FIFO data buffering (2 interrupt
modes).
Heg.13. bfol selects between the FFSK receiver and the
sub-audio circuit as interrupt source. if the FFSK circuit is
selected, then reg.11. bl4] defines the interrupt condition. If
the sub-audio circuit is selected, then reg.02, bl41 makes
the selection between the sub-audio transmit and receive
circuit as interrupt source. Fieg.02, b[4:3] then defines; the
interrupt condition. Table XXIV shows how the control regis-
ters must beprogrammed to define the interrupt sources.
TABLE XXIII. Characteristics of SDA and SCL lnputs/Outputs
Min Max Units
Description Condition
LOW Level Input Voltage SDA Input 1.5 V
HIGH Level Input Voltage SDA Input 2.9 V
Input Hysteresis SDA, SCL Inputs 0.5 1.2 V
Low Level Output Voltage
SDA, 6 mA Sink Current 0.4 V
Suppressed Spike Pulse Width SDA, SCL Inputs 50 ns
Clock Speed SCL 400 kHz
TABLE XXIV. Interrupt Source Selection
reg.13, b[0]
Sub-Audio FFSKRX
reg.02, b[4] reg.11, b[4]
reg.02, b[3:2] TX 8 Bits in FIFO 1-Bit in FIFO
00 Rising Edge
01 NRZ, Sync Falling Edge
10 Both Edges
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8.0 SC11372 Register Map
Address Bit No. Name Code Function Default
_ 00H [2:0] sl [2:0] 000 Ref --r GCO *
.. 001 Mic2 _ GCO
010 COMP! - GCO
011 S17 - GCO
100 tone_g1 _ GCO
101 Mic1 - GCO
110 Ref _ GCO
111 Ref _ G00
3 s2[0] 0 s35 - GC1 .
1 ALC _ GC1
4 s2[11 0 G00 - F6 .
1 XRX - F6
5 s35 0 G00 _ ALC *
1 F6 - ALC
1 [7:6] $32[1:0] 00 ref - F7 .
, 01 s8 - F7
[ IO sums --+ F7
11 GC3 --r F7
3' 01H 0 S10 0 ref - GC8 *
I 1 GC7 - G08
:1 [2:1] s11[1:01 00 ref - G09 .
E1 01 GO? - G09
"! IO GC6 - GC9
11 GC8 - 609
3 s11a O Non-Inverting *
1 Inverting
4 s9 0 s32 - G05 .
1 F7 - G05
5 s31 0 ref - sum2 .
1 GC6 _ sum2
6 S33 0 ref _ sum2 .
1 605 --> sum2
7 steep 0 F5 Standard Mode .
1 F5 Sub-Audio Suppression Active
' 02H [1:0] $22[1:0] 00 Ref _ Rectifier .
01 GC1 _ Rectifier
10 s35 _ Rectifier
11 XRX --y Rectifier
[3:2] dc[1:0] subrx = 0 subrx = 1
00 NRZ Mode, Asynchr. Int. on Rising Edges '
01 NR2 Mode, Synchr. Int. on Falling Edges
10 CTCSS Mode
Int. on both Edges
CTCSS Mode, Inverted
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SC11372
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© ESULLBE 00673'1‘1 5% CCI
8.0 SC11372 Register Map (Continued)
Address Bit No. Name Code Function Default
02h 4 _subrx 0 SUB_.l/O = Input - Sub-Audio Transmit Mode .
(Cont) 1 SUB_I/O = Oytput"r Sub-Audio Receive Mode
5 ffsktxeab 0 FFSKtx Enabled
1 FFSKtx Disabled '
[7:6] ctcss[9:8] CTCSS Frequency Select 1 1
03H [7:0] ctcss[7:0] CTCSS Frequency Select 5BH
04H [2:0] tgl [10:8] ton941 Frequency Select 0
[5:3] 192[10:8] tone-g2 Frequency Select
6 tgl-a 0 tone_g1 Amplitude Low *
1 tone_g1 Amplitude High
7 tg2-a 0 tone_92 Amplitude Low 1
1 tone_gz Amplitude High
05H [7:0] tg1[7:0] tone_g1 Frequency Select 00H
06H [7:0] tg217:0l tone_g2 Frequency Select 00H
07H [3:0] GCO[3:O] 1000
[7:4] GCI [3:0] 1000
08H [3:0] _ GC8 [3:0] 1000
[7:4] GCS[3:0] 1000
09H [3:0] 605 [3:0] 1000
[7:4] GCG[3:0] 1000
OAH _ [3:0] G03[3:0] 1000
[7:4] (304 [3:0] 1 000
OBH 0 PWR_subrx Activates Sub-Audio rx Circuitry 0
F 1 PWR_FFSer Activates FFSKrx Circuits 0
2 PWR_FFSKdt Activates FFSKdt Circuits O
3 PWR_audio Activates all Audio Signal Proc. Circuits 0
4 PWR_tones Activates Alert and Tone Generators 0
T 5 PWR_subtx Activates the Sub-Audio tx Circuits 0
6 PWR_FFSKtx Activates the FFSK transmitter and Switch s8 0
7 PWR_misc Activates ADC, DAC and the Rectifier 0
OCH 0 s6 0 " _ s6 *
1 sum1 - s6
1 s7 0 _ LIMO - limiter .
1 LIMI - limiter
2 s23 0 s6 - GC7 *
1 EXPI -+ GC7
8.0 $611372 Register Map (Continued)
Address Bit No. Name Code Function Default
OCH [4:3] s30ir.ol 00 TXCLK _ TXS .
(Cont) 01 s16 _ TXS
10 F4 - TXS, Activates Selcall rx Circuit .
11 ST2 - TXS, Activates Selcall rx Circuit
[6:5] sal1:0] 00 GC1 - F5 *
01 COMP1 - F5
10 s17 -+ F5
11 GG5 - F5
7 s4 0 ' $3 _ LIMO .
1 F5 - LIMO
ODH 11:0l 55[1:0] 00 limiter - sum1 .
01 ref - sum1
10 s? - sum1
11 tvar test signal - sum1
[3:2] $24[1:0] 00 ref _ ADC .
01 CONVIN _ ADC
10 rectifier - ADC
4 s19 0 Hm RXIN = High .
1 RIN RXIN = Low
[6:5] 525[1:0] 00 ref _ COMPEX .
01 s6 - COMPEX
10 GC1 _ COMPEX
11 (500 _ COMPEX
7 Ip255 0 Bandwidth of F8: 3 kHz .
1 Bandwidth of F8: 2.55 kHz
OEH 0 S14 0 ref _ sum4 .
1 GC4 - sum4
1 s15 0 ref - sum4 .
1 GO? - sum4
[3:2] s21 [1:0] 00 ref - G010 .
01 sum4 - GC10
10 sum5 - 6010
1 1 Compos Test Signal
4 s20 0 ref - (3011 .
. 1 sum4 _ GC11
[6:5] 534[1:0] 00 ref - GC4 *
01 alert_G _ GC4
10 tone__g2 - GC4
11 s32 - GC4
7 s17 0 (502 - s3 *
1 F 1 _ s3
==--==----=-"-'"
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SC11372
8.0 $611372 Register Map (Continued)
Address Bit No. Name Code Function Default
OFH [3:0] GCTI320] 1000
[7:4] GC2[3:0] 1000
10H [3:0] GC1 t) [3:0] 1000
{7:4} GC1 1 [3:01 1000
1 1H [3:0] offset[3:0] Offset Trimming for ST1 0
4 int8 O FFSK rx int. after Bit 1 is Shifted into Empty FIFO *
1 FFSK rx int. after Bit 8 is Shifted into FIFO
12H 0 s13 0 FFSK Test Output Disabled .
1 _ FFSK Test Output - XRX
1 FFSK 0 1200 Baud .
1 2400 Baud
[3:2] $1611 :0] 00 602 _ F4 *
01 s17r-+ F4
" LIMO - F4
11 s25 input - F4
4 s26 0 STref - ST1 *
1 BIAS - ST1
5 s27 0 OP_OUT - s28 *
1 OP_OUT - ST1
6 s28 0 F11 _ FFSKRX .
1 amp _ FFSKRX
7 s29, s29a 0 ref _ FFSKRX and F4 - ST2 *
1 BIAS - FFSKRX and amp - ST2
13H 0 INTS 0 . Interrupt Source: Sub-Audio Circuit *
1 Interrupt Source: FFSer (FIFO)
1 s18 0 F3 - ST1 *
1 F9 _ ST1
2 s36 0 S36 Disabled *
1 G02 _ XRX
[5:3] Xsel[2:0] 000 CLKOUT Output Off
001 Div. Factor = 2
010 Div. Factor -- 8
011 Div. Factor = 4
100 Div. Factor = 3
101 Div. Factor = 2 *
110 Div. Factor == 1.5
111 Div. Factor = 1
6 ADCres 0 8-Bit Resolution '
1 6-Bit Resolution
7 F3chw 0 Bandwidth is Low
_ 1 Jirandwith is High *
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8.0 SC11372 Register Map (Continued) l?
Address Bit No. Name Code Function Default cg
14H [5:0] Lg [5:0] Alert Generator Frequency Select 000000
6 rx___io O FIFO Mode Disabled .
1 FIFO Mode Enabled (RXCLK) pin is input)
7 start__ADC 0 ADC Inactive *
1 ADC is Running
15H [2:0] alc[2:0] 000 Attack Time is 0.5 ms .
001 Attack Time is 0.9 ms
010 Attack Time is 1.9 ms
011 Attack Time is 3.7 ms
- 100 Attack Time is 7.4 ms
; 101 Attack Time is 14.8 ms
110 Attack Time is 29.6 ms
111 Attack Time is 59.3 ms
[3] aic[3] 0 Zero Crossing Detection Off .
1 Zero Crossing Detection On
[7:4] alcl7:41 0-4H Decay/Attack = 4 '
0101 Decay/Attack = B
0110 Decay/Attack = 16
0111 Decay/Attack = 32
1000 Decay/Attack = 64
1001 Decay/Attack = 128
1010 Decay/Attack = 256
1011 Decay/Attack = 512
1 100 Decay/Attack = 1024
1101 Decay/Attack = 2048
1 1 1O Decay/Attack = 4096
1111 Decay/Attack = 8192
16H [7:0] adcl7:0] . 80H (iii""""
17H [7:0] dac[7:0] 00H
1 EH 0 Proff Test Bit
1 Sdat Test Bit
2 aic_mag Test Bit
3 MSB_dis Test Bit
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$011372
8.0 $011372 Register Map (Continued)
Address Bit No. Name Code Function / Default
1FH [2:0] INTSEL[2:0] 000 FFSKsign .
001 Subsign
01 0 AL
01 1 ADCbusy
100 Up
1 01 . Down
110 Zerocross
1 1 1 cpout
3 intselea
4 adcbusy
5 fasttx
6 testadc
7 tesden
Note: Registers 1E and 1F are test registers.
Revision Changes
New Revlslon Old Revision Changes
0.20 . 0.28 Current values in Table III and Table N have been changed.
1.0A 0.20 Typographical and editorial changes.
2.0A 1.0A V Block Diagram, functional change: S2, S25.
Register Map: Reg 00H, bl4a-Rsg ODH, b[1:0] and [6:5].
Table IV. Current Consumption.
Table XXIII renumbered to 24.
Serial Bus l/O Specification added: Table XXIII,
Table 20: Rectifier offset voltage added.
Typographical and editorial changes.
2.0B _ 2.0A Typographical and editorial changes.
- Datasheet revlslon 2.0A is valid for IC’s with datecode 9548 or newer -
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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