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SABC513A-LM |SABC513ALMSIEMENSN/a15avai8-Bit Microcontroller


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SABC513A-LM
8-Bit Microcontroller


8-Bit CMOS Microcontroller Family
Preliminary
C511
C511A
C513
C513A
C513A-H
Fully software compatible to standard 8051/8052 microcontrollersUp to 12 MHz operating frequencyUp to 12 K·8 ROM / EEPROMUp to 256·8 RAMUp to 256 x 8 XRAMFour 8-bit portsUp to three 16-bit Timers / Counters (Timer 2 with Up/Down and 16-bit Autoreload Feature)Synchronous Serial Channel (SSC)Optional USARTUp to seven interrupt sources, two priority levelsPower Saving ModesP-LCC-44 package (C513A also in P-MQFP-44 package)Temperature Ranges :SAB-C511 / 511A / 513 / 513A / C513A-HTA : 0 ˚C to 70 ˚C
SAF-C513ATA : -40 ˚C to 85 ˚C
C511 / C513
The C511, C511A, C513, C513A, and C513A-H are members of a family of low cost micro-
controllers, which are software compatible with the components of the SAB 8051, SAB 80C51 and
C500 families.
The first four versions contains a non-volatile read-only (ROM) program memory. The C513A-H is
a version with a 12 Kbyte EEPROM instead of ROM. This device can be used for prototype designs
which have a demand for reprogrammable on-chip code memory.
The members of the microcontroller family differ in functionality according table 1. They offer
different ROM sizes, different RAM/XRAM sizes and a different timer/USART configuration.
Common to all devices is an advanced SSC serial port, a second synchronous serial interface,
which is compatible to the SPI serial bus industry standard. The functionality of the C513A-H is a
superset of all ROM versions of the C511/C513 family.
Table 1
Functionality of the C511/C513 MCUs
T0/T1 refers to the standard 8051 timer 0/1 units, T2 refers to the 8052 timer 2 unit.

Figure 1
C511 / C513
Table 2
Ordering Information
Note :
The ordering number of the ROM types (DXXXX extension) is defined after program release
(verification) of the customer.
C511 / C513

Figure 2
P-LCC-44 Package Pin Configuration (Top View)

If the C513A-H is used in programming mode, the pin configuration is different to figure 2 and 3 (see
figure 5).
C511 / C513

Figure 3
P-MQFP-44 Package Pin Configuration of the C513A (Top View)


C511 / C513
Table 3
Pin Definitions and Functions
I= Input= Output
C511 / C513I= Input= Output
Table 3
Pin Definitions and Functions (cont’d)
C511 / C513I= Input= Output
Table 3
Pin Definitions and Functions (cont’d)
C511 / C513I = Input
O = Output
Table 3
Pin Definitions and Functions (cont’d)
C511 / C513

Figure 4
C513A-H Logic Symbol in Programming Mode


Figure 5
C511 / C513
Table 4
Pin Definitions and Functions in Programming Mode (C513A-H only)
I= Input= Output
C511 / C513I= Input= Output
Table 4
Pin Definitions and Functions in Programming Mode (C513A-H only) (cont’d)
C511 / C513
Functional Description

The C511/C513 microcontrollers are fully compatible to the standard 8051/80C52 and C500
microcontroller family. While maintaining all architectural and operational characteristics of the
80C52/C500 the C511/C513 incorporates enhancements such as additional internal XRAM and a
second (synchronous) serial interface unit.
Figure 6 shows a block diagram of the C511/C513 microcontroller family.


Figure 6
Block Diagram of the C511/C513 Units
C511 / C513
CPU

The C511/C513 are efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and for bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % three-
byte instructions. With a 12 MHz crystal, 58 % of the instructions execute in 1 ms.
Special Function Register PSW (Address D0H) Reset Value : 00H

D0HPSW
Bit No.76543210
MSBLSB
C511 / C513
Special Function Registers

All registers except the program counter and the four general purpose register banks reside in the
special function register area.
The 34 special function registers (SFR) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits
within the SFR area.
All SFRs are listed in table 5 and table 6. In table 5 they are organized in groups which refer to the
functional blocks of the C511/C513. Table 6 illustrates the contents of the SFRs, e.g. the bits of the
SFRs, in numeric order of their addresses.

C511 / C513
Table 5
SFRs - Functional Blocks
Bit-addressable special function registersThis special function register is listed repeatedly since some bits of it also belong to other functional blocks.
C511 / C513

Table 6
Contents of the SFRs, SFRs in Numeric Order of their Addresses
C511 / C513X means that the value is indeterminate and the location is reserved.The availability of the XMAP bit and the reset value of SYSCON depends on the specific microcontroller :
C511/C511A/C513 :101X0XXXB - bit XMAP is not available
C513A/C513A-H : 101X0XX0B - bit XMAP is availableThis register ist only used for test purposes and must not be written. Otherwise unpredictable results may
occur.
Shaded registers are bit-addressable special function registers.
Table 6
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)
C511 / C513
Timer/ Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 7:
Table 7
Timer/Counter 0 and 1 operating modes

In “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count
rate is fOSC/12.
In “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 7 illustrates the
input clock logic.

Figure 7
C511 / C513
Timer / Counter 2 (not available in the C511/C511A)

Timer 2 is a 16-bit Timer/Counter with up/down count feature. It can operate either as timer or as an
event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in
table 8.
Table 8
Timer/Counter 2 Operating Modes
Note:
fl = falling edge
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