SAA7706H ,Car radio Digital Signal Processor (DSP)General description16 APPLICATION DIAGRAM8.7 The Filter Stream DAC (FSDAC)17 PACKAGE OUTLINE8.7.1 I ..
SAA7706H ,Car radio Digital Signal Processor (DSP)FUNCTIONAL DESCRIPTION8.17 Test mode connections (pins TSCAN, RTCB8.1 Analog front-endand SHTCB)8.1 ..
SAA7706H/N107 ,SAA7706H; Car radio Digital Signal Processor (DSP)
SAA7706H/N108 ,SAA7706H; Car radio Digital Signal Processor (DSP)
SAA7706H/N109 ,SAA7706H; Car radio Digital Signal Processor (DSP)
SAA7715AH ,Digital Signal Processor
SC5205-3.0CSKTR , 150mA Ultra Low Dropout, Low Noise Micropower Linear Regulator
SC5205-3.3CSKTR , 150mA Ultra Low Dropout, Low Noise Micropower Linear Regulator
SC5205-3.6CSKTR , 150mA Ultra Low Dropout, Low Noise Micropower Linear Regulator
SC5205-5.0CSKTR , 150mA Ultra Low Dropout, Low Noise Micropower Linear Regulator
SC5262 ,NPN EPITAXIAL PLANAR TYPE (VHF~UHF BAND LOW NOISE AMPLIFIER APPLICATIONS)
SC5387 ,NPN TRIPLE DIFFUSED MESA TYPE (HORIZONTAL DEFLECTION OUTPUT FOR MEDIUM RESOLUTION DISPLAY/ COLOR TV. HIGH SPEED SWITCHING APPLICATIONS)
SAA7706H
Car radio Digital Signal Processor (DSP)
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
CONTENTS FEATURES
1.1 Hardware
1.2 Software APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
8.1 Analog front-end
8.1.1 The realizationof common mode input with AIC
8.1.2 Realization of the auxiliary input with volume
control
8.1.3 Realization of the FM input control
8.1.4 Pins VDACN1, VDACN2 and VDACP
8.1.5 Pin VREFAD
8.1.6 Supply of the analog inputs
8.2 The signal audio path for input signals CD,
TAPE, AUX, PHONE, NAV and AM
8.3 Signal path for level information
8.4 Signal path from FM_MPX input to IAC and
stereo decoder
8.4.1 Noise level
8.4.2 Mono or stereo switching
8.4.3 The automatic lock system
8.5 DCS clock
8.6 The Interference Absorption Circuit (IAC)
8.6.1 General description
8.7 The Filter Stream DAC (FSDAC)
8.7.1 Interpolation filter
8.7.2 Noise shaper
8.7.3 Function of pin POM
8.7.4 Power-off plop suppression
8.7.5 Pin VREFDA for internal reference
8.7.6 Supply of the filter stream DAC
8.8 Clock circuit and oscillator
8.8.1 Supply of the crystal oscillator
8.9 The phase-locked loop circuit to generate the
DSPs and other clocks
8.10 Supply of the digital part (VDDD3V1to VDDD3V4)
8.11 CL_GEN, audio clock recovery block
8.12 External control pins
8.12.1 DSP1
8.12.2 DSP2
8.13 I2 C-bus control (pins SCL and SDA)
8.14 Digital serial inputs/outputs and SPDIF inputs
8.14.1 General description digital serial audio
inputs/outputs
8.14.2 General description SPDIF inputs(SPDIF1and
SPDIF2)
8.14.3 Digital data stream formats
8.15 RDS demodulator (pins RDS_CLOCK
and RDS_DATA)
8.15.1 Clock and data recovery
8.15.2 Timing of clock and data signals
8.15.3 Buffering of RDS data
8.15.4 Buffer interface
8.16 DSP reset
8.17 Test mode connections (pins TSCAN, RTCB
and SHTCB)2 C-BUS FORMAT
9.1 Addressing
9.2 Slave address (pin A0)
9.3 Write cycles
9.4 Read cycles
9.5 SAA7706H hardware registers
9.5.1 SAA7706H DSPs registers
9.6 I2 C-bus memory map specification LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS RDS AND I2S-BUS TIMING I2 C-BUS TIMING SOFTWARE DESCRIPTION APPLICATION DIAGRAM PACKAGE OUTLINE SOLDERING
18.1 Introduction to soldering surface mount
packages
18.2 Reflow soldering
18.3 Wave soldering
18.4 Manual soldering
18.5 Suitability of surface mount IC packages for
wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
FEATURES
1.1 Hardware 5-bitstream 3rd-order sigma-delta Analog-to-Digital
Converters (ADCs) with anti-aliasing broadband input
filter 1-bitstream 1st-order sigma-delta ADCwith anti-aliasing
broadband input filter 4-bitstream Digital-to-Analog Converters (DACs) with
128-fold oversampling and noise shaping Integrated semi-digital filter; no external post filter
required for DAC Dual media support: allowing separate front-seat and
rear-seat signal sources and separate control Simultaneous radio and audio processing Digital FM stereo decoder Digital FM interference suppression RDS demodulation via separate ADC; with buffered
output option Two mono Common-Mode Rejection Ratio (CMRR)
input stagesfor voice signals fromphone and navigation
inputs Phone and navigation mixing at DAC front outputs Two stereo CMRR input stages (CD-walkman and
CD-changer etc.) Analog single-ended TAPE and AUX input Separate AM-left and AM-right inputsin the eventof use
of external AM stereo decoder One digital input: I2 S-bus or LSB-justified format Two digital inputs: SPDIF format Co-DSP support via I2 S-bus or LSB-justified format Audio output short-circuit protectedI2 C-bus controlled (including fast mode) MOST bus interfacing (details in separate manual) Phase-locked loop derives the internal clocks from one
common fundamental crystal oscillator Combined AM/FM level input Pin compatible with SAA7705 and SAA7708 All digital inputs are tolerant of 5 V input levels All analog inputs have high GSM immunity Low number of external components required
•−40to +85 °C operating temperature range Easy applicable.
1.2 Software Improved FM weak signal processing Integrated 19 kHz MPX filter; de-emphasis and stereo
detection Electronic adjustments: FMor AM level, FM channel
separation, Dolby®(1) level Baseband audio processing (treble, bass, balance,
fader and volume) Four channel 5-band parametric equalizer 9-bands mono audio spectrum analyzer Extended beep functions with tone sequencerfor phone
rings Large volume jumps e-power interpolated to prevent
zipper noise Dual media support; allowing separate front-seat and
rear-seat signal sources and separate control Dynamic loudness or bass boost Audio level monitor Tape equalization and Music Search System (MSS)
detection for tape Dolby-B tape noise reduction (at 44.1 kHz only) Dynamics compression available in all modes CD de-emphasis processing Voice-over possibility for phone and navigation signals Improved AM signal processing Digital AM CQUAM stereo decoder (not in all
rom_codes available) Digital AM interference suppression Soft audio mute RDS update processing: pause detection, mute and
signal-quality sensor-freeze General purpose tone generator
(1)
Dolby — Available only to licensees of Dolby LaboratoriesLicensing Corporation, San Francisco, CA94111, USA, from
whom licensing and application information mustbe obtained.
Dolby is a registered trade-mark of Dolby Laboratories
Licensing Corporation.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H Noise generator allows for frequency response
measurements Boot-up ROM for fast start-up Signal level, noiseand multipath detectionfor AMor FM
signal quality information AM co-channel and adjacent channel detection (not in
all rom_codes available).
APPLICATIONS High-end car radio systems.
GENERAL DESCRIPTIONThe SAA7706H performsall the signal functionsin frontof
the power amplifiers and behind the car radio tuner and FM outputs and the CD, tape and phone inputs.
These functions are: Interference absorption Stereo decoding for FM and AM (stereo) RDS-demodulation FM and AM weak signal processing (soft mute, sliding
stereo and high cut) Dolby-B tape noise reduction CD de-emphasis function Audio controls for volume, balance, fader, tone and
dynamics compression.
Some functions have been implemented in hardware
(FM stereo decoder, RDS-demodulator and Interference Absorption Circuit (IAC) and are not freely
programmable.
Digital audio signals from external sources with the Philips2 S-bus and theLSB-justified 16, 18,20 and24 bits format
or SPDIF format are accepted.
The big advantage of this SAA7706H device is the ‘dual
media support’; this enables independent front seat and
rear seat audio sources and control.
QUICK REFERENCE DATA
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
ORDERING INFORMATION
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
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BLOCK DIAGRAM
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
PINNING
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
Table 1 Brief explanation of used pin types
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H FUNCTIONAL DESCRIPTION
8.1 Analog front-end
The analog front-end consistsof two identical sigma-delta
stereo ADCs (ADC1 and ADC2) with several input control
blocks for handling common mode signals and acting as
input selector. A mono version (ADC3) is added for
handling RDS signals. Alsoa first-order sigma-delta ADC
for tuner level information is incorporated.
The switches S1 and S2 select (see Fig.3) between the
FM_MPX/FM_RDS and the CD, TAPE, AUX, AM,
PHONE and NAV connection to ADC1 and ADC2. The
inputs CD, TAPE, AUX, AM, PHONE and NAV can be
selected with the audio input controls (AIC1/2). The
ground reference (G0 and G1) canbe selectedtobe able
to handle common mode signals for CD or TAPE. The
ground reference G0 is connected to an external pin
and G1 is internally referenced (see Fig.4).
The PHONE and NAV inputs have their own CMRR input
stage and canbe redirectedto ADC1/2via the Audio Input
Control (AIC). For pin compatibility with SAA7704,
SAA7705 and SAA7708 the AMis combined with the NAV
input. It is also possible to directly mix PHONE or NAV
(controlled with MIXC) with the front FSDAC channels
after volume control. The FM inputs (FM_MPX/FM_RDS)
can be selected with external pin SEL_FR. The and RDS input sensitivitycanbe adjusted with VOLFM
and VOLRDS via I2 C-bus.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.1.1 THE REALIZATIONOF COMMON MODE INPUT WITH
AIC high common mode rejection ratio canbe createdby the
use of the ground return pin. Pin CD_(L)_GND can be
used in the case that the left and right channel have one
ground return line. CD_(L)_GND and CD_R_GND canbe
used for separated left and right ground return lines. The
ground return lines can be connected via the switch
GNDC1/2 and GNDRC1/2 (see Fig.4) to the plus input of
the second operational amplifier in the signal path. The
signal of which a high common mode rejection ratio is
required has a signal and a common signal as input. The
common signal is connected to the CD_(L)_GND and/or
CD_R_GND input. The actual input can be selected with
audio input control AIC1/2(1:0).
In Fig.4 the CD input is selected. In this situation both
signal lines going to S1/2 in front of the ADC will contain
the common mode signal. The ADC itself will suppress this
common mode signal witha high rejection ratio. The inputs
CD_L and CD_R in this example are connected via an
external resistor tap of 82 kΩ and 100 kΩ to be able to
handle larger input signals. The 100 kΩ resistors are
needed to provide a DC biasing of the operational
amplifiers OA1 and OA2. The 1 MΩ resistor provides biasing of OA3 and OA4. If no external resistor tap is
needed the resistors of 100 kΩ and 1 MΩ still have to
provide DC biasing. Only the 82 kΩ resistor can be
removed. The impedance level in combination with
parasitic capacitance at input CD_L or CD_R determines
for a great deal the achievable common rejection ratio.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.1.2 REALIZATIONOF THE AUXILIARY INPUT WITH VOLUME
CONTROL
A differential input with volume control for mixing to the
front leftor front rightof both DAC outputsis provided. The
inputs consist of a PHONE and NAV input. Both are
accompanied with their ground return lines. After selection PHONEor NAV the volume canbe changed from about
+18to −22.5 dB in 27 steps and mute (MIX output). This
signal can be added to the left and/or right front DAC
channels.
The output signals of both input circuits can also be
switchedto ADC1 and/or ADC2, dependingon the settings
of audio input control 1 (AIC1) and audio input control2
(AIC2), without volume control (see Fig.3).
8.1.3 REALIZATIONOF THE FM INPUT CONTROL
The gain of the circuit has a maximum of 2.26 (7.08 dB).
This resultsinan input levelof 368 mVfor full-scale, which
means 0 dB (full-scale) at the DSP1 input via the stereo
decoder (see Fig.6). The gain can be reduced in steps of
1.5 dB. When the gain is set to −3.4 dB the input level
becomes 1229 mVfor full-scale. This setting accountsfor
the 200 mV (RMS) input sensitivityat 22.5 kHz sweep and
a saturation of the input at 138 kHz sweep.
RDS update:for RDS update the fast access pin SEL_FR
mustbe made HIGH.In that case the FM_RDS signal also
goes through the path that was set for FM_MPX. In this
situation the signal must be obtained via the FM_RDS
input and a noise sample can be retrieved. The input
FM_MPX gets high-ohmic. Charging of the coupling
capacitor connectedto pin FM_MPXisno longer possible.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.1.4 PINS VDACN1, VDACN2 AND VDACP
Thesepins are usedas negative and positivereferencefor
the ADC1,2,3 and the level-ADC. They haveto bedirectly
connected to the VSSA1 and filtered VDDA1 for optimal
performance (see Figs 25 and 26).
8.1.5 PIN VREFAD
Via this pin the midref voltageof the ADCsis filtered. This
midref voltageis usedas half supply voltage referenceof
the ADCs. External capacitors (connected to VSSA1)
prevent crosstalk between switch cap DACs of the ADCs
and buffers and improves the power supply rejection ratioall components. This pinis also usedin the application referencefor the inputs TAPE and CD (see Fig.4). The
voltage on pin VREFAD is determent by the voltage on
pins VDACP and VDACN1 or VDACN2 and is found as:
8.1.6 SUPPLYOF THE ANALOG INPUTS
The analog input circuit has separate power supply
connections to allow maximum filtering. These pins are
VSSA1 for the analog ground and VDDA1 for the analog
power supply.
8.2 The signal audio path for input signals CD,
TAPE, AUX, PHONE, NAV and AM
The left and right channels are converted and
down-sampledby the ADF1_a, ADF1_b. This data stream
is converted into a serial format and fed to the DSP1 and
DSP2 source selectors. In Figs7 and 8 the overall and
detailed frequency response curves of the
analog-to-digital audio decimation path based on a
44.1 kHz sample frequency are shown.
VVREFAD V VDACP V VDACN1,2– ----------------------------------------------------=
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.3 Signal path for level information
For FM weak signal processing,for AM and FM purposes
(absolute level and multipath)a level inputis implemented
(pin LEVEL).In the eventof radio reception the clockingof
the filters and the level-ADC is based on a 38 kHz
sampling frequency. A DC input signal is converted by a
bitstream sigma-delta ADC followedbya decimation filter.
The input signal hastobe obtained froma radio part. The
tuner must deliver the level informationof either AMor FM
to pin LEVEL.
The input signal for level must be in the range 0to 3.3V
(VVDACP− VVDACN). The 9-bit level-ADC converts this
input voltagein steps witha resolution better thanat least mV over the 3.3 V range.
The tolerance on the gain is less than 2%. The MSB is
always logic 0 to represent a positive level. Input level
span can be increased by an external resistor tap. The
high input impedance of the level-ADC makes this
possible.
The decimation filter reduces in the event of an 38 kHz
based clocking regime the bandwidth of the incoming
signaltoa frequency rangeof0to29 kHz witha resulting=76 kHz. The response curve is given in Fig.9.
The level information is sub-sampled by the DSP1 to
obtain a field strength and a multipath indication. These
values are stored in the coefficient or data RAM. Via the2 C-bus they canbe read and usedin other microcontroller
programs.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.4 Signal path from FM_MPX input to IAC and
stereo decoder
The FM_MPX signal is after selection available at one of
three ADCs (ADC1,2 and 3). The multiplex FM signal is
converted to the digital domain in ADC1,2 and 3 through
a bitstream ADC. Improved performance for FM stereo
can be achieved by means of adapting the noise shaper
curve of the ADC to a higher bandwidth.
The first decimation takes place in two down-sample
filters. These decimation filters are switched by means of
the I2C-bus bit wide_narrow in the wide or narrow band
position. In the event of FM reception it must be in the
narrow position.
After selectionof oneof the ADCs, the FM_MPX pathitis
followedby theIAC and the FM stereo decoder. Oneof the
two MPX filter outputs contains the multiplex signal witha
frequency range of 0to60 kHz. The overall low-pass
frequency response of the decimation filters is shown in
Fig.10.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
The outputsof the stereo decoderto the DSP1, which are
all running on a sample frequency of 38 kHz are: Pilot presence indication: pilot-I. This 1-bit signalis LOW
for a pilot frequency deviation <4 kHz and HIGH for a
pilot frequency deviation >4 kHz and locked on a pilot
tone. ‘Left’ and ‘right’ FM reception stereo signal: this is the
18-bit output of the stereo decoder after the matrix
decoding. Noise level (see also Section 8.4.1): which is retrieved
from the high-pass output of the MPX filter. The noise
levelis detected and filteredin the DSP1 andis usedto
optimize the FM weak signal processing.
Normally the FM_MPX input and the FM_RDS input have
the same source. If the FM input contains a stereo radio
channel, the pilot information is switched to the Digitally
Controlled Sampling (DCS) clock generation and the DCS
clockis lockedto the 256×38 kHzof the pilot.In this case
this locked frequency is also used for the RDS path
ensuring the best possible performance.
Except from the above mentioned theoretical response
also the non-flat frequency responseof the ADC hastobe
compensated in the DSP1 program.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.4.1 NOISE LEVEL
The high-pass 1 (HP1 or narrow band noise level filter)
outputof the second MPX decimation filterina band from kHz to 120 kHz is detected with an envelope detector
and decimated to a frequency of 38 kHz. The response
time of the detector is 100 μs. Another option is the
high-pass 2 (HP2 or wide band noise level filter). This
output of the first MPX decimation filter is in a band fromto 240 kHz. It has the same properties and is also
decimated to the same 38 kHz. Which of the signals is
used (HP1 or HP2) is determined by the I2 C-bus
bit sel_nsdec.
The resulting noise informationis rectified and hasa word
length of 10 bits. This means that the lowest and/or the
highest possible level is not used. The noise level can be
detected and filtered in the DSP1-core and be used to
optimize the FM weak signal processing. The transfer
curves of both filters before decimation are shown in
Fig.12.
8.4.2 MONOOR STEREO SWITCHING
The DCS block uses a sample rate converter to derive
from the XTAL clock, via a PLL, a 512 multiple of 19 kHz
(9.728 MHz). In the event of mono reception the DCS
circuit generates a preset frequency of n×19 kHz±2 Hz.
In the event of stereo reception the frequency is exactly×19 kHz (DCS lockedtoN× pilot tone). The detectionof
the pilot and the stereo indication is done in the DSP
program.
8.4.3 THE AUTOMATIC LOCK SYSTEM
The VCO of the DCS block will be at 19 kHz±2 Hz exact
basedin the eventof no-pilot FM_MPX receptionorin the
event of only RDS reception. In the event of stereo
reception the phase error is zero for a pilot tone with a
frequency of exactly 19 kHz.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.5 DCS clock
In radio mode the stereo decoder, the ADC3 and RDS
demodulator, the ADC1or ADC2 and the level decimation
filters have to run synchronously to the 19 kHz pilot.
Therefore a clock signal with a controlled frequency of a
multipleof19 kHz (9.728 MHz= 512×19 kHz)is needed. the SAA7706H the patented methodof non-equidistant
digitally controlled sampling DCS clock has been
implemented. By a special dividing mechanism a
frequencyof 9.728 MHz from the PLL2 clock frequencyof
>40 MHz is generated. The dividing can be changed by
means of I2 C-bus bits to cope with the different input
frequencies of the DCS block.
The DCS system is controlled by up or down information
from the stereo decoder. In the event of mono
transmissionsor 44.1 kHz ADC1or ADC2 usage the DCS
clock is still controlled by the stereo decoder loop. The
outputkeeps the DCS freerunningona multiple frequency
of 19 kHz±2 Hz if the correct clock setting is applied. In
tape/cd of either 38 or 44.1 kHz and AM mode the DCS
clock always hastobe putin preset mode withabitin the2 C-bus memory map definitions.
8.6 The Interference Absorption Circuit (IAC)
8.6.1 GENERAL DESCRIPTION
TheIAC detects and suppresses ignition interference.This
hardware IAC is a modified, digitized and extended
versionof the analog circuit whichisin usefor many years
already.
The IAC consists of an MPX mute function switched by
mute pulses from ignition interference pulse detectors.
The input signal of a second IAC detection circuit is the level signal(theoutputof the level-ADC).This detector
performs optimally in lower antenna voltage
circumstances. It is therefore complementary to the first
detector.
The input signalofa first IAC detection circuitis the output
signal ofoneof thedown-samplepaths comingfrom ADC1
or ADC2. This interference detector analyses the
high-frequency contents of the MPX signal. The
discrimination between interference pulses and other
signals is performed by a special Philips patented fuzzy
logic such as algorithm and is based on probability
calculations. This detector performs optimally in higher
antenna voltage circumstances. On detection of ignition
interference, this logic will send appropriate pulses to the
MPX mute switch.
The characteristicsof both IAC detectors canbe adapted the propertiesof different FM front-ends bymeansof the
predefined coefficients in the IAC control registers. The
valuescanbe changedvia theI2 C-bus. Both IAC detectors
can be switched on or off independently of each other.
Both IAC detectors can mute the MPX signal
independently of each other.
A third IAC function is the dynamic IAC circuit. This block
is intended to switch off the IAC completely the moment
the MPX signal has a too high frequency deviation which the eventof smallIF filters can resultin AM modulation.
This AM modulation could be interpreted by the IAC
circuitry as interference caused by the car’s engine.
8.7 The Filter Stream DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivityis achieved.A post-filteris not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
8.7.1 INTERPOLATION FILTER
The digital filter interpolates from 1to 64fs by means of a
cascade of a recursive filter and an FIR filter.
Table 2 Digital interpolation filter characteristics
8.7.2 NOISE SHAPER
The 5th-order noise shaper operates at 64fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.7.3 FUNCTIONOF PIN POM
With pin POM it is possible to switch off the reference
currentof the DAC. The capacitoron pin POM determines
the time after which this current hasa soft switch-on.Soat
power-on the current audio signal outputs are always
muted. The loadingof the external capacitoris donein two
stagesvia two different current sources. The loading startsa current level thatis lower than thecurrent loading after
the voltage on pin POM has past a particular level. This
results in an almost dB-linear behaviour. This must
prevent ‘plop’ effects during power on or off.
8.7.4 POWER-OFF PLOP SUPPRESSION
To avoid plops in a power amplifier, the supply voltage of
the analog partof the DAC and the restof the chip canbe
fed from a separate power supply of 3.3 V. A capacitor
connected to this power supply enables to provide power
to the analog part at the moment the digital voltage is
switching off fast. In this event the output voltage will
decrease gradually allowing the power amplifier some
extra time to switch off without audible plops.
8.7.5 PIN VREFDA FOR INTERNAL REFERENCE
With two internal resistors half the supply voltage VDDA2is
obtainedand usedasan internal reference. This reference
voltage is used as DC voltage for the output operational
amplifiers and as reference for the DAC.
In order to obtain the lowest noise and to have the best
ripple rejection,a filter capacitor hastobe added between
this pin and ground, preferably close to the analog
pin VSSA2.
8.7.6 SUPPLYOF THE FILTER STREAM DAC
The entire analog circuitryof the DACs and the operational
amplifiers are suppliedby2 supply pins: VDDA2 and VSSA2.
VDDA2 must have sufficient decoupling to prevent total
harmonic distortion degradation and to ensure a good
power supply rejection ratio. The digital partof the DACis
fully supplied from the chip core supply.
8.8 Clock circuit and oscillator
The chip hasan on-chip crystal clock oscillator. The block
diagram of this Pierce oscillator is shown in Fig.13. The
active element needed to compensate for the loss
resistance of the crystal is the block Gm. This block is
placed between the external pins OSC_IN
and OSC_OUT. The gain of the oscillator is internally
controlled by the AGC block. A sine wave with a
peak-to-peak voltage close to the oscillator power supply
voltageis generated. The AGC block prevents clippingof
the sine wave and therefore the higher harmonics are as
low as possible. At the same time the voltage of the sine
waveisas highas possible which reduces the jitter going
from sine wave to the clock signal.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.8.1 SUPPLYOF THE CRYSTAL OSCILLATOR
The power supply connections of the oscillator are
separated from the other supply lines. This is done to
minimize the feedback from the ground bounceof the chip
to the oscillator circuit. Pin VSS(OSC) is used as ground
supply and pin VDD(OSC) as positive supply. A series
resistor plus capacitance is required for proper operating
on pin VDD(OSC), see Figs 25 and 26. See also important
remark in Section 8.10.
8.9 The phase-locked loop circuit to generate the
DSPs and other clocks
There are several reasons why a PLL circuit is used to
generate the clock for the DSPs: The PLL makes it possible to switch in the rare cases
that tuning on a multiple of the DSP clock frequency
occurstoa slightly higher frequencyfor the clockof the
DSP.In this wayan undisturbed reception with respect
to the DSP clock frequency is possible. Crystalsfor the crystal oscillatorin the rangeof twice the
required DSP clock frequency, so approximately
100 MHz, are always third overtone crystals and must
alsobe manufacturedon customerdemand. This makes
these crystals expensive. The PLL1 enables the useof
a crystal running in the fundamental mode and also a
general available crystal canbe chosen. For this circuit 256× 44.1 kHz= 11.2896 MHz crystalis chosen.This
type of crystal is widely used. Althougha multipleof the frequencyof the used crystal 11.2896 MHz falls within the FM reception band, this
will not disturb the reception because the relatively low
frequency crystal is driven in a controlled way and the
sine wave of the crystal has in the FM reception band
only very minor harmonics.
8.10 Supply of the digital part (VDDD3V1to VDDD3V4)
The supply voltage on pins VDDD3V1to VDDD3V4 must be
for at least 10 ms earlier active than the supply voltage
applied to pin VDD(OSC).
8.11 CL_GEN, audio clock recovery block
Whenan externalI2 S-busor SPDIF sourceis connected,
the FSDAC circuitry needs an 256fs related clock. This
clock is recovered from either the incoming WS of the
digital serial input or the WS derived from the
SPDIF1/SPDIF2 input. There is also a possibility to
provide the chip withan external clock,in that caseit must
be a 256fs clock with a fixed phase relation to the source.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.12 External control pins
8.12.1 DSP1
For external control two input pins have been
implemented. The statusof these pins canbe changedby
applying a logic level. The status is saved in the DSP1
status register. The function of each pin depends on the
DSP1 program.
To control external devices two output pins are
implemented. The statusof these pinsis controlledby the
DSP program.
Functionof these ‘control pins’ canbe foundina separate
manual and is rom_code dependent.
8.12.2 DSP2
For external control four configurable I/O pins have been
implemented. Via the I2 C-bus these four pins can be
independently configuredas inputor output. The statusof
these pins canbe changedby applyinga logic level (input
mode). The status is saved in the DSP2 status register.
The function of each pin depends on the I2C-bus setting
and DSP2 program.
Functionof these ‘control pins’ canbe foundina separate
manual and is rom_code dependent.
8.13I2 C-bus control (pins SCL and SDA)
General information about the I2 C-bus can be found in
“The I2C-bus and how to use it”. This document can be
ordered using the code 9398 393 40011. For the external
control of the SAA7706H device a fast I2 C-bus is
implemented. This is a 400 kHz bus which is
downward-compatible with the standard 100 kHz bus.
There are two different types of control instructions: Instructions to control the DSP program, programming
the coefficient RAM and reading the values of
parameters (level, multipath etc.) Instructions controlling the data flow; such as source
selection, IAC control and clock speed.
The detailed descriptionof theI2 C-bus and the description
of the different bits in the memory map is given in
Chapter9.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
8.14 Digital serial inputs/outputs and SPDIF inputs
8.14.1 GENERAL DESCRIPTION DIGITAL SERIAL AUDIO
INPUTS/OUTPUTS
For communication with external digital sources a digital
serial bus is implemented. It is a serial 3-line bus, having
one line for data, one line for clock and one line for the
word select. For external digital sources the SAA7706H
acts as a slave, so the external source is master and
supplies the clock.
The digital serial inputis capableof handling multiple input
formats. The input is capable of handling Philips I2S-bus
and LSB-justified formats of 16, 18,20 and24 bits word
sizes. The sampling frequency can be either
44.1or48 kHz. See Fig.15 for the general waveform
formats of all possible formats.
The number of bit clock (BCK) pulses may vary in the
application. When the applied word lengthis smaller than bits (internal resolution of DSP2), the LSB bits will get
internally a zero value; when the applied word length
exceeds 24 bits then the LSBs are skipped.
It should be noted that: Two digital sources can not be used at the same time Maximum number of bit clocks per word select (WS) is
limited to64 The word select (WS) must have a duty cycle of 50%.
8.14.2 GENERAL DESCRIPTION SPDIF INPUTS (SPDIF1
AND SPDIF2)
For communication with external digital sources also an
SPDIF input can be used. The two SPDIF input pins can
be connected via an analog multiplexer to the SPDIF
receiver. It is a receiver without an analog PLL that
samples the incoming SPDIF witha high frequency.In this
way the data is recovered synchronously on the applied
system clock.
From the SPDIF signal a three wire serial bus
(e.g. I2S-bus) is made, consisting of a word select, data
andbit clock line. The sample frequencyfs depends solely
on the SPDIF signal input accuracy and both 44.1 and kHz are supported.
This chip does not handle the user data bits, channel
status bits and validity bits of the SPDIF stream, but only
the audiois givenatits outputs. Some rom_codesdo take
care of the pre-emphasis bit of the SPDIF stream.
The bitsin the audio space arealways decoded regardless any status bits e.g.‘copyprotected’, ‘professional mode’
or ‘data mode’. The DAC is not muted in the event of a
non-linear PCM audio, however the bit is observable via
theI2 C-bus.A few other channel status bits are available.
There are5 control signals available from the SPDIF input
stage. These are connected to flags of DSP2. For more
details see separate manual.
These 5 control signals are: Signals to indicate the sample frequency of the SPDIF
signal: 44.1 and 48 kHz (32 kHz is not supported) A lock signal indicating if the SPDIF input is in lock The pre-emphasis bit of the SPDIF audio stream The pcm_audio/non-pcm_audiobit indicatingifan audio
or data stream is detected. The FSDAC output will not mutedin the eventofa non-audio PCM stream. This
status bit can be read via the I2 C-bus, the
microcontroller can decide to mute the DAC (via
pin POM).
The design fulfils the digital audio interface specification
“IEC 60958-1 Ed2, part1, general part IEC 60958-3 Ed2,
part 3, consumer applications”.
It should be noted that: The SPDIF input may only be used in the ‘consumer
mode’ specified in the digital audio interface
specification Only one of the two SPDIF sources can be used
(selected) at the same time The FSDAC will not (automatically) be muted in the
event of a non-audio stream Two digital sources can not be used at the same time Supported sample frequencies are 44.1 and48 kHz.
Philips Semiconductors Product specification
Car radio Digital Signal Processor (DSP) SAA7706H
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8.14.3 DIGITAL DATA STREAM FORMATS
