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RIVA128ZXNVIDIAN/a525avai128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZXNIVRN/a20avai128-BIT 3D MULTIMEDIA ACCELERATOR


RIVA128ZX ,128-BIT 3D MULTIMEDIA ACCELERATORTABLE OF CONTENTS1 RIVA128ZX 300PBGA DEVICE PINOUT...... 42 PIN DESCRIPTIONS . 52.1 ACCELERATED GRA ..
RIVA128ZX ,128-BIT 3D MULTIMEDIA ACCELERATORFEATURES ....... 458.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC ... 468.3 TIMING DIAGRA ..
RJH60F5DPK , Silicon N Channel IGBT High Speed Power Switching
RJH60F7ADPK , Silicon N Channel IGBT High Speed Power Switching
RJJ0101DPD , P Channel Power MOS FET High Speed Switching
RJJ0101DPD , P Channel Power MOS FET High Speed Switching
RSS090 N03 , Switching (30V, 9A)
RSS090N03 , Switching (30V, 9A)
RSS090N03 , Switching (30V, 9A)
RSS120N03 , Switching (30V, 12A)
RSS125N03 , Switching (30V, 12.5A)
RSS140N03 , Switching (30V, 14A)


RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
128-BIT 3D MULTIMEDIA ACCELERATOR
PRELIMINARY DATA
RIVA 128ZX
BLOCK DIAGRAM

Palette DAC
YUV- RGB,
Graphics Engine
128bit2D
Direct3D
8MByteVGA
DMABus
Internal
Bus
CCIR656
Video
PCI/AGP
128bit
interface
Monitor/
1.6 GByte/s
Internal Bus
Bandwidth
DMA Engine
Video Port&Y scaler
Host
Interface
FIFO/
DMA
Pusher
DMA Engine
SDRAM/SGRAM
Interface
KEY FEATURES
Fast 32-bit VGA/SVGA High performance 128-bit 2D/GUI/DirectDraw
Acceleration Interactive, Photorealistic Direct3D Accelera-
tion with advanced effects Pinout backwards compatible with RIVA 128 Massive 1.6Gbytes/s, 100MHz 128-bit wide
8MByte SGRAM framebuffer interface Adds 16Mbit SDRAM support for cost sensitive
8MByte framebuffer applications Video Acceleration for DirectDraw/DirectVideo,
MPEG-1/2 and Indeo Planar 4:2:0 and packed 4:2:2 Color Space
Conversion X andY smoothup and down scaling 250MHz Palette-DAC supporting up to
1600x1200@85Hz NTSC and PAL output with flicker-filter Multi-function Video Port and serial interface Bus mastering DMA Accelerated Graphics Port
(AGP) 1.0 Interface supporting 133MHz 2X
data transfer mode Bus mastering DMA PCI 2.1 interface ACPI power management interface support 0.35 micron 5LM CMOS 300 PBGA
DESCRIPTION

The RIVA128ZX offers unparalleled 2D and 3D
performance, meetingall the requirementsof the
mainstream PC graphics market and Microsoft’s
PC’97. RIVA128ZX combines all the featuresof
RIVA 128 plus 8MByte SDRAM and SGRAM
based framestore support and AGP 2X data trans-
fer.It provides the most advanced Direct3D ac-
celeration solution and delivers leadership VGA, and Video performance, enablinga rangeof
applications from 3D games throughto DVD, In-
tercast and video conferencing.
RIVA128ZX 128-BIT 3D MULTIMEDIA ACCELERATOR
TABLE OF CONTENTS RIVA128ZX 300PBGA DEVICE PINOUT....................................................................................... 4 PIN DESCRIPTIONS ...................................................................................................................... 5

2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE..................................................... 5
2.2 PCI 2.1 LOCAL BUS INTERFACE ........................................................................................ 5
2.3 FRAMEBUFFER INTERFACE .............................................................................................. 7
2.4 VIDEO PORT......................................................................................................................... 7
2.5 DEVICE ENABLE SIGNALS.................................................................................................. 8
2.6 DISPLAY INTERFACE.......................................................................................................... 8
2.7 VIDEO DAC AND PLL ANALOG SIGNALS .......................................................................... 8
2.8 POWER SUPPLY ..................................................................................................................8
2.9 TEST...................................................................................................................................... 9 OVERVIEW OF THE RIVA128ZX .................................................................................................. 10
3.1 BALANCED PC SYSTEM...................................................................................................... 10
3.2 HOST INTERFACE ............................................................................................................... 10
3.3 2D ACCELERATION ............................................................................................................. 11
3.4 3D ENGINE ........................................................................................................................... 11
3.5 VIDEO PROCESSOR............................................................................................................ 11
3.6 VIDEO PORT......................................................................................................................... 12
3.7 DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER ......................................... 12
3.8 SUPPORT FOR STANDARDS.............................................................................................. 12
3.9 RESOLUTIONS SUPPORTED.............................................................................................. 12
3.10 CUSTOMER EVALUATION KIT ............................................................................................ 13
3.11 TURNKEY MANUFACTURING PACKAGE........................................................................... 13 ACCELERATED GRAPHICS PORT (AGP) INTERFACE ............................................................. 14
4.1 RIVA128ZX AGP INTERFACE.............................................................................................. 15
4.2 AGP BUS TRANSACTIONS.................................................................................................. 15 PCI 2.1 LOCAL BUS INTERFACE................................................................................................. 23
5.1 RIVA128ZX PCI INTERFACE ............................................................................................... 23
5.2 PCI TIMING SPECIFICATION............................................................................................... 24 FRAMEBUFFER INTERFACE ....................................................................................................... 30
6.1 SDRAM INTERFACE ............................................................................................................ 31
6.2 SGRAM INTERFACE ............................................................................................................ 32
6.3 SDRAM/SGRAM ACCESSES AND COMMANDS ................................................................ 35
6.4 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS ................................................................ 37
6.5 FRAMEBUFFER INTERFACE TIMING SPECIFICATION .................................................... 37 VIDEO PLAYBACK ARCHITECTURE........................................................................................... 42
7.1 VIDEO SCALER PIPELINE ................................................................................................... 43 VIDEO PORT.................................................................................................................................. 45
8.1 VIDEO INTERFACE PORT FEATURES ............................................................................... 45
8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC .............................. 46
8.3 TIMING DIAGRAMS.............................................................................................................. 47
8.4 656 MASTER MODE ............................................................................................................. 51
8.5 VBI HANDLINGIN THE VIDEO PORT ................................................................................. 52
8.6 SCALINGIN THE VIDEO PORT ........................................................................................... 52 BOOT ROM INTERFACE...............................................................................................................53
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX POWER-ON RESET CONFIGURATION........................................................................................ 55 DISPLAY INTERFACE................................................................................................................... 57
11.1 PALETTE-DAC ...................................................................................................................... 57
11.2 PIXEL MODES SUPPORTED ............................................................................................... 57
11.3 HARDWARE CURSOR ......................................................................................................... 58
11.4 SERIAL INTERFACE.............................................................................................................59
11.5 ANALOG INTERFACE .......................................................................................................... 60
11.6 TV OUTPUT SUPPORT........................................................................................................ 61 IN-CIRCUIT BOARD TESTING ...................................................................................................... 63
12.1 TEST MODES ....................................................................................................................... 63
12.2 CHECKSUM TEST ................................................................................................................63 ELECTRICAL SPECIFICATIONS .................................................................................................. 64
13.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................ 64
13.2 OPERATING CONDITIONS .................................................................................................. 64
13.3 DC SPECIFICATIONS........................................................................................................... 64
13.4 ELECTRICAL SPECIFICATIONS.......................................................................................... 65
13.5 DAC CHARACTERISTICS .................................................................................................... 65
13.6 FREQUENCY SYNTHESIS CHARACTERISTICS ................................................................ 66 PACKAGE DIMENSION SPECIFICATION .................................................................................... 67
14.1 300 PIN BALL GRID ARRAY PACKAGE .............................................................................. 67 REFERENCES................................................................................................................................ 68 ORDERING INFORMATION .......................................................................................................... 68
APPENDIX............................................................................................................................................... 69 PCI CONFIGURATION REGISTERS............................................................................................. 69

A.1 REGISTER DESCRIPTIONS FOR PCI CONFIGURATION SPACE .................................... 69
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX RIVA128ZX 300PBGA DEVICE PINOUT
NOTES NIC=No Internal Connection.Donot connectto these pins. VDD=3.3V Signals denotedwithan asteriskare definedfor future expansion. SeePin Descriptions, Section2, page5for details.
6789

FBD[4]
FBD[6]
FBD[7]
FBD[17]
FBD[19]
FBD[21]
FBD[23]
FBDQM[2]
FBA[0]
FBA[2]
FBA[4]
FBA[6]
FBA[8]
FBDQM[5]
FBD[41]
FBD[43]
FBD[45]
FBD[47]
FBD[56]
FBD[57]
FBD[3]
FBD[5]
FBD[16]
FBD[18]
FBD[20]
FBD[22]
FBDQM[0]
FBA[9]
FBA[1]
FBA[3]
FBA[5]
FBA[7]
FBCLK1
FBDQM[7]
FBD[40]
FBD[42]
FBD[44]
FBD[46]
FBD[58]
FBD[59]
FBD[1]
FBD[2]
FBD[28]
FBD[27]
FBD[26]
FBD[25]
FBD[15]
FBD[13]
FBD[11]
FBD[9]
FBDQM[1]
FBWE#
FBRAS#
FBA[10]
FBDQM[4]
FBD[55]
FBD[54]
FBD[53]
FBD[6
FBD[61]
FBCLK0
FBD[0]
FBD[29]
FBD[30]
VDD
FBD[24]
FBD[14]
FBD[12]
FBD[10]
FBD[8]
FBDQM[3]
FBCAS#
FBCS0
FBCS1
FBDQM[6]
VDD
FBD[52]
FBD[51]
FBD[62]
FBD[63]
SCL
FBCLK2
FBD[31]
VDD
NIC
VDD
VDD
VDD
FBCKE
VDD
VDD
VDD
VDD
FBD[50]
FBD[39]
FBD[38]
MP_AD[6]
NIC
SDA
FBCLKFB
VDD
VDD
FBD[48]
FBD[49]
FBD[37]
FBD[36]
MPFRAME#
MP_AD[7]
MP_AD[5]
MP_AD[4]
MPCLAMP
VDD
FBD[35]
FBD[34]
FBD[33]
FBD[32]
MP_AD[2]
MPSTOP#
MPCLK
MP_AD[3]
VDD
NIC
FBDQM[12]
FBDQM[14]
FBDQM[15]
FBDQM[13]
FBDQM[8]
MPDTACK#
MP_AD[1]
MP_AD[0]
GND
GND
GND
GND
FBD[118]
FBD[119]
FBD[105]
FBD[104]
FBDQM[9]
FBD[87]
FBDQM[10]
FBDQM[11]
GND
GND
GND
GND
FBD[116]
FBD[117]
FBD[107]
FBD[106]
FBD[86]
FBD[85]
FBD[72]
FBD[73]
GND
GND
GND
GND
FBD[114]
FBD[115]
FBD[109]
FBD[108]
FBD[84]
FBD[83]
FBD[74]
FBD[75]
GND
GND
GND
GND
FBD[112]
FBD[113]
FBD[111]
FBD[110]
FBD[82]
FBD[81]
FBD[76]
FBD[77]
NIC
NIC
FBD[102]
FBD[103]
FBD[121]
FBD[120]
FBD[80]
FBD[71]
FBD[78]
FBD[79]
VDD
VDD
FBD[100]
FBD[101]
FBD[123]
FBD[122]
FBD[70]
FBD[69]
FBD[88]
FBD[89]
NIC
NIC
FBD[98]
FBD[99]
FBD[125]
FBD[124]
FBD[68]
FBD[67]
FBD[90]
VDD
NIC
HOSTVDD
HOSTVDD
HOST-
CLAMP
HOSTVDD
HOST-
CLAMP
HOSTVDD
HOST-
CLAMP
VDD
FBD[97]
FBD[127]
FBD[126]
FBD[66]
FBD[65]
FBD[92]
FBD[91]
HOST-
CLAMP
XTALOUT
PCIRST#
AGPST[1]
PCIAD[30]
PCIAD[26]
PCICBE#[3]
PCIAD[20]
PCIAD[16]
PCITRDY#
PCIPAR
HOSTVDD
PCICBE#[0]
FBD[96]
VIDVSYNC
VIDHSYNC
FBD[64]
FBD[95]
RED
DACVDD
VREF
PCIINTA#
PCIGNT#
AGPPIPE#
PCIAD[28]
PCIAD[24]
PCIAD[22]
PCIAD[18]
PCIFRAME#
PCISTOP#
PCIAD[15]
PCIAD[11]
PCIAD[
PCIAD[2]
TESTMODE
ROMCS#
FBD[93]
FBD[94]
BLUE
COMP
PLLVDD
PCIREQ#
AGPST[2]
PCIAD[31]
PCIAD[27]
AGPAD-
STB1
PCIAD[21]
PCIAD[17]
PCIIRDY#
PCICBE#[1]
PCIAD[13]
PCIAD[9]
PCIAD[4]
PCIAD[0]
PCIAD[7]
PCIAD[5]
GREEN
GND
RSET
XTALIN
PCICLK
AGPST[0]
PCIIDSEL/
AGPRBF#
PCIAD[29]
PCIAD[25]
PCIAD[23]
PCIAD[19]
PCICBE#[2]
PCI-
DEVSEL#
PCIAD[14]
PCIAD[12]
PCIAD[10]
PCIAD[8]
AGPAD-
STB0
PCIAD[3]
PCIAD[1]
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX PIN DESCRIPTIONS
2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE
2.2 PCI 2.1 LOCAL BUS INTERFACE
Signal I/O Description
AGPST[2:0]
I AGP status bus providing information fromthe arbiterto the RIVA128ZXon whatit may
do. AGPST[2:0] only havemeaningto the RIVA128ZXwhen PCIGNT#is asserted. When
PCIGNT#
is de-asserted these signals haveno meaning and mustbe ignored.
000 Indicates that previously requested low priority reador flush datais being
returnedto the RIVA128ZX.
001 Indicates that previously requested high priority read datais being returnedto
the RIVA128ZX.
010 Indicates that the RIVA128ZXisto provide low priority write data fora previous
enqueued write command.
011 Indicates that the RIVA128ZXisto provide high priority write datafora previous
enqueued write command.
100 Reserved
101 Reserved
110 Reserved
111 Indicates that the RIVA128ZX has been given permissionto starta bus transac-
tion. The RIVA128ZX may enqueue AGP requestsby asserting AGPPIPE#or
starta PCI transactionby asserting PCIFRAME#. AGPST[2:0] are alwaysan
output from the Core Logic (AGP chipset) andan inputto the RIVA128ZX.
AGPRBF#
O Read Buffer Full indicates when the RIVA128ZXis readyto accept previously requested
low priority read dataor not. When AGPRBF#is asserted the arbiteris not allowedto
return (low priority) read datato the RIVA128ZX.This signal shouldbe pulledupviaa
4.7KΩ resistor (althoughitis supposedtobe pulledupby the motherboard chipset).
AGPPIPE#
O Pipelined Readis assertedby RIVA128ZX (when the current master)to indicateafull
width read addressistobe enqueuedby the target. The RIVA128ZX enqueues one
request each rising clock edge while AGPPIPE#is asserted. When AGPPIPE#is de-
assertedno new requests are enqueued across PCIAD[31:0]. AGPPIPE#isa sustained
tri-state signal from the RIVA128ZX andisan inputto the target (the core logic).
AGPADSTB0,
AGPADSTB1

I/O Bus strobe signals providing timingfor AGP2X data transfer modeon PCIAD[15:00] and
PCIAD[31:16]
respectively. The agent thatis supplying data drives these signals.
Signal I/O Description
PCICLK
I PCI clock. This signal provides timingforall transactionson the PCI bus, exceptfor
PCIRST#
and PCIINTA#.All PCI signals are sampledon the rising edgeof PCICLK and
all timing parameters are defined with respectto this edge.
PCIRST#
I PCI reset. This signalis usedto bring registers, sequencers and signalstoa consistent
state. When PCIRST#is assertedall output signals are tristated.
PCIAD[31:0]
I/O 32-bit multiplexed address and data bus.A bus transaction consistsofan address phase
followedby oneor more data phases.
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
PCICBE[3:0]#
I/O Multiplexedbus command and byte enable signals. During the address phaseofa trans-
action PCICBE[3:0]# define the bus command, during the data phase PCICBE[3:0]# are
usedas byte enables. The byte enables are validfor the entire data phase and determine
which byte lanes contain valid data. PCICBE[0]# appliesto byte0 (LSB) and PCICBE[3]#
appliesto byte3 (MSB).
When connectedto AGP these signals carry differentcommands than PCI when requests
are being enqueued usingAGPPIPE#. Validbyte informationis provided during AGPwrite
transactions. PCICBE[3:0]# are not used during the returnof AGP read data.
PCIPAR
I/O Parity. This signalis the even paritybit generated across PCIAD[31:0] and
PCICBE[3:0]#. PCIPAR
is stable and valid one clock after the address phase. For data
phases PCIPARis stable and valid one clock after either PCIIRDY#is assertedona write
transactionor PCITRDY#is assertedona read transaction. Once PCIPARis valid,it
remains valid until one clock after completionofthe current data phase. The master drives
PCIPAR
for address and write data phases; the target drives PCIPARfor read data
phases.
PCIFRAME#
I/O Cycle frame. This signalis drivenby the current masterto indicate the beginningofan
access andits duration. PCIFRAME#is assertedto indicate thata bus transactionis
beginning. Data transfers continue while PCIFRAME#is asserted. When PCIFRAME#is
deasserted, the transactionisin the finaldata phase.
PCIIRDY#
I/O Initiator ready.This signal indicates the initiator’s(bus master’s)abilityto complete the cur-
rent data phaseof the transaction. See extended descriptionfor PCITRDY#.
When connectedto AGP this signal indicates the initiator (AGP compliant master)is ready provideall write datafor the current transaction. Once PCIIRDY#is assertedfora write
operation, the masteris not allowedto insert wait states. The assertionof PCIIRDY#for
reads, indicates that the masteris readyto transfera subsequent blockof read data. The
masteris never allowedto inserta wait state during the initial blockofa read transaction.
However,it may insert wait states after each block transfers.
PCITRDY#
I/O Target ready. This signal indicates the target’s (selected device’s)abilityto complete the
current data phaseof the transaction.
PCITRDY#
is usedin conjunction with PCIIRDY#.A data phaseis completedon any clock
when both PCITRDY# and PCIIRDY# are sampledas being asserted. Duringa read,
PCITRDY#
indicates that valid datais presenton PCIAD[31:0]. Duringa write,it indicates
the targetis preparedto accept data. Wait cycles are inserted until both PCIIRDY# and
PCITRDY#
are asserted together.
When connectedto AGP this signal indicates theAGP compliant targetis readyto provide
read datafor the entire transaction (when transaction can complete within four clocks)or readyto transfera (initialor subsequent) blockof data, when the transfer requires more
than four clocksto complete. The targetis allowedto insert wait states after each block
transferson both read and write transactions.
PCISTOP#
I/O PCISTOP# indicates that the current targetis requesting the masterto terminate the cur-
rent transaction.
PCIIDSEL
I Initialization device select. This signalis usedasa chip select during configuration read
and write transactions.
For AGP applications note that IDSELis nota pinon the AGP connector.The RIVA128ZX
performs the device select decode internally withinits host interface.Itis not requiredto
connect the AD16 signalto the IDSEL pinas suggestedin the AGP specification.
PCIDEVSEL#
I/O Device select. When actingasan output PCIDEVSEL# indicates that the RIVA128ZX has
decoded the PCI address andis claiming the current accessas the target.Asan input
PCIDEVSEL#
indicates whether any other deviceon the bus has been selected.
PCIREQ#
O Request. This signalis assertedby the RIVA128ZXto indicateto the arbiter thatit desires become masterof the bus.
Signal I/O Description
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
2.3 FRAMEBUFFER INTERFACE
2.4 VIDEO PORT
PCIGNT#
I Grant. This signal indicatesto the RIVA128ZX that accessto the bus has been granted
andit can now become bus master.
When connectedto AGP additional informationis providedon AGPST[2:0] indicating that
the masteris the recipientof previously requested read data (highor low priority),itisto
provide write data (highor low priority),fora previously enqueued write commandor has
been given permissionto starta bus transaction (AGPor PCI).
PCIINTA#
O Interrupt request line. This open drain outputis asserted and deasserted asynchronously PCICLK.
Signal I/O Description
FBD[127:0]
I/O The 128-bit memory data bus.
FBD[31:0]
are also usedto accessupto 64KBytesof 8-bit ROMor Flash ROM, using
FBD[15:0]
as address ROMA[15:0], FBD[31:24]as ROMD[7:0], FBD[17]as ROMWE#
and FBD[16]as ROMOE#.
FBA[10:0]
O Memory Address bus. Configuration strapping options are also decodedon these signals
during PCIRST#as describedin Section 10, page 55.
FBRAS#
O Memory Row Address Strobeforall memory devices.
FBCAS#
O Memory Column Address Strobeforall memory devices.
FBCS[1:0]#
O Memory Chip Select strobes. For SDRAM the FBCS[1] pin provides the memory’s inter-
nal bank selectbit (BA/A11).
FBWE#
O Memory Write Enable strobeforall memory devices.
FBDQM[15:0]
O Memory Data/Output Enable strobes.
FBCLK0,
FBCLK1,
FBCLK2
Memory Clock signals. Separate clock signals FBCLK0 and FBCLK1 are providedfor
each bankof memoryfor reduced clock skew and loading. Detailsof recommended mem-
ory clock layout are givenin Section 6.4, page 37.
FBCLKFB
I Framebuffer clock feedback. FBCLK2is fed backto FBCLKFB.
FBCKE
O Framebuffer memory clock enable signal.
Signal I/O Description
MP_AD[7:0]
I/O Media Port 8-bit multiplexed address and data busor ITU-R-656 video data bus whenin
656 mode.
MPCLK
I 40MHz Media Port system clockor pixel clock whenin 656 mode.
MPDTACK#
I Media Port data transferacknowledgment signal.
MPFRAME#
O Initiates Media Port transfers when active, terminates transfers when inactive.
MPSTOP#
I Media Port control signal usedby the slaveto terminate transfers.
Signal I/O Description
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
2.5 DEVICE ENABLE SIGNALS
2.6 DISPLAY INTERFACE
2.7 VIDEO DAC AND PLL ANALOG SIGNALS
2.8 POWER SUPPLY
Signal I/O Description
ROMCS#
O Enables reads froman external 64Kx8or 32Kx8 ROMor Flash ROM. This signalis used conjunction with framebuffer data linesas described abovein Section 2.3.
Signal I/O Description
SDA
I/O Usedfor DDC2B+ monitor communication and interfaceto video decoder devices.
SCL
I/O Usedfor DDC2B+ monitor communication and interfaceto video decoder devices.
VIDVSYNC
O Vertical sync suppliedto the display monitor.No bufferingis required.InTV mode this sig-
nal supplies composite synctoan external PAL/NTSCencoder.
VIDHSYNC
O Horizontal sync suppliedto the display monitor.No bufferingis required.
Signal I/O Description
RED,
GREEN,
BLUE
RGB display monitor outputs. These are software configurableto drive eithera doubly ter-
minatedor singly terminated 75Ω load.
COMP
- External compensation capacitorfor the video DACs. This pin shouldbe connectedto
DACVDD
via the compensation capacitor, see Figure 66, page 60.
RSET
- A precision resistor placed between this pin and GND sets the full-scale video DAC cur-
rent, see Figure 66, page 60.
VREF
- A capacitor shouldbe placed between this pin and GNDas shownin Figure 66, page 60.
XTALIN
I A series resonant crystalis connected between these two pointsto provide the reference
clockfor the internal MCLK and VCLK clock synthesizers, see Figure66 and Table20,
page 60. Alternately,an external LVTTL clock oscillator output maybe driven into XTA-
LOUT,
connecting XTALINto GND. For designs supporting TV-out, XTALOUT shouldbe
drivenbya reference clockas describedin Section 11.6, page 61.
XTALOUT
O
Signal I/O Description
DACVDD
P Analog power supplyfor the video DACs.
PLLVDD
P Analog power supplyforall clock synthesizers.
VDD
P Digital power supply.
GND
P Ground.
MPCLAMP
P MPCLAMPis connectedto +5Vto protect the 3.3V RIVA128ZX from external devices
which will potentially drive5V signal levels onto the Video Port input pins.
HOSTVDD
P HOSTVDDis connectedto the Vddq 3.3 pinson the AGP connector. Thisis the supply
voltagefor the I/O buffers andis isolated from the core VDD.On AGP designs these pins
are also connectedto the HOSTCLAMP pins. On PCI designs they are connectedto the
3.3V supply.
HOSTCLAMP
P HOSTCLAMPis the supply signalling rail protectionfor the host interface.In AGP designs
these signals are connectedto Vddq 3.3. For PCI designs they are connectedto the I/O
power pins (V(I/O)).
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
2.9 TEST
Signal I/O Description
TESTMODE
I For designs which willbe tested in-circuit, this pin shouldbe connectedto GND througha
10KΩ pull-down resistor, otherwise this pin shouldbe connected directlyto GND. When
TESTMODE
is asserted, MP_AD[3:0] are reassignedas TESTCTL[3:0] respectively.
Informationon in-circuit testis givenin Section 12, page 63.
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX OVERVIEW OF THE RIVA128ZX
The RIVA128ZXis the first 128-bit 3D Multimedia
Acceleratorto offer unparalleled 2D and 3D per-
formance, meeting all the requirements of the
mainstream PC graphics market and Microsoft’s
PC’97. The RIVA128ZX introduces the most ad-
vanced Direct3D acceleration solution and also
delivers leadership VGA, 2D and Video perfor-
mance, enablinga rangeof applications from 3D
games throughto DVD, Intercast and video con-
ferencing.
3.1 BALANCED PC SYSTEM
The RIVA128ZXis designedto leverage existing system resources such as system memory,
high bandwidth internal buses and bus master ca-
pabilities. The synergy between the RIVA128ZX
graphics pipeline architecture and thatof the cur-
rent generation PCI and next generation AGP plat-
forms, defines ground breaking performance lev-
elsat the cost point currently required for main-
stream PC graphics solutions.
Execute versus DMA models

The RIVA128ZXis architectedto optimize PC sys-
tem resourcesina manner consistent with the
AGP “Execute” model.
In this model texture map
data for 3D applicationsis storedin system mem-
ory and individual texels are accessedas needed the graphics pipeline. Thisisa significant en-
hancement over the DMA model where entire tex-
ture maps are transferred into off-screen frame-
buffer memory.
The advantagesof the Execute versus the DMA
model are: Improved system performance since only the
required texels and not the entire texture map,
cross the bus. Substantial cost savings since all the frame-
bufferis usable for the displayed screen andZ
buffer andno partofitis requiredto be dedicat-to texture storageor texture caching. Thereis no software overheadin the Direct3D
driverto manage texture caching between ap-
plication memory and the framebuffer. extend the advantagesof the Execute model,
the RIVA128ZX’s proprietary texture cache and
virtual DMA bus master design overcomes the
bandwidth limitationof PCI, by sustaininga high
texel throughput with minimum bus utilization. The
host interface supports burst transactions upto
133MHz and provides over 400MBytes/son AGP.
AGP accesses offer other performance enhance-
ments since they are from non-cacheable memory
(no snoop) and canbe low priorityto prevent pro-
cessor stalls,or high priorityto prevent graphics
engine stalls.
Buildinga balanced system

RIVA128ZXis architectedto provide the levelof graphics performance and quality availablein
top arcade platforms. To provide comparable
scene complexityin the 1997 time-frame, proces-
sors will haveto achieve new levelsof floating
point performance. Profiles have shown that 1997
mainstream CPUs will be ableto transform over1
millionlit, meshed triangles/sat 50% utilization us-
ing Direct3D. This represents an orderof magni-
tude performance increase over anything attain-
ablein 1996 PC games. builda balanced system the graphics pipeline
must match the CPU’s performance.It mustbe ca-
pableof renderingat least1 million polygons/sin
orderto avoid CPU stalls. Factors affecting this
system balance include: Direct3D compatibility. Minimizing the differ-
ences between the hardware interface and the
Direct3D data structures. Triangle setup. Minimizing the numberof for-
mat conversions and delta calculations doneby
the CPU. Display-list processing. Avoiding CPU stallsby
allowing the graphics pipelineto execute inde-
pendentlyof the CPU. Vertex caching. Avoids saturating the host in-
terface with repeated vertices, lowering thetraf-
ficon the bus and reducing system memory col-
lisions. Host interface performance.
3.2 HOST INTERFACE
The host interface boosts communication between
the host CPU and the RIVA128ZX. The optimized
interface performs burst DMA bus mastering for
efficient and fast data transfer. 32-bit PCI version 2.1or AGP version 1.0 Burst DMA Master and target 33MHz PCI clock rate, 66MHz AGP clock rate
and AGP 2X mode Supports over 100MBytes/s with 33MHz PCIto
over 400MBytes/son AGP 2X mode Implements read buffer postingon AGP
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX Fully supports the “Execute” modelon both PCI
and AGP
3.3 2D ACCELERATION
The RIVA128ZX’s 2D rendering engine delivers
industry-leading Windows acceleration perfor-
mance: 100MHz 128-bit graphics engine optimized for
single cycle operation into the 128-bit memory
interface supportingupto 1.6GBytes/s Acceleration functions optimized for minimal
software overhead on key GDI calls Extensive support for DirectDraw in
Windows95 including optimized Direct Frame-
buffer (DFB) access with Write-combining Accelerated primitives including BLT, transpar-
ent BLT, stretchBLT, points, lins, lines,
polylines, polygons, fills, patterns, arbitrary
rectangular clipping and improved text render-
ing Pipeline optimized for multiple color depths in-
cluding8, 15, 24, and30 bits per pixel DMA Pusher allows the 2D graphics pipelineto
load rendering methods optimizing
RIVA128ZX/host multi-tasking Executionofall 256 Raster Operations (as de-
fined by Microsoft Windows)at8, 15, 24 and
30-bit color depths 15-bit hardware color cursor Hardware color dithering Multi buffering (Double, Triple, Quad buffering)
for smooth animation
3.4 3D ENGINE
Triangle setup engine
Setup hardware optimized for Microsoft’s
Direct3D API 5Gflop floating point geometry processor Slope and setup calculations Accepts IEEE Single Precision format usedin
Direct3D Efficient vertex caching
Rendering engine

The RIVA128ZX Multimedia Accelerator inte-
grates an orthodox 3D rendering pipeline and tri-
angle setup function which not only fully utilizes
the capabilitiesof the Accelerated Graphics Port,
but also supports advanced texture mapped 3D
over the PCI bus. The RIVA128ZX 3D pipeline of-
fersto Direct3Dor similar APIs advanced triangle
rendering capabilities: Rendering pipeline optimized for Microsoft’s
Direct3D
API Perspective correct true-color Gouraud lighting
and texture mapping Full 32-bit RGBA texture filter and Gouraud
lighting pixel data path Alpha blending for translucency and transpar-
ency Sub-pixel accurate texture mapping Internal pixel path: upto 24bits, alpha: upto8
bits Texture magnification filtering with high quality
bilinear filtering without performance degrada-
tion Texture minification filtering with MIP mapping
without performance degradation LOD MIP-mapping: filter shapeis dynamically
adjusted based on surface orientation Texture sizes from4to 2048 texelsin eitherUV Textures canbe looped and pagedin real time
for texture animation Perspective correct per-pixel fog for atmo-
spheric effects Perspective correct specular highlights Multi buffering (Double, Triple, Quad buffering)
for smooth 3D animation Multipass rendering for environmental mapping
and advanced texturing
3.5 VIDEO PROCESSOR
The RIVA128ZX Palette-DAC pipeline accelerates
full-motion video playback, sustaining 30 frames
per secondwhile retaining the highest quality color
resolution, implementing true bilinear filtering for
scaled video, and compensating for filtering losses
using edge enhancement algorithms. Advanced support for DirectDraw (DirectVideo) Windows95 Back-end hardware video scaling forvideo con-
ferencing and playback Hardware color space conversion (YUV 4:2:2
and 4:2:0) Multi-tapX andY filtering for superior image
quality Optional edge enhancement to retain video
sharpness
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX Supportfor scaled field interframingfor reduced
motion artifacts and reduced storage Per-pixel color keying Multiple video windows with hardware color
space conversion and filtering Planar YUV12 (4:2:0) to/from packed (4:2:2)
conversion for software MPEG acceleration
and H.261 video conferencing applications Accelerated playbackof industry standard co-
decs including MPEG-1/2, Indeo, Cinepak
3.6 VIDEO PORT
The RIVA128ZX Multimedia Accelerator provides
connectivity for video input devices suchas Philips
SAA7111A, ITT 3225 and Samsung KS0127
through an ITU-R-656 video input busto DVD and
MPEG2 decoders through bidirectional media port
functionality. Supported through VPE extensionsto Direct-
Draw Supports filtered down-scaling and decimation Supports real time video capture via Bus Mas-
tering DMA Serial interface for decoder control
3.7 DIRECT RGB OUTPUT TO LOW COST
PAL/NTSC ENCODER
The RIVA128ZX has also been designedto inter-
facetoa standard PALor NTSC television viaa
low cost TV encoder chip.In PALor NTSC display
modes the interlaced outputis internally flicker-fil-
tered and CCIR/EIA compliant timing reference
signals are generated.
3.8 SUPPORT FOR STANDARDS Multimedia support for MS-DOS, Windows
3.11, Windows 95, and Windows NT Acceleration for Windows 95 Direct APIs in-
cluding Direct3D, DirectDraw and DirectVideo VGA and SVGA: The RIVA128ZX has an in-
dustry standard 32-bit VGA core and BIOS sup-
port.In PCI configuration space the VGA can enabled and disabled independentlyof the
GUI. Glue-less Accelerated Graphics Port (AGP 1.0) PCI 2.1 bus interface ITU/CCIR-656 compatible video port VESA DDC2B+, DPMS, VBE 2.0 supported
3.9 RESOLUTIONS SUPPORTED
Resolution BPP 2MByte 4MByte (128-bit) 8MByte (64-bit) 8MByte (128-bit)

640x480 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz
800x600 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz
1024x768 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz - 120Hz 120Hz 120Hz
1152x864 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz - 100Hz 100Hz 100Hz
1280x1024 100Hz 100Hz 100Hz 100Hz - 100Hz 100Hz 100Hz - - t.b.d. 75Hz
1600x1200 85Hz 85Hz 85Hz 85Hz - 85Hz 85Hz 85Hz - - - 60Hz
1920x1080 8 - 85Hz 85Hz 85Hz - - 85Hz 85Hz
1920x1200 8 - 75Hz 75Hz 75Hz - - 75Hz 75Hz
1800x1440 16 - - 60Hz 60Hz
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
3.10 CUSTOMER EVALUATION KIT Customer Evaluation Kit (CEK)is available for
evaluating the RIVA128ZX. The CEK includesa
PCIor AGP adapter card designedto support the
RIVA128ZX feature set, an evaluation CD-ROM
containinga fast-installation application, extensive
device drivers and programs demonstrating the
RIVA128ZX features and performance.
This CEK includes: RIVA128ZX evaluation board and CD-ROM QuickStart install/user guide OS drivers and files Windows 3.11 Windows95 Direct X/3D Windows NT 3.5 Windows NT 4.0 Demonstration files and Game demos Benchmark programs and files
3.11 TURNKEY MANUFACTURING PACKAGE Turnkey Manufacturing Package (TMP)is avail-
ableto support OEM designs and development
throughto production.It deliversa complete man-
ufacturable hardware and software solution that
allows an OEMto rapidly design and bringto vol-
umean RIVA128ZX-based product.
This TMP includes: CD-ROM RIVA128ZX Datasheet and Application
Notes OrCAD schematic capture and PADS
layout design information Quick Start install/user guide/release notes BIOS Modification program, BIOS binaries,
utilities and BIOS Modification Guide docu-
mentation Bring-up and OEM Production Diagnostics Software and Utilities OS drivers and files Windows 3.11 Windows95 Direct X/3D Windows NT 3.5 Windows NT 4.0 Content developer and WWW information Partner solutions Accessto our password-protected web site for
upgrade files and release notes.
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX ACCELERATED GRAPHICS PORT (AGP) INTERFACE
The Accelerated Graphics Port (AGP)isa high performance, component level interconnect targetedat 3D
graphical display applications and basedon performance enhancementsto the PCI local bus.
Figure1.
System block diagram showing relationship between AGP and PCI buses
Backgroundto AGP

Although 3D graphics accelerationis becominga
standard featureof multimedia PC platforms, 3D
rendering generally hasa voracious appetite for
memory bandwidth. Consequently thereis upward
pressureon the PC’s memory requirement leading higher billof material costs. These trends willin-
crease, requiring high speed access to larger
amountsof memory. The primary motivation for
AGP therefore wasto contain these costs whilst
enabling performance improvements. providing significant bandwidth improvement
between the graphics accelerator and system
memory, someof the 3D rendering data structures
can be shifted into main memory, thus relieving
the pressure to increase the cost of the local
graphics memory.
Texture data are the first structures targeted for
shiftingto system memory for four reasons: Textures are generally read only, and therefore not have special access orderingor coher-
ency problems. Shifting textures balances the bandwidth load
between system memory and local graphics
memory, sincea well cached host processor
has much lower memory bandwidth require-
ments thana 3D rendering engine. Texture ac-
cess comprises perhaps the largest single com-
ponentof rendering memory bandwidth (com-
pared with rendering, display andZ buffers),so
avoiding loadingor caching texturesin graphics
local memory saves not only this componentof
local memory bandwidth, but also the band-
width necessaryto load the texture storein the
first place. Furthermore, this data must pass
through main memory anyway asitis loaded
froma mass store device. Texture sizeis dependent upon application
quality rather than on display resolution, and
therefore subjectto the greatest pressure for
growth. Texture datais not persistent;it residesin
memory onlyfor the durationof the application, any system memory spent on texture stor-
age can be returnedto the free memory heap
when the application finishes (unlike display
buffers which remainin use).
Other data structurescanbe movedto main mem-
ory but the biggest gain results from moving tex-
ture data.
Relationshipof AGPto PCI

AGPisa supersetof the 66MHz PCI Specification
(Revision 2.1) with performance enhancements
optimized for high performance 3D graphics appli-
cations.
The PCI Specificationis unmodifiedby AGP and
‘reserved’ PCI fields, encodings and pins, etc. are
not used.
AGP does not replace the need for the PCI busin
the system and the two are physically, logically,
and electrically independent.As shownin Figure1
AGP chipsetRIVA128ZX System
memory
CPU
I/O I/O I/O
PCI
AGP
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
the AGP bridge chip and RIVA128ZX are the only
devices on the AGP bus-all other I/O devices re-
main on the PCI bus.
The add-in slot defined for AGP usesa new con-
nector body (for electrical signaling reasons)
whichis not compatible with the PCI connector;
PCI and AGP boards are not mechanically inter-
changeable.
AGP accesses differ from PCIin that they are
pipelined. This compares with serialized PCI
transactions, where the address, wait and data
phases needto complete before the next transac-
tion starts. AGP transactions can only access sys-
tem memory- not other PCI devicesor CPU. Bus
mastering accesses can be either PCIor AGP-
style.
Full detailsof AGP are givenin the Accelerated
Graphics Port Interface Specification[3] published Intel Corporation.
4.1 RIVA128ZX AGP INTERFACE
The RIVA128ZX glueless interfaceto AGP 1.0is shownin Figure2.
Figure2.
AGP interface pin connections
4.2 AGP BUS TRANSACTIONS
AGP bus commands supported

The following AGP bus commands are supported the RIVA128ZX: Read Read (hi-priority)
PCI transactions on the AGP bus

PCI transactions can be interleaved with AGP
transactions including between pipelined AGP
data transfers.A basic PCI transactionon the AGP
interfaceis shownin Figure3.If the PCI targetis non AGP compliant master,it will not see
AGPST[2:0]
and the transaction appearstobeon PCI bus. For AGP aware bus masters,
AGPST[2:0]
indicate that permission touse thein-
terface has been grantedto initiatea request and
notto move AGP data.
AGP
bus
PCICBE[3:0]#
PCIAD[31:0]
AGPPIPE#

PCIDEVSEL#
PCIIRDY#
PCITRDY#
PCISTOP#
PCIIDSEL
PCIREQ#
PCIGNT#
PCICLK
PCIRST#
PCIPAR
PCIINTA#

RIVA128ZX
AGPST[2:0]#

AGPRBF#
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Figure3.
Basic PCI transaction on AGP exampleofa PCI transaction occurring between an AGP command cycle and returnof datais shown Figure4. This shows the smallest numberof cycles during whichan AGP request can be enqueued,a
PCI transaction performed and AGP read data returned.
Figure4.
PCI transaction occurring between AGP request and data
bus cmd
data_pciaddress
BE[3:0]#
111 111 xxx xxx xxxxxx
PCICLK
PCIFRAME#
PCIAD[31:0]
PCICBE[3:0]#
PCIIRDY#
PCITRDY#
PCIDEVSEL#
PCIREQ#
PCIGNT#
AGPST[2:0]
4 5 62
111 xxx 111 111 xxx111
address data D7 +1 pci_cmd BE 0000 000
xxx 00x xxx xxx
PCICLK
AGPPIPE#
PCIFRAME#
PCIAD[31:0]
PCICBE#
PCIIRDY#
PCITRDY#
PCIDEVSEL#
PCIAGPRBF#
PCIREQ#
PCIGNT#
AGPST[2:0]
2 34 5 678 9 10
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
Figure5.
Basic AGP pipeline concept
Pipeline operation

Memory access pipelining provides the main per-
formance enhancementof AGP over PCI. AGP
pipelined bus transactions share mostof the PCI
signal set, and are interleaved with PCI transac-
tions on the bus.
The RIVA128ZX supports AGP pipelined reads
witha 4-deep queueof outstanding read requests.
Pipelined reads are primarily used by the
RIVA128ZX for cache filling, the cache size being
optimized for AGP bursts. Depending on the AGP
bridge,a bandwidthofupto 248MByte/sis achiev-
able for 128-byte pipelined reads. This compares
with around 100MByte/s for 128-byte 33MHz PCI
reads. Another featureof AGPis that for smaller
sized reads the bandwidthis not significantly re-
duced. Whereas 16-byte reads on PCI transferat
around 33MByte/s, on AGP around 175MByte/sis
achievable. The RIVA128ZX actually requests
reads greater than 64 bytesin multiplesof 32-byte
transactions.
The pipe depth canbe maintainedby the AGP bus
master (RIVA128ZX) interveningina pipelined
transferto insert new requests between data re-
plies. This bus sequencingis illustratedin Figure
When the busisin an idle condition, the pipe can startedby inserting oneor more AGP access
requests consecutively. Once the data replyto
those accesses starts, that stream can be broken
(or intervened)by the bus master (RIVA128ZX)in-
serting oneor more additional AGP access re-
questsor insertinga PCI transaction. This inter-
ventionis accomplished with the bus ownership
signals, PCIREQ# and PCIGNT#.
The RIVA128ZX implements both high and low
priority reads dependingof the statusof the ren-
dering engine.If the pipelineis likelyto stall dueto
system memory read latency,a high priority read
requestis posted.
Address Transactions

The RIVA128ZX requests permission from the
bridge to use PCIAD[31:0]to initiate either an
AGP request ora PCI transaction by asserting
PCIREQ#.
The arbiter grants permission by as-
serting PCIGNT# with AGPST[2:0] equalto ”111”
(referredtoas START). When the RIVA128ZX re-
ceives STARTit must start the bus operation with- two clocksof the bus becoming available. For
example, when the busisinan idle condition when
STARTis received, the RIVA128ZX must initiate
the bus transactionon the next clock and the one
following.
Figure6 showsa single address being enqueued the RIVA128ZX. Sometime before clock1, the
RIVA128ZX asserts PCIREQ#to gain permission use PCIAD[31:0]. The arbiter grants permission indicating START on clock2.A new request
(address, command and length) are enqueued on
each clockin which AGPPIPE#is asserted. The
addressof the requesttobe enqueuedis present-on PCIAD[31:3], the lengthon PCIAD[2:0] and
the command on PCICBE[3:0]#.In Figure6 only single addressis enqueued since AGPPIPE#is
just asserted fora single clock. The RIVA128ZX
indicates that the current addressis the lastit in-
tendsto enqueue when AGPPIPE#is asserted
and PCIREQ#is deasserted (occurring on clock
3). Once the arbiter detects the assertionof AGP-
PIPE#
or PCIFRAME#it deasserts PCIGNT# on
clock4.
Bus Idle
Pipelined
data
transfer
Intervene
cycles

Pipelined AGP requests A2
Data-1 Data-2
PCI transaction Data
Data-3
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Figure6.
Single address- no delayby master
Figure7 shows the RIVA128ZX enqueuing4 requests, where the first requestis delayedby the maximum cycles allowed. STARTis indicated on clock2, but the RIVA128ZX does not assert AGPPIPE# until
clock4. Note that PCIREQ# remains assertedon clock6to indicate that the current requestis not the last
one. When PCIREQ#is deasserted on clock7 with AGPPIPE# still asserted this indicates that the current
addressis the last onetobe enqueued during this transaction. AGPPIPE# mustbe deassertedon the next
clock when PCIREQ#is sampledas deasserted.If the RIVA128ZX wantsto enqueue more requests dur-
ing this bus operation,it continues asserting AGPPIPE# untilallofits requests are enqueuedor untilit has
filledall the available request slots providedby the target.
Figure7.
Multiple addresses enqueued, maximum delayby RIVA128ZX Data Transfers data transfers are similarto 1X transfers except thatan entire8 bytes are transferred duringa single
PCICLK
period. This requires that two4 byte piecesof data are transferred across PCIAD[31:0]for each
CLK period.A read data transferis described followedbya write transfer.
111 111 xxx xxx xxxxxx xxx xxx
PCICLK
AGPPIPE#
PCIAD[31:0]
PCICBE[3:0]#
PCIREQ#
PCIGNT#
AGPST[2:0]
3 4 5 6 7 8
111 111 111 xxx xxxxxx xxx xxx A3 A4 C2 C3 C4
PCICLK
AGPPIPE#
PCIAD[31:0]
PCICBE#
PCIREQ#
PCIGNT#
AGPST[2:0]
3 4 56 7
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
Figure8.
2X Read data,no delay
Figure8 shows32 bytes being transferred during4 clocks (compared with 16 bytesin AGP1x mode). The
control signals are identical. The AGPAD_STBx signal has been added when datais transferredat8
bytes per PCICLK period. AGPAD_STBx represents AGPAD_STB0 and AGPAD_STB1 and are used the 2X interface logicto indicate when valid data ispresenton the AD bus. The controllogic (PCITRDY# this case) indicates when data can be usedby the target.
Figure9.
2X Backto back read data, no delay
Figure9 shows backto back8 byte read transactions. AGPST[2:0] are shown toggling between “000”and
“001”to illustrate that they are actually changing. However, they are not requiredto change between high
and low priorityto do backto back transactions.In this diagram, PCITRDY#is asserted on each clock
sincea new transaction starts on each clock.
00x xxx xxx xxx xxxxxx xxx +5 +6 +7+2 +3 +4
PCICLK
PCIAD[31:0]
AGPADSTBx
AGPRBF#
PCITRDY#
PCIREQ#
PCIGNT#
AGPST[2:0]

123 456 7
000 001 000 001 000xx 001 000 001 +1 H5 +1 +1 +L7 L8 +1 H6 +1 L9 +1
PCICLK
PCIAD[31:0]
AGPADSTBx
AGPRBF#
PCITRDY#
PCIGNT#
AGPST[2:0]

123456 7 8 9
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Figure 10.
2X Basic write no delay
Figure10isa basic write transaction that transfers dataat the 2X rate. Thereisno differencein the control
signals from AGP1x mode- only more datais moved. The normal control signals determine when datais
valid.
Figure 11.
QuadWord writes backto back-no delays
Figure11 illustrates multiple8 byte write operations compared with the single transfer shownin Figure 10.
When the transactions are short, the arbiteris requiredto give grantson every clockor the AD bus will not totally utilized.In this examplea new writeis startedon each rising clock edge except clock7, because
the arbiter deasserted PCIGNT#on clock6. Sincea new transactionis startedon each CLK, PCIIRDY# only deasserted on clock7.
xxx xxx 01x xxx xxxxx xxx xxx xxx +3 +4W1 +1 +5 +6 +7 BE BEBE BE BE BE BE
PCICLK
PCIAD[31:0]
PCICBE#
AGPADSTBx
PCIIRDY#
PCITRDY#
PCIREQ#
PCIGNT#
AGPST[2:0]

123456 7 8 9
01x 01x 01x 01x xxxxx 01x 01x xxx +1 +1 W7 +1W3 +1 W4 +1 W8 +1 BEBE BE BE BEBE BE BE BE BE BE
PCICLK
PCIAD[31:0]
PCICBE#
AGPADSTBx
PCIIRDY#
PCITRDY#
PCIGNT#
AGPST[2:0]
23456 7 8 9
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
AGP timing specification
Figure 12.
AGP clock specification
Table1.
AGP clock timing parameters
NOTES This rise and falltimeis measured acrossthe minimum peak-to-peak rangeas shownin Figure12.
Figure 13.
AGP timing diagram
Table2.
AGP timing parameters
Symbol Parameter Min. Max. Unit Notes

tCYC PCICLK period 15 30 ns
tHIGH PCICLK high time 6 ns
tLOW PCICLK low time 6 ns
PCICLK
slew rate 1.5 4 V/ns 1
Symbol Parameter Min. Max. Unit Notes

tVAL AGPCLKto signal valid delay (data and control
signals)
211 ns
tON Floatto active delay 2 ns
tOFF Activeto float delay 28 ns
tSU Input setup timeto AGPCLK (data and control
signals)
7ns Input hold time from AGPCLK 0ns
tCYC tHIGH tLOW
PCICLK

0.3VDD
0.4VDD
0.5VDD
0.2VDD
0.6VDD p-to-p
(minimum)
tVAL tVAL
tON
tOFF
tSU tH
data1 data2
data1 data2
AGPCLK

Output delay
Tri-state output
Input
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Figure 14.
AGP timing diagram (2X data transfer mode)
Table3.
AGP timing parameters (2X data transfer mode)
Figure 15.
AGP Strobe/Data turnaround timing diagram (2X data transfer mode)
Table4.
AGP Strobe/Data turnaround timing parameters (2X data transfer mode)
Symbol Parameter Min. Max. Unit Notes

tTSF AGPCLKto transmit strobe falling edge 2 12 ns
tTSR AGPCLKto transmit strobe rising edge 20 ns
tDVB Output data valid before strobe 1.7 ns
tDVA Output data valid after strobe 1.7 ns
tRSSU Receiver strobe setup timeto AGPCLK 6ns
tRSH Receiver strobe hold time from AGPCLK 1ns
tDSU Input datato strobe setup time 1 ns
tDH Input datato strobe hold time 1 ns
Symbol Parameter Min. Max. Unit Notes

tOND Floatto active delay -1 9 ns
tOFFD Activeto float delay 1 12 ns
tONS Strobe activeto strobe falling edge setup 6 10 ns
tOS Strobe rising edgeto strobe float delay 6 10 ns
tDVB
tDVA
tTSF tDVB
tDVA
tTSR
tRSH
tDSU
tDH
tDSU
tDH
tRSSU
Data1 Data2 Data3 Data4
Data1 Data2 Data3 Data4
AGPCLK

Output data
Output strobe
Input data
Input strobe
tOFFS
tOFFD tOND
tONS
AGPCLK
PCIAD[31:0]
AGPADSTBx
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX PCI 2.1 LOCAL BUS INTERFACE
5.1 RIVA128ZX PCI INTERFACE
The RIVA128ZX supportsa glueless interfaceto PCI 2.1 with both master and slave capabilities. The host
interfaceis fully compliant with the 32-bit PCI 2.1 specification.
The Multimedia Accelerator supports PCI bus operationupto 33MHz with zero-wait state capability and
full bus mastering capability handling burst reads and burst writes.
Figure 16.
PCI interface pin connections
Table5.
PCI bus commands supportedby the RIVA128ZX
Bus master Bus slave

Memory read and write Memory read and write
Memory read line I/O read and write
Memory read multiple Configuration read and write
Memory read line
Memory read multiple
Memory write invalidate
PCI
bus
PCICBE[3:0]#
PCIAD[31:0]
PCIFRAME#

PCIDEVSEL#
PCIIRDY#
PCITRDY#
PCISTOP#
PCIIDSEL
PCIREQ#
PCIGNT#
PCICLK
PCIRST#
PCIPAR
PCIINTA#

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
5.2 PCI TIMING SPECIFICATION
The timing specificationof the PCI interface takes the formof generic setup, hold and delay timesof tran-
sitionsto and from the rising edgeof PCICLKas shownin Figure 17.
Figure 17.
PCI timing parameters
Table6.
PCI timing parameters
NOTE PCIREQ# and PCIGNT#are pointto point signals and have different valid delay and input setup times than bussed sig-
nals.All other signals are bussed.
Symbol Parameter Min. Max. Unit Notes

tVAL PCICLKto signal valid delay (bussed signals) 2 11 ns 1
tVAL (PTP) PCICLKto signal valid delay (pointto point) 2 12 ns 1
tON Floatto active delay 2 ns
tOFF Activeto float delay 28 ns
tSU Input setup timeto PCICLK (bussed signals) 7 ns 1
tSU (PTP) Input setup timeto PCICLK (PCIGNT#)10 ns 1
tSU (PTP) Input setup timeto PCICLK (PCIREQ#)12 ns Input hold time from PCICLK 0ns
tVAL
tON
tOFF
tSU tH
PCICLK
Output delay
Tri-state output
Input
PCICLK
Output timing parameters
Input timing parameters
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
Figure 18.
PCI Target write- Slave Write (single 32-bit with 1-cycle DEVSEL# response)
Figure 19.
PCI Target write- Slave Write (multiple 32-bit with zero wait state DEVSEL# response)
address data
bus cmd BE[3:0]#
(med)
PCICLK
PCIAD[31:0]
PCICBE[3:0]#
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIDEVSEL#

address data0
bus cmd BE[3:0]#
data1 data2
BE[3:0]# BE[3:0]#
PCICLK
PCIAD[31:0]
PCICBE[3:0]#
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIDEVSEL#
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Figure 20.
PCI Target read- Slave Read (1-cycle single word read)
Figure 21.
PCI Target read- Slave Read (slow single word read)
address
bus cmd BE[3:0]#
data0
PCICLK
PCIAD[31:0]
PCICBE[3:0]#
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIDEVSEL#

address
bus cmd BE[3:0]#
data0
PCICLK
PCIAD[31:0]
PCICBE[3:0]#
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIDEVSEL#
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
Figure 22.
PCI Master write- multiple word
Figure 23.
PCI Master read- multiple word
Note: The RIVA128ZX doesnot generate fast backto back cyclesasa bus master
bus cmd
data0 data1address data2 data3
BE[3:0]# BE[3:0]# BE[3:0]# BE[3:0]#
PCICLK
PCIREQ#
PCIGNT#
PCIAD[31:0]
PCICBE[3:0]#
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIDEVSEL#

bus cmd
data0address data1
BE[3:0]# BE[3:0]#
PCICLK
PCIREQ#
PCIGNT#
PCIAD[31:0]
PCICBE[3:0]#
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIDEVSEL#
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Figure 24.
PCI Target configuration cycle- Slave Configuration Write
Figure 25.
PCI Target configuration cycle- Slave Configuration Read
bus cmd BE[3:0]#
data0address
(med)
PCICLK
AD[31:0]
PCICBE[3:0]#
PCIFRAME#
PCIIDSEL
PCIIRDY#
PCITRDY#
PCIDEVSEL#

bus cmd BE[3:0]#
config_dataaddressPCIAD[31:0]
PCICBE[3:0]#
PCIFRAME#
PCIIDSEL
PCIIRDY#
PCITRDY#
PCIDEVSEL#
(med)
PCICLK
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
Figure 26.
PCI basic arbitration cycle
Figure 27.
Target initiated termination
address data address data
accessA accessB
PCICLK
PCIREQ#_a
PCIREQ#_b
PCIGNT#_a
PCIGNT#_b
PCIFRAME#
PCIAD[31:0]
3 4123 4 3 412 3 4 5
Disconnect-A Disconnect-B
Disconnect-C/ Retry Target- Abort
PCICLK
PCIFRAME#
PCIIRDY#
PCITRDY#
PCISTOP#
PCIDEVSEL#
PCICLK
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIPCISTOP#
PCIDEVSEL#
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX FRAMEBUFFER INTERFACE
The RIVA128ZX framebuffer interface supports SDRAM and SGRAM memory. Using SDRAMit canbe
configured withan 8MByte 64-bit data bus. With SGRAMit can be configured witha2or 4MByte 64-bit
data busora4or 8MByte 128-bit data bus. The memory configurations supported by RIVA128ZX are
shownin Table7.Allof the framebuffer signalling environmentis 3.3V.
Table7.
RIVA128ZX memory configurations
8Mbit internal bank
SGRAM
16Mbit internal bank
SGRAM
16Mbit internal bank
SGRAM
16Mbitx16
SDRAM
2MByte
2 devices
64-bit
N/A N/A N/A
4MByte
4 devices
128-bit devices
64-bit devices
64-bit
N/A
8MByte
2 banksof4 devices
128-bit devices
128-bit devices
128-bit devices
64-bit
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
6.1 SDRAM INTERFACE
Two extra address lines are requiredto support 8MByte SDRAM compared with those neededfor 4MByte
SGRAM on RIVA 128. These are the A10 signal which was defined on the RIVA 128 pinout for future ex-
pansion and the SDRAM’s internal bank select address bit (BA signal). To provide this extra signal the
RIVA128ZX FBCS[1]# pinis internally redefinedto be the SDRAM BA/A11 signal.
Since the RIVA128ZX supportsa maximum addressable memoryof 8MBytes, SDRAM supportis onlyal-
lowed witha 64-bit data bus. Figure28 showsan example SDRAM memory configuration for RIVA128ZX.
Note this figure attemptsto scramble the bytes and data bits within bytesto simplify board layout, but this
will depend on how the board components are placedin the layout.
Figure 28.
8MByte SDRAM configuration using 16Mbit devices
FBD[127:0]
FBD[7:0]
FBDQM[3]#
FBDQM[0]#
FBDQM[5]#
FBDQM[6]#
FBDQM[1]#
FBDQM[2]#
FBDQM[4]#
FBDQM[7]#
FBCS[0]#
FBCLK1
FBCS[0]#
FBCLK0
FBCS[0]#
FBCLK1
FBCS[0]#
FBCLK0
FBCKE# FBCAS#FBWE#
FBRAS#
FBA[10:0]

1M×16
SDRAM
FBCS[1]#

A[10:0]
RASCAS
CKE
DQML
DQMH
CLK
1M×16
SDRAM
A[10:0]
RASCAS
CKE
DQML
DQMH
CLK
1M×16
SDRAM
A[10:0]
RASCAS
CKE
DQML
DQMH
CLK
1M×16
SDRAM
A[10:0]
RASCAS
CKE
DQML
DQMH
CLK
FBCKE# FBCAS#FBWE# FBRAS#
FBA[10:0]
FBCS[1]#
FBD[31:24]
FBD[23:16]
FBD[15:8]
FBD[55:48]
FBD[47:40]
FBD[56:63]
FBD[32:39]
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
6.2 SGRAM INTERFACE
Signal changes between RIVA 128 and RIVA128ZX

The extra address signal (FBA[10]) requiredto address 16Mbit SGRAM devices was definedon RIVA 128
and was connectedto pin 30of the SGRAMin the RIVA 128 Reference Design schematics. This pinisa
N/C on8Mbit memory devices andit was also N/Con RIVA 128. For 8MByte designs using 8Mbit devices;
FBCS0#
drives the chip selects for the first external bankof memory and FBCS1# drives the second ex-
ternal bank.
The ROM BIOS implements code which automatically detects the configuration and memory type.Ifa mix-
tureof 4-internal bank and 2-internal bank 16Mbit devices are used (e.g.2 soldered down and2 addedby end userasan SO-DIMM) then RIVA128ZX will program those devices and operate itselfas 2-internal
bank. Thereisno supportfor mixed 16Mbit and 8Mbit memories (i.e. thereisno 6MByte mode) noris there
support for 16MByte using eight 16Mbit devices. The upgrade path from two devicesto four devices has
also been changedto better accommodate board layout for SO-DIMMs.As shownin Figure 29, the first
two memories installed are on the left sideof the chip and the upgradeis on the right hand side. Thisis
differentto RIVA 128 which populated the top two chips first and then populated the lower (far left and far
right) memoriesas the upgrade. Both formsof 64-bit bus are supportedin RIVA128ZX and the data paths
populated are determinedby the BIOS duringits boot memory detection sequence.
Figure 29.
Upgrade from 64-bit 4MByteto 128-bit 8MByte SGRAM via SO-DIMM
RIVA128ZX
FBD[31:0]
FBD[95:64]

Bank2
512K
x32
FBD[63:32]
FBD[127:96]

Upgradeto
8MBytevia
SO-DIMM
First two
memories
installed
Bank0
512K
x32
Bank1
512K
x32
Bank3
512K
x32
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
Figure 30.
4 MByte SGRAM configurations using 16Mbit devices
NOTE The 64-bit bus data paths populatedby RIVA128ZXare determinedby the BIOS duringits boot memory detectionse-
quence.
FBD[127:0]
FBDQM[0]#
FBDQM[1]#
FBD[31:0] FBD[95:64]FBDQM[2]#
FBDQM[3]#
FBDQM[8]#
FBDQM[9]#
FBDQM[10]#
FBDQM[11]#
FBCS[0]#
FBCLK0
FBCS[1]#
FBCLK0
FBCKE# FBCAS#FBWE# FBRAS#FBA[10:0]
Compatible with RIVA128ZX layout
implementing SO-DIMM upgradeto 8Mbytes
FBD[127:0]
FBDQM[0]#
FBDQM[1]#

Bank0
512K×32
SGRAM
FBD[31:0] FBD[63:32]FBDQM[2]#
FBDQM[3]#
FBDQM[4]#
FBDQM[5]#
FBDQM[6]#
FBDQM[7]#
FBCS[0]#
FBCLK0
FBCS[0]#
FBCLK1
FBCKE# FBCAS#FBWE#
FBRAS#
FBA[10:0]
RIVA 128 layout compatible
Bank1
512K×32
SGRAM
Bank0
512K×32
SGRAM
Bank2
512K×32
SGRAM
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Figure 31.
8MByte SGRAM configuration using 16Mbit devices
FBD[63:32]
FBD[127:0]
FBDQM[0]#
FBDQM[1]#
FBD[31:0] FBD[95:64]FBDQM[2]#
FBDQM[3]#
FBDQM[4]#
FBDQM[5]#
FBDQM[6]#
FBDQM[7]#
FBDQM[8]#
FBDQM[9]#
FBDQM[10]#
FBDQM[11]#
FBDQM[12]#
FBDQM[13]#
FBDQM[14]#
FBDQM[15]#
FBD[127:96]
FBCS[0]#
FBCLK1
FBCS[0]#
FBCLK0
FBCS[1]#
FBCLK1
FBCS[1]#
FBCLK0
FBCKE# FBCAS#FBWE#
FBRAS#
FBA[10:0]
FBCKE# FBCAS#
FBWE#
FBRAS#
FBA[10:0]

Bank0
512K×32
SGRAM
Bank2
512K×32
SGRAM
Bank1
512K×32
SGRAM
Bank3
512K×32
SGRAM
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
6.3 SDRAM/SGRAM ACCESSES AND COMMANDS
Read and write accessesto SDRAM/SGRAM are burst oriented. SDRAM/SGRAM commands supported the RIVA128ZX are shownin Table9. Initializationof the memory devicesis performedin the standard
SDRAM/SGRAM manner. Access sequences begin withan Active command followedbya Reador Write
command. The address bits registered coincident with the Reador Write command are usedto select the
starting column location for the burst access. The RIVA128ZX always usesa burst lengthof one and can
launcha new reador write on every cycle.
SDRAM/SGRAM hasa fully synchronous interface withall signals registered on the positive edgeof FB-
CLKx.
Multiple clock outputs allow reductionsin signal loading and more accuracyin data samplingat
high frequency. The clock signals canbe interspersedas shownin Figure 30, page33 for optimal loading
with either4or 8MBytes. The I/O timings relativeto FBCLKx are shownin Figure 32, page 37.
Table8.
Truth tableof supported SDRAM commands
NOTES FBCKEis high and DSFis lowforall supported commands. Activatesor deactivates FBD[63:0] during writes (zero clock delay) and reads (two-clock delay). For FBA10 low, FBCS[1]# determines which bankis precharged;for FBA10 high,all banksare precharged irrespectivethe stateof FBCS[1]#.
Command1 FBCS0# FBRAS# FBCAS# FBWE# FBDQM FBCS[1]#,
FBA[10:0]
FBD[63:0] Notes
Command inhibit
(NOP) H x x x x x x operation (NOP) L H H H x x x
Active
(select bank and
activate row) H H x FBCS[1]#=bank
FBA[10:0]=row

Read
(select bank and
column and start read
burst) LH x FBCS[1]#=bank
FBA[10]=0
FBA[7:0]=col

Write
(select bank and
column and start write
burst) L L x FBCS[1]#=bank
FBA[10]=0
FBA[7:0]=col

valid data
Precharge
(deactivate
rowin bankor banks) H L x FBA[10]=code x 3
Load mode register
LLLL x FBCS[1]#,
FBA[10:0]=

opcode
Write enable/output
enable
- - - L - active 2
Write inhibit/output
High-Z
- - - H - high-Z 2
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Table9.
Truth tableof supported SGRAM commands
NOTES FBCKEis high and DSFis lowforall supported commands. Activatesor deactivates FBD[127:0] during writes (zero clock delay) and reads (two-clock delay). For FBA9 low, FBA10 determines which bankis precharged;for FBA9 high, allbanksare precharged irrespectiveofthe
stateof FBA10.
SDRAM/SGRAM Initialization

SDRAM/SGRAMs mustbe powered-up and initializedina predefined manner. The first SDRAM/SGRAM
commandis registered on the first clock edge following PCIRST# inactive.
All internal SDRAM/SGRAM banks are prechargedto bring the device(s) into the “all bank idle” state. The
SDRAM/SGRAM mode registers are then programmed and loadedto bring them intoa defined state be-
fore performing any operational command.
SDRAM/SGRAM Mode register

The Mode register defines the modeof operation ofthe SDRAM/SGRAM. This includes burst length, burst
type, read latency and SDRAM/SGRAM operating mode. The Mode registeris programmed via the Load
Mode register and retainsits state until reprogrammedor power-down.
Mode registerbits M[2:0] specifythe burst length;for the RIVA128ZX SDRAM/SGRAM interface these bits
are setto zero, selectinga burst lengthof one.In this case FBA[7:0] select the unique columntobe ac-
cessed and Mode registerbit M[3]is ignored. Mode register bits M[6:4] specify the read latency; for the
RIVA128ZX SDRAM/SGRAM interface these bits are setto either2or3, selectinga burst lengthof2or respectively.
Command1 FBCS0#,
FBCS1#
FBRAS# FBCAS# FBWE# FBDQM FBA[10:0] FBD[127:0] Notes
Command inhibit
(NOP) H x x x x x x operation (NOP) L H H H x x x
Active
(select bank and
activate row) H H x FBA[10]=bank
FBA[9:0]=row

Read
(select bank and
column and start read
burst) L H x FBA[10]=bank
FBA[9]=0
FBA[7:0]=col

Write
(select bank and
column and start write
burst) H LLx FBA[10]=bank
FBA[9]=0
FBA[7:0]=col

valid data
Precharge
(deactivate
rowin bankor banks) H L x FBA[10]=code x 3
Load mode register
L LLLx FBA[10:0]=
opcode
Write enable/output
enable
- - - L - active 2
Write inhibit/output
High-Z
- - - H - high-Z 2
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
6.4 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS
Separate clock signals FBCLK0 and FBCLK1 are provided for each bankof memoryto give reduced
clock skew and loading. Additionally thereisa clock feedback loop between FBCLK2 and FBCLKFB.is recommended that long traces are used without tunable components.If the layout includes provision
for expansionto 8MBytes, the clock pathto the 4MByte parts should beat the endof the trace, and the
clock pathto the 8MByte expansion located between the RIVA128ZX and the 4MByte partsas shownin
Figure 32. FBCLK2 and FBCLKFB shouldbe shorted togetheras closeto the packageas possible.
Figure 32.
Recommended memory clock layout
6.5 FRAMEBUFFER INTERFACE TIMING SPECIFICATION
Figure 33.
SDRAM/SGRAM I/O timing diagram
Table 10.
SDRAM/SGRAM I/O timing parameters
Symbol Parameter Min. Max. Unit Notes
-10 -12 -10 -12

tCK CLK period 10 12 - - ns
tCH CLK high time 3.5 4.5 - - ns
tCL CLK low time 3.5 4.5 - - ns
tAS Address setup time 3 4 - ns
tAH Address hold time 1 1 - ns
tDS Write data setup time 3 4 - ns
RIVA128ZX 512K
x32
512K
x32
512K
x32
512K
x32
Bank1 Bank0
Expansion 8MBytes
FBCLK0
FBCLK1

FBCLK2
FBCLKFB

tCH
tCK
tCL
tAS,tDS
tAH,tDH
tLZ
tAC
tOH
FBCLKx
FBA[10:0], FBD[63:0]
FBD[63:0]
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Figure 34.
SDRAM/SGRAM random read accesses withina page, read latencyof two1
NOTE Covers either successive readstothe active rowina given bank,ortothe active rowsin different banks. DQMsareall
active (LOW).
Figure 35.
SDRAM/SGRAM random read accesses withina page, read latencyof three1
NOTE Covers either successive readstothe active rowina given bank,ortothe active rowsin different banks. FBDQMisall
active (LOW).
Figure 36.
SDRAM/SGRAM readto write, read latencyof three
tDH Write data hold time 1 1 - ns
tOH Read data hold time 3 3 - ns
tAC Read data access time 9 9 - ns
tLZ Data out low impedance time 0 0 - ns
Symbol Parameter Min. Max. Unit Notes
-10 -12 -10 -12

read read read
datan dataa
read nop nop
bank, coln bank,cola bank, colx bank,colm
datax datam
FBCLKx
Command
FBA[10:0]
FBD[63:0]

read read read
datan
read nop nop
bank,coln bank,cola bank,colx bank,colm
dataa datax datam
nop
FBCLKx
Command
FBA[10:0]
FBD[63:0]

tHZ tDS
read nop nop
read datan
nop write
bank, coln
write datab
bank, colb
FBCLKx
TDDQM
Command
FBA[10:0]
FBD[63:0]
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
Table 11.
SDRAM/SGRAM I/O timing parameters
Figure 37.
SDRAM/SGRAM random write cycles withina page
NOTE Covers either successivewritestothe active rowina given bankorto theactive rowsin different banks. FBDQMis active
(low).
Figure 38.
SDRAM/SGRAM writeto read cycle
NOTEA read latencyof2is shownfor illustration
Figure 39.
SDRAM/SGRAM readto precharge, read latencyof two
NOTE FBDQMis active (low)
Symbol Parameter Min. Max. Unit Notes

tHZ Data out high impedance time 4 10 ns
tDS Write data setup time 4 ns
write write write write
datan dataa datax datam
bank, coln bank,cola bank,colx bank, colm
FBCLKx
Command
FBA[10:0]
FBD[63:0]

write nop read nop nop nop
bank,
coln
bank,
colb
write
datan
write
datan
read
datab
FBCLKx
Command
FBA[10:0]
FBD[63:0]

nop active
bank(s) bank,row
datan
tRP
read precharge nop
bank,coln
FBCLKx
Command
FBA[10:0]
FBD[63:0]
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX
Figure 40.
SDRAM/SGRAM readto precharge, read latencyof three
NOTE FBDQMis active (low)
Figure 41.
SDRAM/SGRAM Writeto Precharge
Figure 42.
SDRAM/SGRAM Activeto Reador Write
Table 12.
SDRAM/SGRAM timing parameters
Symbol Parameter Min. Max. Unit Notes

tCS FBCSx, FBRAS#, FBCAS#, FBWE#,
FBDQM
setup time
3ns
tCH FBCSx, FBRAS#, FBCAS#, FBWE#,
FBDQM
hold time
1ns
tMTC Load Mode register commandto command 2 tCK
tRAS Activeto Precharge command period 7 tCK
tRC Activeto Active command period 10 tCK
tRCD Activeto Reador Write delay 3 tCK
precharge nop nop active
bank(s) bank,
datan
tRP
read
bank,
FBCLKx
Command
FBA[10:0]
FBD[63:0]

coln row
write nop nop precharge nop nop active
bank(s) row
tRP
tWR
bank, coln
write datan write data
n+1
FBCLKx
FBDQM#
Command
FBA[10:0]
FBD[63:0]

active nop nop
tRCD
reador write
FBCLKx

Command
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
tREF Refresh period (1024 cycles) 16 ms
tRP Precharge command period 4 tCK
tRRD Active bankAto Active bankB command
period
3tCK Transition time 1 ns
tWR Write recovery time 2 tCK
Symbol Parameter Min. Max. Unit Notes
128-BIT 3D MULTIMEDIA ACCELERATORRIVA128ZX VIDEO PLAYBACK ARCHITECTURE
The RIVA128ZX video playback architectureis
designedto allow playbackof CCIR PALor NTSC
video formats with the highest quality while requir-
ing the smallest video surface. The implementa-
tionis optimized around the Windows 95 Direct
Video and ActiveX APIs, and supports the follow-
ing features: Accepts interlaced video fields: This allows the off-screen video surfaceto
consume less memory since only one field
(halfof each frame)is stored. Double buffer-
ing between fieldsis donein hardware with
‘temporal averaging’ being applied basedon
intraframing. Linestore: To support high quality video playback the
RIVA128ZX memory controller and video
overlay engine supports horizontal and verti-
cal interpolation usinga 3x2 multitap interpo-
lating filter with image sharpening. YUVto RGB conversion: YUV 4:2:2 formatto 24-bit RGB true-color Chrominance optimization/user control Color key video composition
Figure 43.
Video scaler pipeline
YUV
Vertical
Interpolation
Filter
(Smooth/Sharpen)
Color Space
Conversionto 24-bit
RGB
Horizontal
Interpolation
24-bit RGB
Video output
Video windowing, merge
with graphics pixel pipeline
Linestore
128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX
7.1 VIDEO SCALER PIPELINE
The RIVA128ZX video scaler pipeline performs
stretchingof video imagesin any arbitrary factorin
both horizontal and vertical directions. The video
scaler pipeline consistsof the following stages: Vertical stretching Filtering Color space conversion Horizontal stretching
Vertical stretching

Vertical stretchingis performed on pixels priorto
color conversion. The video scaler linearly interpo-
lates the pixelsin the vertical direction usinganin-
ternal buffer which stores the previous lineof pixel
information.
Filtering

After vertical interpolation, the pixels are horizon-
tally filtered using an edge-enhancement ora
smoothing filter. The edge-enhancement filter en-
hances picture transition informationto prevent
lossof image clarity following the smoothing filter-
ing stage. The smoothing filterisa low-pass filter
that reduces the noisein the source image.
Color space conversion

The video overlay pipeline logic converts images
from YUV 4:2:2 formatto 24-bit RGB true-color.
The default color conversion coefficients convert
from YCrCbto gamma corrected RGB.
Saturation controls make sure that the conversion
does not exceed the output range. Four control
flagsin the color converter provides16 setsof col- conversion coefficientsto allow adjustmentof
the hue and saturation. The brightnessof eachGB component can also be individually adjust-
ed, similarto the brightness controlsof the moni-
tor.
Horizontal stretching

Horizontal stretchingis donein 24-bit RGB space
after color conversion. Each componentis linearly
interpolated usinga triangle 2-tap filter.
Windowing and panning

Video images are clippedtoa rectangular windowa pairof registers specifying the position and
width. programming the video start address and the
video pitch, the video overlay logic also supportsa
panning windowthat can zoom intoa portionof the
source image.
Video composition

With the color keying feature enabled,a program-
mable keyin the graphics pixel stream allows se-
lectionof either the videoor the graphics outputon pixelby pixel basis. Color keying allows any ar-
bitrary portionsof the videoto overlay the graph-
ics.
With color keying disabled and video overlay
turned on, the video output overlays the graphics the video window.
Interlaced video

The video overlay can display both non-interlaced
and interlaced video.
Traditional video overlay hardware typically drops
every other fieldof an interlaced video stream,
resultingina low frame rate. Some solutions have
attemptedto overcome the this problem by de-
interlacing the fields intoa single frame. This
however introduces motion artifacts. Fast moving
objects appearingin different positionsin different
fields, when deinterlaced, introduces visible
artifacts which look like hair-like lines projecting
outof the object.
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