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OP282GP-OP282GS-OP482GP-OP482GS
Dual/Quad Low Power, High Speed JFET Operational Amplifiers
REV.BDual/Quad Low Power, High Speed
JFET Operational Amplifiers
GENERAL DESCRIPTION

The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. Slew rate
exceeds 7 V/μs with supply current under 250 μA per amplifier.
These unity gain stable amplifiers have a typical gain bandwidth
of 4 MHz.
The JFET input stage of the OP282/OP482 insures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 volts of each supply, low
power consumption and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power restricted applica-
tions. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for high-
side signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. Both dual and quad amplifiers are available
in plastic and ceramic DIP plus SOIC surface mount packages.
FEATURES
High Slew Rate: 9 V/ms
Wide Bandwidth: 4 MHz
Low Supply Current: 250 mA/Amplifier
Low Offset Voltage: 3 mV
Low Bias Current: 100 pA
Fast Settling Time
Common-Mode Range Includes V+
Unity Gain Stable
APPLICATIONS
Active Filters
Fast Amplifiers
Integrators
Supply Current Monitoring
PIN CONNECTIONS
8-Lead Narrow-Body SOIC8-Lead Epoxy DIP
(S Suffix)(P Suffix)OUT A
–IN A
+IN A
OUT B
–IN B
+IN B
OUT A
–IN A
+IN A
OUT B
–IN B
+IN B
14-Lead Epoxy DIP14-Lead Narrow-Body SOIC
(P Suffix)(S Suffix)
OP282/OP482–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 615.0 V, TA = +258C unless otherwise noted)

NOTEThe input bias and offset currents are tested at TA = TJ = +85°C. Bias and offset currents are guaranteed but not tested at –40°C.
Specifications subject to change without notice.
WAFER TEST LIMITS (@ VS = 615.0 V, TA = +258C unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . .36 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . .Indefinite
Storage Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Operating Temperature Range
OP282A, OP482A . . . . . . . . . . . . . . . . . .–55°C to +125°C
OP282G, OP482G . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Junction Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Lead Temperature Range (Soldering, 60 sec) . . . . . .+300°C
NOTES
1For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for cerdip, P-DIP; θJA is specified for device soldered in circuit board for
SOIC package.
ORDERING GUIDE

OP282GS
OP482GP
DICE CHARACTERISTICS

OP282 Die Size 0.063 3 0.060 Inch, 3,780 Sq. Mils
OP482 Die Size 0.070 3 0.098 Inch, 6,860 Sq. Mils
OP282/OP482
APPLICATIONS INFORMATION

The OP282 and OP482 are single and dual JFET op amps that
have been optimized for high speed at low power. This
combination makes these amplifiers excellent choices for battery
powered or low power applications requiring above average
performance. Applications benefiting from this performance
combination include telecom, geophysical exploration, portable
medical equipment and navigational instrumentation.
HIGH SIDE SIGNAL CONDITIONING

There are many applications that require the sensing of signals
near the positive rail. OP282s and OP482s have been tested and
guaranteed over a common-mode range (–11 V ≤ VCM ≤ +15 V)
that includes the positive supply.
One application where this is commonly used is in the sensing of
power supply currents. This enables it to be used in current
sensing applications such as the partial circuit shown in Figure
1. In this circuit, the voltage drop across a low value resistor,
such as the 0.1 Ω shown here, is amplified and compared to 7.5
volts. The output can then be used for current limiting.
+15V
100k
100k
0.1L

Figure 1.Phase Inversion
PHASE INVERSION

Most JFET-input amplifiers will invert the phase of the input
signal if either input exceeds the input common-mode range.
For the OP282 and OP482 negative signals in excess of approxi-
mately 14 volts will cause phase inversion. The cause of this
effect is saturation of the input stage leading to the forward-
biasing of a drain-gate diode. A simple fix for this in noninverting
applications is to place a resistor in series with the noninverting
input. This limits the amount of current through the forward-
biased diode and prevents the shutting down of the output
stage. For the OP282/OP482, a value of 200 kΩ has been found
to work. However, this adds a significant amount of noise.
OUTV

Figure 2.OP282 Phase Reversal
ACTIVE FILTERS

The OP282 and OP482’s wide bandwidth and high slew rates
make either an excellent choice for many filter applications.
There are many types of active filter configurations, but the four
most popular configurations are Butterworth, elliptical, Bessel,
and Chebyshev. Each type has a response that is optimized for a
given characteristic as shown in Table I.
PROGRAMMABLE STATE-VARIABLE FILTER
Table I.
The circuit shown in Figure 3 can be used to accurately
program the “Q,” the cutoff frequency fC, and the gain of a two
pole state-variable filter. OP482s have been used in this design
because of their high bandwidths, low power and low noise.
This circuit takes only three packages to build because of the
quad configuration of the op amps and DACs.
The DACs shown are all used in the voltage mode so all values
are dependent only on the accuracy of the DAC and not on the
absolute values of the DAC’s resistive ladders. This make this
circuit unusually accurate for a programmable filter.
Adjusting DAC 1 changes the signal amplitude across R1;
therefore, the DAC attenuation times R1 determines the
amount of signal current that charges the integrating capacitor,
C1. This cutoff frequency can now be expressed as: =1
2πR1C1
256
where D1 is the digital code for the DAC.
Gain of this circuit is set by adjusting D3. The gain equation is:
Gain=R4
256
DAC 2 is used to set the “Q” of the circuit. Adjusting this DAC
controls the amount of feedback from the bandpass node to the
input summing node. Note that the digital value of the DAC is
in the numerator, therefore zero code is not a valid operating point. =R2
256
Figure 3.
OP282/OP482
OP282/OP482 SPICE MACRO MODEL

Figure 4 shows the OP282 SPICE macro model. The model for
the OP482 is similar to that of the OP282, but there are some
minor changes in the circuit values. Contact ADI for a copy of
the latest SPICE model diskette for both listings.
IN-
IN+
IOSR4G1
EREF19
C14
R27
R2830
VOUT

Figure 4.
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