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OMAPL137BZKB3TIN/a360avaiC6000 DSP+ARM Processor 256-BGA 0 to 90


OMAPL137BZKB3 ,C6000 DSP+ARM Processor 256-BGA 0 to 90 SPRS563G–SEPTEMBER 2008–REVISED JUNE 2014The ARM core has a coprocessor 15 (CP15), protection modu ..
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OMAPL137BZKB3
C6000 DSP+ARM Processor
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SPRS563G–SEPTEMBER 2008–REVISED JUNE 2014
OMAP-L137 Low-Power Applications Processor OMAP-L137 Low-Power Applications Processor
1.1 Features
Supportsupto Four SP Additions Per Clock,• Software Support Four DP Additions Every2 Clocks– TI DSP/BIOS™ • Supportsupto Two Floating-Point (SPor– Chip Support Library and DSP Library DP) Reciprocal Approximation (RCPxP) and• Dual Core SoC Square-Root Reciprocal Approximation– 375- and 456-MHz ARM926EJ-S™ RISC MPU (RSQRxP) Operations Per Cycle– 375- and 456-MHz C674x VLIW DSP – Two Multiply Functional Units• ARM926EJ-S Core • Mixed-Precision IEEE Floating Point Multiply– 32-Bit and 16-Bit (Thumb®) Instructions Supported upto: DSP Instruction Extensions – 2 SPx SP-> SP Per Clock Single Cycle MAC – 2 SPx SP-> DP Every Two Clocks ARM® Jazelle® Technology – 2 SPx DP-> DP Every Three Clocks Embedded ICE-RT™ for Real-Time Debug – 2 DPx DP-> DP Every Four Clocks• ARM9™ Memory Architecture • Fixed-Point Multiply Supports Two32x 32- 16KBof Instruction Cache Bit Multiplies, Four16x 16-Bit Multiplies,or
Eight8x 8-Bit Multiplies per Clock Cycle,– 16KBof Data Cache
and Complex Multiples– 8KBof RAM (Vector Table) Instruction Packing Reduces Code Size– 64KBof ROM All Instructions Conditional• C674x Instruction Set Features Hardware Supportfor Modulo Loop– Supersetof the C67x+ and C64x+ ISAs
Operation– Upto 3648 MIPS and 2736 MFLOPS C674x – Protected Mode Operation– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – Exceptions Support for Error Detection and– 8-Bit Overflow Protection Program Redirection– Bit-Field Extract, Set, Clear • 128KBof RAM Shared Memory– Normalization, Saturation, Bit-Counting • 3.3-V LVCMOS I/Os (Exceptfor USB Interfaces)– Compact 16-Bit Instructions • Two External Memory Interfaces:• C674x Two-Level Cache Memory Architecture – EMIFA– 32KBof L1P Program RAM/Cache • NOR (8-or 16-Bit-Wide Data)– 32KBof L1D Data RAM/Cache • NAND (8-or 16-Bit-Wide Data)– 256KBofL2 Unified Mapped RAM/Cache • 16-Bit SDRAM with 128-MB Address Space– Flexible RAM/Cache Partition (L1 and L2) – EMIFB• Enhanced Direct Memory Access Controller3 • 32-Bitor 16-Bit SDRAM with 256-MB Address Space • Three Configurable 16550-Type UART Modules: Channels – UART0 with Modem Control Signals Channels – Autoflow Control Signals (CTS, RTS)on UART0 Size Only VLIW 16xor •
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