NMC27C32BQE250 ,250 ns, Vcc=5V+/-10%, 32,768-bit (4k x 8) high speed version UV erasable CMOS PROMBlock Diagram _
DATA OUTPUTS h-ih
lltm o-- e----'------,
tmo H
Ile _
Pin Names
Chip ..
NMC27C512AQ15 ,150 ns, Vcc=5V+/-5%, 524,288-bit (64k x 8) UV erasable CMOS PROMFeatures
I Ciocked sense amps for fast access time down to
150 ns
I Low CMOS power consumpti ..
NMC27C512AQ150 ,150 ns, Vcc=5V+/-10%, 524,288-bit (64k x 8) UV erasable CMOS PROMNational
Semiconductor
NMC27C512A
PRELIMINARY
524,288-Bit (64k x 8) UV Erasable CMOS PROM ..
NMC27C512AQ-150 ,150 ns, Vcc=5V+/-10%, 524,288-bit (64k x 8) UV erasable CMOS PROMElectrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
IL. Input Load Current F ..
NMC27C512AQ170 ,170 ns, Vcc=5V+/-10%, 524,288-bit (64k x 8) UV erasable CMOS PROMapplications where fast turnaround, pattern experiments
tion and low power consumption are importa ..
NMC27C512AQ-170 ,170 ns, Vcc=5V+/-10%, 524,288-bit (64k x 8) UV erasable CMOS PROMElectrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
IL. Input Load Current F ..
OM4068H ,LCD driver for low multiplex ratesGENERAL DESCRIPTION1⁄3The OM4068 is a low-power CMOS LCD driver, designed• 32 segment driversto dri ..
OM4068H/2 ,OM4068; LCD driver for low multiplex rates
OM4085T/F1 ,OM4085; Universal LCD driver for low multiplex rates
OM5193H ,Disk drive spindle and VCM with servo controller
OM5202FBB ,ROMless 8-bit microcontroller
OM5604 ,Multimedia radio tuner
NMC27C32BQE250
250 ns, Vcc=5V+/-10%, 32,768-bit (4k x 8) high speed version UV erasable CMOS PROM
National
Semiconductor
PRELIMINARY
NMC27C32B 32,768-Bit (4k It 8)
High Speed Version UV Erasable CMOS PROM
General Description
The NMC27C32B is a high-speed 32k UV erasable and
electrically reprogrammable CMOS EPROM, ideally suited
for applications where fast turnaround, pattern experiments
tion and low power consumption are important require-
ments.
The NMC27C32B is designed to operate with a single + 5V
power supply with i 10% tolerance. The CMOS design al-
lows the part to operate over the Extended Temperature
Range.
The NMC27C32B is packaged in a 24-pin dual-in-line pack-
age with transparent lid. The transparent iid allows the user
to expose the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written electrically into the device
by following the programming procedure.
This EPROM is fabricated with National's proprietary, time
proven CMOS double-poly silicon gate technology which
combines high performance and high density with low pow-
er consumption and excellent reliability.
Features
II Clocked sense amps for fast access time down to
150 ns
" Low CMOS power consumption
- Active Power
- Standby Power
1: Optimal EPROM for total CMOS systems
Single 5V power supply
Extended temperature range (NMC27C32BOE), -40''C
to +85''C, available
II Pin compatible with NMOS 32k EPROMs
a Fast and reliable programming-loo p.s typical/byte
II Static operation-mo clocks required
55 mW Max
0.55 mW Max
TTL, CMOS compatible inputs/outputs
TRI-STATiYr output
I: Manufacturer's identification code for automatic pro-
gramming control
I: High current CMOS level output drivers
Block Diagram
om OUTPUTS th-o,
Vcc o---
Glt0 Pin Names
V» o---
AO-All Addresses
output ENABLE - .
Ann cm cum" CE Chip Enable
mm mm MJFFERS O-E/imp Output Enable/
Programming
Voltage
0333053 t wins 00-07 Outputs
AO-M 1
ADDRESS
INPUI'S
DECODER
32.768 BIT
CELL MATRIX
TL/D/8827-1
GZSOLZOWN
NMC27C3ZB
Connection Diagram
270256 270128 27064 27016 270 16 27C64 270128 276256
27256 27128 2764 2716 2716 2764 27128 27256
VPP VPP VPP m,ah'Ji'2'j,'e,U, E -'.l.tE Vcc
A12 A12 A12 PGM PGM A14
A7 A7 A7 A7 A7 -1 1 U 24 -a Vcc NC A13 A13
A6 A6 A6 A6 A6 - 2 23 -" M A8 A8 A8
A5 A5 A5 A5 A5 - 3 22 .-.h9 A9 A9 A9 A9
A4 A4 A4 A4 A4- 4 21 -htl Vpp A11 A11 A11
A3 A3 A3 A3 A3 - 5 20 -rsl hre E Ul? UE UE
A2 A2 A2 A2 A2- 6 19 -hlo A10 A10 A10 A10
A1 A1 A1 A1 A1 - 7 18 -cR E E E CE
A0 A0 A0 A0 A0 - 8 17 - 07 O7 O7 O7 O7
00 00 00 00 00 ' 9 16 - 06 06 Os th 06
O1 o, O1 o, th- 10 15 -05 O5 Os Os Os
02 02 O2 02 02 - 11 14 - O4 O4 04 O4 04
GND GND GND GND tmo- 12 13 -os Os Os Os ck
TL/D/8827-2
Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C32B pins.
Order Number NMC27C32BQ
See NS Package Number J24AQ
Commercial Temp Range (0°C to + 70''C) Vcc = 5V i5%
Parameter/Order Number Access Time ins)
NMC27C32BQ15 150
Commercial Temp Range (0°C to +70'C) Vcc = 5V i: 10%
Parameter/Order Number Access Tlme (ns)
NMC27C32BQ150 150
NMC27C32BO200 200
NMC27C32BO250 250
Extended Temp Range (-4tt'C to + 85''C) Vcc = 5V i 10%
Parameter/Order Number Access Time (ns)
NMG27C32BQE200 200
NMC27C32BOE250 250
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
COMMERCIAL TEMPERATURE RANGE
Absolute Maximum Ratings (Note1)
E Vpp Supply and A9 Voltage with
Respect to Ground
+ 14.0V to --0.6V
Oftltte/Dltgtrlbutortt for avallabllity and speclflcatlons. Power Dissipation 1.0W
Temperature Under Bias - 10''C to + 80°C Lead Temperature (Soldering, 10 sec.) 300°C
Extended Temp Parts Operating Temp ESD Rating
Storage Temperature - 65'C to + 150°C (Mil Spec 8830, Method 3015.2) 2000V
Vcc Supply Voltage with
Respect to Ground + 7.0V to -0.6V Operating Conditions (Note 6)
All Inpgt_Voltages except A9 Temperature Range
and OE/Vpp with NMC27C32BO150, 200, 250 0''C to + 70°C
Respect to Ground (Note 9) + 6.5V to - 0.6V NMC27C32BQE200, 250 -40oC to + 85°C
All Output Voltages with Vcc Power Supply + 5V ct: 10%
Respect to Ground (Note 9) Vcc+ 1.0V to GND - 0.6V except NMC27C32BQ15 + 5V f.: 5%
READ OPERATION
DC Electrical Characteristics
Symbol Parameter Condltlons Min Typ Max Unlts
IL. Input Load Current VIN = Vcc or GND 0.01 1 M
[pp Coil/vm, Load Current UE/i/pt, = Vcc or GND 10 FA
lLo Output Leakage Current VOUT = Vcc or GNDE == VIH 0.01 1 WA
Icc1 Vcc Current (Active) 3 = Nhof = 1 MHz 8 20 m A
TTL Inputs Inputs = VIH orVIL. I/O T.'.'.: 0 mA
lccg Vcc Current (Active) tTE = GND,f = 1 MHz 3 10 . _ m A
CMOS Inputs Inputs = Vcc or GND, I/O = 0 mA
'CCSB1 Vcc Current (Standby) CE = Vm 0.1 1 m A
TTL Inputs
ICCSBZ I/gg/r,',';),,"'"'') CE Vcc 0.5 10 0 M A
VIL Input Low Voltage -0.2 0.8 V
VIH Input High Voltage 2.0 Voc + 1 V
VOL1 OutputLow Voltage loc = 2.1 mA 0.45 V
VOH1 Output High Voltage lor, = -400 pA 2.4 V
V0.2 Output Low Voltage IOL = 10 WA 0.1 V
VOH2 Output High Voltage IOH = -10 p.A Vcc - 0.1 V
AC Electrical Characteristics
NM627032B
Symbol Parameter Conditions 015, 0150 0200, 05200 0250, 0E250 Unlts
Mln Max Mln Max Min Max
tAcc Address to Output Delay E = E = " 150 200 250 ns
tCE Uit-to Output Delay CE == " 150 200 250 ns
log 6Eto Output Delay CE = " 60 60 70 ns
tDF UE High to Output Float E = Vu. o 50 o 60 60 ns
tCF Cl? High to Output Float bi = " 50 0 so 60 ns
10H gtputliold from Addresses, tX = tTE = "
CE or OE, Whichever 0 0 ns
Occurred First
GZSOLZOWN
NMC27C3ZB
Capacitance TA = +25'C,t = 1 MHz (Note2)
Symbol Parameter Condltlons Typ Max Units
Clm lnputCapacitance exceptGE/Vpp VIN = 0V 6 8 pF
thte ty-E/vm, InputCapacitance VIN = 0V 25 28 pF
COUT Output Capacitance VOUT = 0V 9 12 pF
AC Test Conditions
Output Load 1 TTL Gate and Timing Measurement Reference Level
Ct. = 100 pF (Note 8) Inputs 0.8V and 2V
Input Rise and Fall Times 35 ns Outputs 0.8V and 2V
Input Pulse Levels 0.45V to 2.4V
AC Waveforms (Note 7)
ADDRESSES 2.tN ADDRESSES VALID l'
cs g.gv N rr y'
J' - ---
tc: (nom4.5)
amp? tg lt ",', ot
toe tar -
"I (NOTES) ' *(uovzs¢,s)
2.0V Hi-Z y, "" Hi-Z
ourPur 3331- VALID OUTPUT rr Ill]
- tacc ''
(nous) ' --Aml
TL/D/8827-3
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating'o'nly and functional
operation of the device at these or any other Conditions above those indicated in the operational sections of this trpetymation is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3.. UE may be delayed up to two - 105 after the falling edge ott5E without impacting tAcc.
Note 4: The top and to; compare level is determined as follows:
High to TH|-STATE. the measured Vom (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) ' 0.10V.
Note s: TRI-STATE may be attained using E or E.
Note tk The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 pF ceramic capacitor be used on
every device between Vcc and GND.
Note P. The outputs must be mstricted to Vcc + 1.0V to avoid latch-up and device damage.
Note 3: 1 TTL Gate: kx = 1.6 mA, lon = -400 WA.
CL: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max, except for o-E/vs,,, which cannot exceed -0.2V.
Programming Characteristics (Notes1. 2, a a 4)
Symbol Parameter Condltlons Min Typ Max Units
us Address Setup Time 1 'M'
toes UE Setup Time 1 ps
tDS Data Setup Time 1 p.S
tvcs Vcc Setup Time 1 HS
tAH Address Hold Time 0 p.s
tDH Data Hold Time 1 p.s
top Chip Enable to Output Float Delay UE = " 0 60 ns
tpw Program Pulse Width 95 100 105 ps
(OEH -0t? Hold Time 1 ns
toy Data Valid from CE CE = " 250 ns
1pm UE .Pulse Rise Tirhe 50 ns
During Programming
tVR Vpp Recovery Time 1 p5
lpp Vpp Supply Current During CE = VIL, 30 m A
Programming Pulse E = Vpp
ICC VCC Supply Current 10 mA
TA Temperature Ambient 20 25 30 "C
Vcc Power Supply Voltage 6.0 6.25 6.5 V
Vpp Programming Supply Voltage 12.5 12.75 13.0 V
tFR Input Rise, Fall Time 5 ns
" Input Low Voltage 0.0 0.45 V
Vm Input High Voltage 2.4 4.0 .. ‘V
th Input Timing Reference Voltage 0.8 1.5 2.0 V
tour Output Timing Reterence Voltage 0.8 1.5 2.0 V
Programming Waveforms
PROGRAM 'Rt,ilt.,e-
ADDRESSES E
DATA J: (iv, nm em nu: m I r---
_ 12.5v tw
ooh,, tMN /
c‘z ry'"""'-"''
vac s.ov L
0V TL/D/8627-4
Note 1: Netional's standard product warranty applies onty to devices programmed to specifications described herein.
Note 2: Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The EPROM must not be inserted into or removed from a
board with voltage applied to Vpp or Vcc.
Note 3: The maximum absolute allowable voltage which may be applied to the Vpp pin during programming is 14V. Care must be taken when switching the Vpp
supply to prevent any overshoot trom exceeding this 14V maximum specification. At least a 0.1 p.F capacitor is required across Vcc to GND to suppress spurious
voltage transients which may damage the device.
Note & Programming and program verify are tested with the fast Program Algorithm, at typical power supply voltages and timings.
GZSOLZOWN
NMCZ7C3ZB
Fast Programming Algorithm Flow Chart (Note 4)
ADDR = FIRST LOCATION
PROGRAM ONE 100 us PULSE
wnu v,,P = 12.75v
INCREMENT ADDR
DEVICE PASSED
FIGURE 1
DEVICE '
FAILED
DEVICE
FAILED
TL/D/8827- 5
Interactive Programming Algorithm Flow Chart (Note 4)
ADDR = FIRST LOCATION
PROGRAM ONE 0.5 ms PULSE
WITH br, = 12.5V
INCREMENT X
INGREDIENT ADDR
voc=5.ov:5z
DEVICE
FAILED
FAILED
DEVICE PASSED
FIGURE 2
TL/D/6827 - 6
QZSOLZOWN
NMC27C328
Functional Description
DEVICE OPERATION
The six modes of operation of the NMC27C32B are listed in
Table l. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for -trE/vep during
programming. In the program mode the ttEntre, input is
pulsed from a TTL low level to 12.75V.
Read Mode
The NMC27C32B has two control functions, both of which
must be logically active in order to obtain data at the out-
puts. Chip Enable (E) is the power control and should be
used for device selection. Output Enable (CE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (tAcc) is equal to the delay
from Ct? to output (tog). Data is available at the outputs tog
after the falling edge of E, assuming that O_E has been low
and addresses have been stable for at least tAcc-tog.
The sense amps are clocked for fast access time. Vcc
should therefore the maintained at operating voltage during
read and verify. If Vcc temporarily drops below the spec.
voltage (but not to ground) an address transition must be
performed after the drop to ensure proper output data.
Standby Mode
The NMC27C32B has a standby mode which reduces the
active power dissipation by 99%, from 55 mW to 0.55 mW.
The NMG27C32B is placed in the standby mode by applying
a CMOS high signal to the C-E input. When in standby mode,
the outputs are in a high impedance state, independent of
the E input.
Output OR-Tylng
Because EPROMs are usually used in larger memory ar-
rays, National has provided a 2-line control function that
accommodates this use of multiple memory connection.
The 2-Iine control function allows for:
a. The lowest possible memory power dissipation, and
b. complete assurance that output bus contention will not
occur.
common connection to all devices in the array and connect-
ed to the READ line from the system control bus. This as-
sures that all deselected memory devices are in their low
power standby modes and that the output pins are active
only when data is desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 20 O-E/Vpp will damage
the NMC27C32B.
Initially, and after each erasure, all bits of the NMC27C32B
are in the "I" state. Data is introduced by selectively pro-
gramming "Os" into the desired bit locations. Although only
"Os" will be programmed, both "ls" and "Os" can be pre-
sented in the data word. The only way to change a "ty' to a
"1" is by ultraviolet light erasure.
The NMC270326 is in the programming mode when trty
Vpp is at 12.75V. It is required that at least a 0.1 pF capaci-
tor be placed across Vcc and ground to suppress spurious
voltage transients which may damage the device. The data
to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data
inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the E input. A program pulse
must be applied at each address location to be pro-
grammed. The NMC27G32B is programmed with the Fast
Programming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100 us pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
Program with a single 100 ps pulse.
Note: Some programmer manufactures due to equipment limitation may at.
ter interactive program Algorithm (Shown in Figure 2).
The NMC27C32B must not be programmed with a DC signal
applied to the ttE input.
Programming multiple NMC27C32Bs in parallel with the
same data can be easily accomplished due to the simplicity
of the programming requirements. Like inputs of the paral-
leled NMC27G32B may be connected together when they
are programmed with the same data. A low level TTL pulse
. . . . . applied to the E input programs the paralleled
To most effucne_ntly use these two control lines, it is recom- NMC27C32B
mended that CE (pin 18) be decoded and used as the pri- .
mary device selecting function, while a? (pin 20) be made a
TABLE I. Mode Selectlon
Pins Wi tTE/vm, Vcc Outputs
Mode (18) (20) (24) (9-11,13-17)
Read " " 5V DOUT
Standby VIH Don't Care 5V Hi-Z
Program " 12.75V 6.25V DIN
Program Verify " " 6.25V DOUT
Program Inhibit " 12.75V 6.25V Hi-Z
Output Disable Don't Care VIH 5V Hi-Z
Functional Description (Continued)
Program lnhlblt
Programming multiple NMC27C32B in parallel with different
data is also easily accomplished. Except for E all like in-
puts (including E) of the parallel NMC27C32B may be
common. A TTL low level program pulse applied to an
NMC27C32B's tre input with te/Viv, at 12.75v will pro-
gram that NMC27C32B. A TTL high level CE input inhibits
the other NMC27C32B from being programmed.
Program Verify
A verify should be performed on the programmed bit to de..
termine whether they were correctly programmed. The veri-
fy is accomplished with tFE/Viv, and (TE at VI, Data should
be verified tDv after the falling edge of E.
MANUFACTURER’S IDENTIFICATION CODE
The NMC27C32B has a manufacturer’s identification code
to aide in programming. The code, shown in Table ll, is two
bytes wide and is stored in a ROM configuration on the chip.
It identifies the manufacturer and the device type. The code
for the NMC27C32B is, "8F01 ", where "BF" designates that
it is made by National Semiconductor, and "OI" designates
a 32k part.
The code is accessed by applying 12.0V i0.5V to address
pin A9. Addresses AI-M, AIO-AI l, ' and UE are held
at VIL. Address A0 is held at " for the manufacturer's
code, and at ViH for the device code. The code is read out
on the 8 data pins. Proper code access is only guaranteed
at 25°C :t5°C.
The primary purpose of the manufacturer's identification
code is automatic programming control. When the device is
inserted in an EPROM programmer socket, the programmer
reads the code and then automatically calls up the specific
programming algorithm for the part. This automatic pro-
gramming control is only possible with programmers which
have the capability of reading the code.
ERASURE CHARACTERISTICS
The erasure characteristics of the NMC27C32B are such
that erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000A-4000A
range. After programming, opaque labels should be placed
over the NMC27C32B's window to prevent unintentional
erasure. Covering the window will also prevent temporary
functional failure due to the generation of photo currents.
The recommended erasure procedure for the NMC27C32B
is exposure to short wave ultraviolet light which has a wave-
length of 2537A. The integrated dose (i.e., UV intensity X
exposure time) for erasure should be a minimum of
15 W.sec/crn2.
The NMC27C32B should be placed within 1 inch of the
lamp tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. Table III
shows the minimum NMC27C32B erasure time for various
light intensities.
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (It
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occurring. Incomplete erasure will cause symptoms that
can be misleading. Programmers, components, and even
system designs have been erroneously suspected when in-
complete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require
careful decoupling of the devices. The supply current, lcc,
has three segments that are of interest to the system de-
signer-the standby current level, the active current level,
and the transient current peaks that are produced by volt-
age transitions on input pins. The magnitude of these tran-
sient current peaks is dependent on the output capacitance
loading of the device. The associated Vcc transient voltage
peaks can be suppressed by properly selected decoupling
capacitors. It is recommended that at least a 0.1 " ceramic
capacitor be used on every device between Vcc and GND.
This should be a high frequency capacitor of low inherent
inductance. In addition, at least a 4.7 ,uF bulk electrolytic
capacitor should be used between Vcc and GND for each
eight devices. The bulk capacitor should be located near
where the power supply is connected to the array. The pur-
pose of the bulk capacitor is to overcome the voltage drop
caused by the inductive effects of the PC board traces.
TABLE ll. Manufacturer’s Identification Code
HZSOLZOWN
Pins A0 o, ths Os O4 th 02 o, 00 Hex
(8) (17) (16) (15) (14) (13) (11) (10) (9) Data
Manufacturer Code " 1 0 0 0 1 1 1 1 BF
Device Code VIH 0 O 0 0 0 0 0 1 01
TABLE III. Minimum NMC27C32B Erasure Time
Light Intensity
(wW/cm2)
Erasure Time
(Minutes)
15,000
10,000
This datasheet has been :
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
NMC27C32BQE250 - product/nm027c32bqe250?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
