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NM25C040LM8XNSN/a2094avai 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
NM25C040LNFAIN/a25avai 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
NM25C040M8XFAIN/a2477avai 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)


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OAC5A , 5 VDC SOLID-STATE OPTO-ISOLATED I/O MODULES
OAC5A , 5 VDC SOLID-STATE OPTO-ISOLATED I/O MODULES
OAC5Q , AC Modules have High Current Thyristors with 100 Amp
OAC5Q , AC Modules have High Current Thyristors with 100 Amp
OAC5Q , AC Modules have High Current Thyristors with 100 Amp
OAC-5Q , AC Modules have High Current Thyristors with 100 Amp


NM25C040LM8X-NM25C040LN-NM25C040M8X
4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
NM25C040 4K-Bit Serial CMOS EEPROM (Serial Periphrial Interface (SPI) Synchronous Bus) March 1999 NM25C040 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) General Description Features The NM25C040 is a 4096-bit CMOS EEPROM with an SPIn2.1 MHz clock rate @ 2.7V to 5.5V compatible serial interface. The NM25C040 is designed for datan4096 bits organized as 512 x 8 storage in applications requiring both non-volatile memory and in- nMultiple chips on the same 3-wire bus with separate chip system data updates. This EEPROM is well suited for applications select lines using the 68HC11 series of microcontrollers that support the SPI nSelf-timed programming cycle interface for high speed communication with peripheral devices via a serial bus to reduce pin count. The NM25C040 is imple-nSimultaneous programming of 1 to 4 bytes at a time mented in Fairchild Semiconductor’s floating gate CMOS process nStatus register can be polled during programming to monitor that provides superior endurance and data retention. READY/BUSY The serial data transmission of this device requires four signalnWrite Protect (WP) pin and write disable instruction for both lines to control the device operation: Chip Select (CS), Clock hardware and software write protection (SCK), Data In (SI), and Serial Data Out (SO). All programming nBlock write protect feature to protect against accidental cycles are completely self-timed and do not require an erase writes before WRITE. nEndurance: 1,000,000 data changes BLOCK WRITE protection is provided by programming the STA- nData retention greater than 40 years TUS REGISTER with one of four levels of write protection. nPackages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP Additionally, separate WRITE enable and WRITE disable instruc- tions are provided for data protection. Hardware data protection is provided by the WP pin to protect against inadvertent programming. The HOLD pin allows the serial communication to be suspended without resetting the serial sequence. Block Diagram CS V CC Instruction HOLD VSS Decoder SCK Control Logic WP and Clock Instruction SI Generators Register Program Address High Voltage Enable Counter/ Generator Register and Program VPP Timer EEPROM Array Decoder 4096 Bits 1 of 512 (512 x 8) Read/Write Amps Data In/Out Register Data Out SO 8 Bits Buffer Non-Volatile Status Register DS012401-1 1 © 1999 NM25C040 Rev. D.1
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