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NL17SZ06-NL17SZ06DFT2-NL17SZ06XV5T2 Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
NL17SZ06ONN/a3120avaiSingle Inverter Open Drain
NL17SZ06DFT2ONN/a4000avaiSingle Inverter Open Drain
NL17SZ06XV5T2ONN/a4000avaiSingle Inverter Open Drain


NL17SZ06DFT2 ,Single Inverter Open DrainMAXIMUM RATINGSSymbol Characteristics Value UnitV DC Supply Voltage −0.5 to +7.0 VCCV DC Input Volt ..
NL17SZ06DFT2G ,Single Inverter with Open Drain OutputsELECTRICAL CHARACTERISTICS t = t = 2.5 ns; C = 50 pF; R = 500 R F L LÎÎT = 25°C −40°C ≤ T ≤ 85°CA ..
NL17SZ06DFT2G ,Single Inverter with Open Drain OutputsFeatures5• Tiny SOT−353 and SOT−553 Packages5• Extremely High Speed: t 2.5 ns (typical) at V = 5.0 ..
NL17SZ06XV5T2 ,Single Inverter Open DrainFeatures5• Tiny SOT−353 and SOT−553 Packages5• Extremely High Speed: t 2.5 ns (typical) at V = 5.0 ..
NL17SZ07 ,Single Non−Inverting Buffer with Open Drain OutputMaximum ratings applied to the device are individual stress limitvalues (not normal operating condi ..
NL17SZ07DFT2 ,Single Non−Inverting Buffer with Open Drain Outputallows the NL17SZ07 to be used to interface 5.0 V circuits to circuitsof any voltage between 0 and ..
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NL17SZ06-NL17SZ06DFT2-NL17SZ06XV5T2
Single Inverter Open Drain
NL17SZ06
Single Inverter with Open
Drain Outputs
The NL17SZ06 is a high performance single inverter with open
drain outputs operating from a 1.65 to 5.5 V supply.
The Output stage is open drain with Over Voltage Tolerance. This
allows the NL17SZ06 to be used to interface 5.0 V circuits to circuits
of any voltage between 0 and +7.0 V.
Features
Tiny SOT−353 and SOT−553 Packages Extremely High Speed: tPD 2.5 ns (typical) at VCC = 5.0 V Designed for 1.65 V to 5.5 V VCC Operation, CMOS Compatible Over V oltage Tolerant Inputs VIN may be Between 0 and 7.0 V for
VCC Between 0.5 and 5.4 V TTL Compatible − Interface Capability with 5.0 V TTL Logic with
VCC = 2.7 V to 3.6 V LVCMOS Compatible 24 mA Output Sink Capability, Pullup may be between 0 and 7.0 V Near Zero Static Supply Current Substantially Reduces System
Power Requirements Chip Complexity: FET = 20 Pb−Free Packages are Available
VCCNC
IN A
OUT YGND
IN A OUT Y
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
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