NE57814DD ,DDR memory termination regulator with standby mode and enhanced efficiencyPIN CONFIGURATION PIN DESCRIPTIONPIN SYMBOL DESCRIPTION1 V Terminator groundSS2 V SENSE V remote se ..
NE590 ,Addressable peripheral driver
NE591N ,Addressable peripheral drivers
NE592 ,Video AmplifierELECTRICAL CHARACTERISTICS (V = 6.0 V, V = 0, typicals at T = +25°C, min and max at 0°C T 70°C ..
NE594D ,Vacuum fluorescent display driver
NE594D ,Vacuum fluorescent display driver
NL27WZ00 ,Dual 2 Input NAND Gate
NL27WZ00 ,Dual 2 Input NAND GateELECTRICAL CHARACTERISTICS t = t = 3.0 nsR FT = 25C 40C T 85CA AV VCC CCSymbol Parameter Co ..
NL27WZ00USG , Dual 2−Input NAND Gate
NL27WZ00USG , Dual 2−Input NAND Gate
NL27WZ02 ,Dual 2 Input NOR GateELECTRICAL CHARACTERISTICST = 25C 40C T 85CA AV VCC CCSymbol Parameter Condition (V) Min Ty ..
NL27WZ02US ,Dual 2 Input NOR GateMaximum Ratings are those values beyond which damage to the device may occur. Exposure to these con ..
NE57814DD
DDR memory termination regulator with standby mode and enhanced efficiency
Product data
Supersedes data of 2003 Jan 22
2003 Apr 03
Philips Semiconductors Product data
NE57814DDR memory termination regulator with
standby mode and enhanced efficiency
DESCRIPTIONThe NE57814 is designed to provide power for termination of a DDR
memory bus. It significantly reduces parts count, board space, and
overall system cost over previous switching solutions. The NE57814
has an independent power source pin (VD) for further reducing the
operational power and a standby low-power mode for
energy-sensitive portable applications.
The DDR terminator regulator provides a very accurate reference
(RefOut) and termination voltage (VTT) which is one-half of the RAM
supply voltage over wide range of current demand. HSO8 (TOP) HSO8 (BOTTOM)
FEATURES Fast transient response time Over-temperature protection Over-current protection Commercial (0 °C to 70 °C) temperature range High bandwidth drivers minimize requirement for output hold-up
filter capacitors Internal divider maintains termination voltage at 1/2 memory
supply voltage RefOut output pin for other memory and control components
APPLICATIONS Laptop computers Desktop microcomputer systems Workstations Set-top boxes Servers Networking routers and switches Video display systems Personal video recorders Game machines Embedded systems
SIMPLIFIED SYSTEM DIAGRAM
Figure 1. Simplified system diagram.
Philips Semiconductors Product data
NE57814DDR memory termination regulator with
standby mode and enhanced efficiency
ORDERING INFORMATION
PIN CONFIGURATION
Figure 2. Pin configuration.
PIN DESCRIPTION
NOTE: The thermal heatspreader connects electrically to VSS internally
and provides enhancement to thermal conductivity, but it should
not be used as the primary connection to ground. Device
specifications apply to use of the VSS pin as the connection to
ground.
MAXIMUM RATINGS
NOTE: Tested on a minimum footprint on a four-layer PCB per JEDEC specification JESD51-7.
Philips Semiconductors Product data
NE57814DDR memory termination regulator with
standby mode and enhanced efficiency
ELECTRICAL CHARACTERISTICSTamb = 0 °C to +70 °C; VDD = 2.5 V; VD = 2.5 V, unless otherwise specified.
NOTE: Limits are 100% production tested at 25 °C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Ceramic capacitors. Low ESR Electrolytic capacitors are not required for stability, but may be needed for the application. Voltage Accuracy referred to voltage at the center node of the Vref resistor divider. RefOut voltage referenced to 1 /2 VDD. See Figure 15 for the Safe Operating Area versus Temperature.
Philips Semiconductors Product data
NE57814DDR memory termination regulator with
standby mode and enhanced efficiency
TYPICAL PERFORMANCE CURVES
Figure 3. VTT transient response
(output filter 50 μF ceramic)
Figure 4. VDD-to-VTT response
(output filter 50 μF ceramic)
Figure 5. Vref-to-VTT transient response
(output filter 820 μF + 50 μF ceramic)
Figure 6. Vref-to-VTT transient response
(output filter 50 μF ceramic)
Philips Semiconductors Product data
NE57814DDR memory termination regulator with
standby mode and enhanced efficiency
Figure 7. Output regulation.
Philips Semiconductors Product data
NE57814DDR memory termination regulator with
standby mode and enhanced efficiency
TECHNICAL DISCUSSIONThe NE57814 supplies power to the DDR memory bus termination
resistors at one-half the voltage supplied to the memory ICs or
DIMMs. The DDR memory bus can only have one output drive any
one bus line at any one time. So the load on the DDR termination
system is a matter of the number of bus lines being terminated and
the termination resistor values. The memory size (that is the MB) of
memory space is not relevant. A typical DDR memory system is
seen in Figure 8. Each bus input/output pin on the bus has a series
20 Ω resistor connected to it. The bus is terminated to the DDR
terminator though a 27 to 50 Ω resistance. The memory system will
then require current from the terminator output only when the
instantaneous value of the aggregate bus does not correspond to
equal amounts of 1s and 0s. When memory bus speeds are in the
200–300 MHz region, the period of any single bus state is extremely
small. This creates two bus loading conditions: the high frequency
condition which is caused by the instantaneous numbers of 1s and
0s, and the low frequency condition caused by mainly the address
bus being oriented towards the top or bottom of the memory space.
This creates two relatively independent output-filtering situations for
the DDR terminator: the high frequency bus speed, and the
low-frequency address skew of the processor system. Each should
be examined separately.
Figure 9 models the VTT loading condition of each bus line
equivalent circuit during operation and with terminating resistors.
This yields the worst case current loading equation: O(max)�NDDRVDD
2(RT� RS)
Where:
NDDR is the total number of terminated control, address and data
lines within the DDR memory system (typically 192).
RT is the value of the terminating resistors.
RS is the value of the series resistors from the active output
driver.
Hence the worst-case current loading condition for the typical DDR
memory is 194 terminated bus lines, and there are either all 1s or all
0s for an instant. If the terminator resistances are RT = 27 Ω and
RS = 20 Ω, then this results in a momentary instantaneous output
current of either + or – 3.3 Amperes.
Figure 8. Functional diagram.
Figure 9. The model for a single bus line for the DDR system.
Philips Semiconductors Product data
NE57814DDR memory termination regulator with
standby mode and enhanced efficiency
APPLICATION INFORMATIONThe NE57814 is intended for DDR memory termination systems
which require small space, low cost, high output transient current
dynamic range, and higher efficiency than the traditional linear DDR
terminator. The increased efficiency is gained by being able to draw
its output current from a lower voltage than the DDR RAM VDD
voltage. As much as a 40 percent in the overall efficiency can be
gained by operating the output stage from a voltage source of
0.25 V above the output VTT voltage. This gives it a distinct benefit
in portable applications.
The standby mode turns OFF the VTT amplifier and 3-states the VTT
output. The RefOut pin is still active for use elsewhere within the
system.
Using the STANDBY signalThe NE57814 provides a STANDBY pin that can be used to put the
device into low-power mode. When STANDBY is asserted (LOW),
the VTT power amplifier is turned off and the VTT output is 3-stated.
This brings the quiescent current of the entire device to less than
800 μA. The internal reference divider (ExtRefIn pin) and the
reference amplifier will remain active, allowing those circuits
requiring a reference during the STANDBY state to remain active.
If STANDBY is not externally connected, an internal 10 kΩ resistor
biases the control logic to VDD causing the output sections to be
turned on and the NE57814 operates normally.
Output filteringThere are two components to the memory signal load: a high
frequency component caused by the 266 MHz plus speed of the
address, data, and control buses, and a low frequency component
caused by the time-average skew of all of the bus states away from
an equal number of 1s and 0s. All electrolytic and tantalum
capacitors appear inductive at the high frequencies. Therefore two
types of capacitors are needed for the output filtering.
For a 256 MB memory space, for example, approximately 100 μF of
ceramic surface mount ceramic capacitors should be evenly
distributed across the physical memory layout. Depending upon the
PCB noise environment, this could be 10 pieces of 10 μF, 20 pieces
of 5 μF, and so on. These are the high frequency filter, represented
by Cout (HF) in the illustrations. One half of the high frequency filter
capacitors should be connected to VDD and the other half to VSS so
that the output will better track any variations in the VDD voltage.
Filtering the lower frequencies of the DDR load usually requires
larger, low-ESR capacitors such as tantalum or low-ESR electrolytic
capacitors, shown as Cout (LF) in the illustrations.
This is where the NE57814 excels. Because of its fast input and
output transient responses, very small or no additional large
capacitors are needed. Worst-case system analysis has shown that
an additional 110 μF of capacitance is needed for each microsecond
lag in the response time of the DDR regulator. The NE57814
responds in within one microsecond, so this requirement can be
filled by the 100 μF of ceramic capacitors already on the output.
Additional studies have shown that other regulators, which cannot
directly source the maximum instantaneous current demanded from
the termination system, must have an additional 75 μF of
capacitance for each ampere of insufficient output drive.
Together, the fast output response and peak drive current
capabilities make the NE57814 the ideal choice for DDR
termination.
