MPC949FA ,Low voltage 1:15 PECL to CMOS clock driverLogic Diagram Figure 2. 52–Lead Pinout (Top View)TCLK_SelTCLK0 (LVTTL)0÷101TCLK1 (LVTTL)÷21 39 38 3 ..
MPC949FA ,Low voltage 1:15 PECL to CMOS clock driverfeatures a low voltage PECL input, inaddition to its LVCMOS/LVTTL inputs, to allow it to be incorpo ..
MPC949FA ,Low voltage 1:15 PECL to CMOS clock driverfeatures selectabilityto allow the user to select the ratio of 1X outputs to 1/2X outputs.Two indep ..
MPC950 ,LOW VOLTAGE PLL CLOCK DRIVER**SEMICONDUCTOR TECHNICAL DATA * ** The MPC950/951 are 3.3V compatible, PLL based clock driver d ..
MPC950 ,LOW VOLTAGE PLL CLOCK DRIVERLOGIC DIAGRAMfselaPLL_EnTclkRef_SelPHASE VCO Qaxtal1÷2/÷4xtal200–480MHzDETECTOROSCxtal2LPFQb÷4/÷8÷8 ..
MPC950 ,LOW VOLTAGE PLL CLOCK DRIVERLOGIC DIAGRAMfselaPLL_EnTclkRef_Sel(Pull Up)PHASE VCO Qa÷2/÷4PECL_CLK200–550MHzDETECTORPECL_CLKLPFQ ..
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MSP430F1232IRHBT ,16-bit Ultra-Low-Power Microcontroller, 8kB Flash, 256B RAM, 10 bit ADC, 1 USARTblock diagram, MSP430x11x2XIN XOUT V V RST/NMI P1/JTAG P2CCSS8 6ROSCOscillatorACLK 8KB Flash 256B R ..
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MSP430F123IPWR ,16-Bit Ultra-Low-Power Microcontroller, 8kB Flash, 256B RAM, USART, ComparatorMSP430x12xMIXED SIGNAL MICROCONTROLLERSLAS312C − JULY 2001 − REVISED SEPTEMBER 2004 Low Supply Vol ..
MPC949FA
Low voltage 1:15 PECL to CMOS clock driver
SEMICONDUCTOR TECHNICAL DATA - -
The MPC949 is a low voltage CMOS, 15 output clock buffer. The 15
outputs can be configured into a standard fanout buffer or into 1X and
1/2X combinations. The device features a low voltage PECL input, in
addition to its LVCMOS/LVTTL inputs, to allow it to be incorporated into
larger clock trees which utilize low skew PECL devices (see the
MC100LVE111 data sheet) in the lower branches of the tree. The fifteen
outputs were designed and optimized to drive 50Ω series or parallel
terminated transmission lines. With output to output skews of 300ps the
MPC949 is an ideal clock distribution chip for synchronous systems
which need a tight level of skew from a large number of outputs. For a
similar product with a smaller fanout and package consult the MPC946
data sheet. Clock Distribution for Pentium Systems with PCI Low Voltage PECL Clock Input 2 Selectable LVCMOS/LVTTL Clock Inputs 350ps Maximum Output to Output Skew Drives up to 30 Independent Clock Lines Maximum Output Frequency of 150MHz High Impedance Output Enable 52–Lead TQFP Packaging 3.3V VCC Supply
With an output impedance of approximately 7Ω, in both the HIGH and
the LOW logic states, the output buffers of the MPC949 are ideal for
driving series terminated transmission lines. More specifically each of the
15 MPC949 outputs can drive two series terminated transmission lines.
With this capability, the MPC949 has an effective fanout of 1:30 in
applications using point–to–point distribution schemes.
The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are
generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability
to allow the user to select the ratio of 1X outputs to 1/2X outputs.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the
TCLK1 input is selected. The PCLK_Sel input will select the PECL input clock when driven HIGH.
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the
Dsel pins will select the 1X output. The MR/OE input will reset the internal flip flops and tristate the outputs when it is forced HIGH.
The MPC949 is fully 3.3V compatible. The 52 lead TQFP package was chosen to optimize performance, board space and cost
of the device. The 52–lead TQFP has a 10x10mm body size with a 0.65mm pin spacing.
Pentium is a trademark of Intel Corporation.
