MM74HCT573 ,Octal D-Type LatchFeaturesgoes LOW, data at the D inputs will be retained at the out- TTL input characteristic compat ..
MM74HCT573MTC ,Octal D-Type LatchMM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-FlopFebruary 1990Revised May ..
MM74HCT573MTCX ,Octal D-Type LatchFeaturesgoes LOW, data at the D inputs will be retained at the out- TTL input characteristic compat ..
MM74HCT573N ,Octal D-Type LatchGeneral Descriptionlevel is applied to the Output Control (OC) input, all outputsThe MM74HCT573 oct ..
MM74HCT573SJX ,Octal D-Type LatchFeaturesgoes LOW, data at the D inputs will be retained at the out- TTL input characteristic compat ..
MM74HCT573WM ,Octal D-Type LatchMM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-FlopFebruary 1990Revised May ..
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MNA-4 ,Circuits - Monolithic Amplifiers High Directivity, 50Ω, 0.5 to 5.9 GHz
MNA-4 ,Circuits - Monolithic Amplifiers High Directivity, 50Ω, 0.5 to 5.9 GHz
MNA-6 ,Circuits - Monolithic Amplifiers High Directivity, 50Ω, 0.5 to 5.9 GHz
MM74HCT573
Octal D-Type Latch
MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop February 1990 Revised May 1999 MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop going transitions of the Clock (CK) input. When a high logic General Description level is applied to the Output Control (OC) input, all outputs The MM74HCT573 octal D-type latches and go to a high impedance state, regardless of what signals MM74HCT574 octal D-type flip-flop advanced silicon-gate are present at the other inputs and the state of the storage CMOS technology, which provides the inherent benefits of elements. low power consumption and wide power supply range, but The MM74HCT devices are intended to interface between are LS-TTL input and output characteristic and pin-out TTL and NMOS components and standard CMOS devices. compatible. The 3-STATE outputs are capable of driving 15 These parts are also plug in replacements for LS-TTL LS-TTL loads. All inputs are protected from damage due to devices and can be used to reduce power consumption in static discharge by internal diodes to V and ground. CC existing designs. When the MM74HCT573 Latch Enable input is HIGH, the Q outputs will follow the D inputs. When the Latch Enable Features goes LOW, data at the D inputs will be retained at the out- � TTL input characteristic compatible puts until Latch Enable returns HIGH again. When a high logic level is applied to the Output Control input, all outputs � Typical propagation delay: 18 ns go to a high impedance state, regardless of what signals � Low input current: 1 μA maximum are present at the other inputs and the state of the storage � Low quiescent current: 80 μA maximum elements. � Compatible with bus-oriented systems The MM74HCT574 are positive edge triggered flip-flops. � Output drive capability: 15 LS-TTL loads Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive Ordering Codes: Order Number Package Number Package Description MM74HCT573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HCT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide MM74HCT574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HCT574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 1999 DS010627.prf
