MM24256-BMW6T Fast Delivery |IC PHOENIX CO.,LIMITED

MM24256-BMW6T ,256/128 Kbit Serial IC Bus EEPROM Without Chip Enable LinesLogic DiagramThese memory devices are compatible with the2I C extended memory standard. This is a t ..
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MM24256-BMW6T
256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines
1/19
PRELIMINARY DATA
February 2000
M24256-B
M24128-B
256/128 Kbit Serial I C Bus EEPROM
With Three Chip Enable Lines Compatible withI2C Extended Addressing Two WireI2C Serial Interface
Supports 400 kHz Protocol Single Supply Voltage: 4.5Vto 5.5Vfor M24xxx-B 2.5Vto 5.5Vfor M24xxx-BW 1.8Vto 3.6Vfor M24xxx-BR Hardware Write Control BYTE and PAGE WRITE(upto64 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior 100000 Erase/Write Cycles (minimum) 40 Year Data Retention (minimum)
DESCRIPTION
TheseI2 C-compatible electrically erasable pro-
grammable memory (EEPROM) devicesare orga-
nizedas 32Kx8 bits (M24256-B) and 16Kx8 bits
(M24128-B).
These memory devices are compatible withthe2C extended memory standard. Thisisa two wire
serial interface that usesa bi-directional data bus
and serial clock. The memory carriesa built-in4-
bit unique Device Type Identifier code (1010)in
accordance withtheI2C bus definition.
Figure1. Logic Diagram
AI02809
SDA
VCC
M24256-B
M24128-B
SCL
VSS
E0-E2Table1. Signal Names
E0,E1,E2 Chip Enable Inputs
SDA Serial Data/Address Input/
Output
SCL Serial Clock Write Control
VCC Supply Voltage
VSS Ground
PSDIP8 (BN)
0.25mm frame
SO8 (MN)
150mil width
TSSOP8 (DW)
169mil width
TSSOP14 (DL)
169mil width
M24256-B, M24128-B
2/19
The memory behavesasa slave deviceintheI2C
protocol, withall memory operations synchronizedthe serial clock. Read and Write operationsare
initiatedbya START condition, generatedbythe
bus master. The START conditionis followedbya
Device Select Code and RWbit(as describedin
Table3), terminatedbyan acknowledgebit.
When writing datatothe memory,the memoryin-
sertsan acknowledgebit duringthe9thbit time,
following the bus master’s 8-bit transmission.
When datais readby the bus master, the bus
master acknowledgesthe receiptofthe data bytethe same way. Data transfersare terminatedby STOP condition afteran Ackfor WRITE, andaf-
tera NoAckfor READ.
PowerOn Reset: VCC Lock-Out Write Protect orderto prevent data corruption and inadvertent
write operations during powerup,a PowerOn Re-
Figure2A. PSDIP8 Connections
Figure2B. SO8 and TSSOP8 Connections
SDAVSS
SCLE1 VCC
AI02810
M24256-B
M24128-B
AI02811 SDAVSS
SCLE1 VCC
M24256-B
M24128-B
Figure2C. TSSOP14 Connections
Note:1.NC=Not Connected
AI02812 SDAVSS SCL
M24256-B
M24128-B NC
VCC
Table2. Absolute Maximum Ratings1
Note:1. Exceptforthe rating “Operating Temperature Range”, stresses above those listedinthe Table “Absolute Maximum Ratings”may
cause permanent damage tothe device. These arestress ratingsonly,and operationof thedeviceat theseorany other conditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposure toAbsolute Maximum Rating condi-
tionsfor extended periodsmay affect device reliability. ReferalsototheST SURE Programand other relevant quality documents. MIL-STD-883C, 3015.7(100pF,1500Ω)
Symbol Parameter Value Unit Ambient Operating Temperature -40to125 °C
TSTG Storage Temperature -65to150 °C
TLEAD Lead Temperature during Soldering
PSDIP8:10 seconds
SO8:40 seconds
TSSOP8:40 seconds
TSSOP14:40 seconds
VIO Inputor Output range -0.6to6.5 V
VCC Supply Voltage -0.3to6.5 V
VESD Electrostatic Discharge Voltage (Human Body model)2 4000 V
3/19
M24256-B, M24128-B
set (POR) circuitis included. The internal resetis
held active untilthe VCC voltage has reachedthe
POR threshold value, andall operations are dis-
abled–the devicewillnot respondto any com-
mand.Inthe same way, when VCC drops fromthe
operating voltage, belowthe POR threshold value,
all operationsare disabled andthe devicewillnot
respondto any command.A stable and valid VCC
mustbe applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL inputpinis usedto strobeall datain and
outofthe memory.In applications where thisline usedby slavesto synchronizethebustoa slow- clock,the master must havean open drain out-
put, anda pull-up resistor mustbe connected from
the SCL lineto VCC. (Figure3 indicates howthe
valueofthe pull-up resistorcanbe calculated).In
most applications, though,this methodof synchro-
nizationisnot employed, andsothe pull-up resis-
torisnot necessary, provided thatthe masterhas push-pull (rather than open drain) output.
Serial Data (SDA)
The SDApinis bi-directional, andis usedto trans-
fer datainoroutofthe memory.Itisan open drain
output that maybe wire-OR’ed with other open
drainor open collector signalsonthe bus.Apull resistor mustbe connected fromthe SDA bus VCC. (Figure3 indicates how the valueofthe
pull-up resistor canbe calculated).
Chip Enable (E2,E1,E0)
These chip enable inputsare usedtosetthe value
thatistobe lookedforonthe three least significant
bits (b3, b2,b1)ofthe 7-bit device select code.
These inputs mustbe tied directlyto VCCor VSSto
establish the device select code. When uncon-
nected, the E2,E1 andE0 inputs are internally
readasVIL (see Table7 and Table8)
Write Control (WC)
The hardware Write Controlpin (WC)is usefulfor
protectingthe entire contentsofthe memory from
inadvertent erase/write. The Write Control signalis
usedto enable (WC=VIL)or disable (WC=VIH)
write instructionstothe entire memory area. When
unconnected,the WC inputis internally readas
VIL, and write operationsare allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytesarenot acknowl-
edged.
Please seethe Application Note AN404fora more
detailed descriptionofthe Write Control feature.
DEVICE OPERATION
The memory device supports theI2C protocol.
Thisis summarizedin Figure4, andis compared
with other serial bus protocolsin Application Note
AN1001. Any device that sends dataontothe bus definedtobea transmitter, and any device that
readsthe datatobea receiver. The device that
controlsthe data transferis knownasthe master,
andthe otherasthe slave.A data transfercan only initiatedbythe master, whichwill also provide
the serial clockfor synchronization. The memory
deviceis alwaysa slave deviceinall communica-
tion.
Start Condition
STARTis identifiedbya highto low transitionof
the SDA line whilethe clock, SCL,is stableinthe
high state.A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except duringa programming
Figure3. MaximumRL Value versus Bus Capacitance (CBUS)foranI2C Bus
AI01665
VCC
CBUS
SDA
MASTER
SCL CBUS
100BUS(pF)
Maximum
value 1000= 400kHz =100kHz
M24256-B, M24128-B
4/19
cycle)the SDA and SCL linesfora START condi-
tion, andwillnot respond unless oneis given.
Stop Condition
STOPis identifiedbyalowto high transitionofthe
SDA line whilethe clock SCLis stableinthe high
state.A STOP condition terminates communica-
tion betweenthe memory deviceandthe bus mas-
ter.A STOP conditionat the endofa Read
command, after (and only after)a NoAck, forces
the memory device intoits standby state.A STOP
conditionatthe endofa Write command triggers
the internal EEPROM write cycle.
AcknowledgeBit (ACK) acknowledge signalis usedto indicatea suc-
cessful byte transfer. Thebus transmitter, whetherbe masteror slave, releasesthe SDA bus after
sending eight bitsof data. During the9th clock
pulse period,the receiver pullsthe SDAbuslowto
acknowledgethe receiptofthe eight data bits.
Data Input
During data input,the memory device samplesthe
SDA bus signalon the rising edgeof the clock,
SCL.For correct device operation,the SDA signal
mustbe stable duringthe clock low-to-high transi-
tion, andthe data must change only whenthe SCL
lineis low.
Memory Addressing start communication betweenthe bus master
andthe slave memory,the master must initiatea
START condition. Following this,the master sends
the 8-bit byte, shownin Table3,onthe SDA bus
line (most significantbit first). This consistsofthe
7-bit Device Select Code, andthe 1-bit Read/Write
Designator (RW). The Device Select Codeisfur-
ther subdivided into:a 4-bit Device Type Identifier,
anda 3-bit Chip Enable “Address” (E2,E1, E0). address the memory array,the 4-bit Device
Type Identifieris 1010b.
Figure4.I2C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
AI00792
STOP
CONDITION 3 7 89
MSB ACK
START
CONDITION
SCL 123 78 9
MSB ACK
STOP
CONDITION
5/19
M24256-B, M24128-Bto eight memory devicescanbe connectedon singleI2C bus. Each oneis givena unique 3-bit
codeonits Chip Enable inputs. Whenthe Device
Select Codeis receivedonthe SDAbus,the mem-
ory only respondsifthe Chip Select Codeisthe
sameas the pattern appliedtoits Chip Enable
pins.
The8thbitisthe RWbit. Thisissetto‘1’for read
and‘0’for write operations.Ifa match occurson
the Device Select Code,the corresponding mem-
ory givesan acknowledgmentonthe SDA bus dur-
ingthe9thbit time.Ifthe memory doesnot match
the Device Select Code, itdeselects itself fromthe
bus, and goes into stand-by mode.
There are two modes bothfor read and write.
Theseare summarizedin Table6 and described
later.A communication betweenthe master and
the slaveis ended witha STOP condition.
Each data byteinthe memory hasa 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble4)is sent first, followedbythe Least significant
Byte (Table5). Bits b15tob0 formthe addressof
the bytein memory.Bit b15is treatedasa Don’t
Carebitonthe M24256-B memory. Bits b15 and
b14are treatedas Don’t Carebitsonthe M24128- memory.
Write Operations
Followinga START conditionthe master sendsa
Device Select Code withthe RWbitsetto’0’,as
shown inTable6. The memory acknowledges this,
and waitsfor two address bytes. The memoryre-
spondsto each address byte withan acknowledge
bit, and then waitsforthe data byte.
Writingtothe memory maybe inhibitedifthe WC
inputpinis taken high. Any write command with
WC=1 (duringa periodof time fromthe START
condition untilthe endofthe two address bytes)
willnot modifythe memory contents, andtheac-
companying data byteswillnotbe acknowledged, shownin Figure5.
Byte Writethe Byte Write mode, after the Device Select
Code andthe address bytes,the master sends
one data byte.Ifthe addressed locationis write
protectedbythe WCpin,the memory replies with NoAck, andthe locationisnot modified.If,in-
stead,the WCpinhas been heldat0,as shownin
Figure6, the memory replies withan Ack. The
master terminates the transferby generatinga
STOP condition.
Page Write
The Page Write mode allowsupto64 bytestobe
writtenina single write cycle, provided that they
areall locatedinthe same ’row’in the memory:
Table3. Device Select Code1
Note:1.The most significantbit,b7,issentfirst.
Device Type Identifier Chip Enable RW b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 E2 E1 E0 RW
Table4. Most Significant Byte
Note:1.b15is treatedas Don’t Careonthe M24256-B series.
b15 andb14are Don’t Care onthe M24128-B series.
Table5. Least Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8 b6 b5 b4 b3 b2 b1 b0
Table6. Operating Modes
Note:1.X=VIHorVIL.
Mode RWbit WC1 Data Bytes Initial Sequence
Current Address Read 1 X 1 START, Device Select,RW=‘1’
Random Address Read
START, Device Select,RW=‘0’, Address X reSTART, Device Select,RW=‘1’
Sequential Read 1 X ≥1 Similarto Currentor Random Address Read
Byte Write 0 VIL 1 START, Device Select,RW=‘0’
Page Write 0 VIL ≤ 64 START, Device Select,RW=‘0’
M24256-B, M24128-B
6/19
Figure5. Write Mode Sequences with WC=1 (data write inhibited)
STOP
START
BYTE WRITE DEVSEL BYTE ADDR BYTE ADDR DATAIN
START
PAGE WRITE DEVSEL BYTE ADDR BYTE ADDR DATAIN1
DATAIN2
AI01120B
PAGE WRITE
(cont’d) (cont’d)
STOP
DATAINN
ACK ACK ACK NOACK
R/W
ACK ACK ACK NOACK
R/WACK NOACK
thatisthe most significant memory address bits
(b14-b6for the M24256-B and b13-b6for the
M24128-B)arethe same.If more bytesare sent
thanwillfituptothe endofthe row,a condition
knownas ‘roll-over’ occurs. Data startsto become
overwritten(ina waynot formally specifiedinthis
data sheet).
The master sends from oneupto64 bytesof data,
eachof whichis acknowledgedbythe memoryif
the WCpinis low.Ifthe WCpinis high,the con-
tentsofthe addressed memory location arenot
modified, and each data byteis followedbya
NoAck. After each byteis transferred,the internal
byte address counter (the6 least significant bits
only)is incremented. The transferis terminatedby
the master generatinga STOP condition.
Whenthe master generatesa STOP conditionim-
mediately afterthe Ackbit(inthe “10th bit” time
slot), eitheratthe endofa byte writeora page
write,the internal memory write cycleis triggered. STOP conditionat any other time doesnot trig-
gerthe internal write cycle.
Duringthe internal write cycle,the SDA inputis
disabled internally, andthe device does notre-
spondtoany requests.
7/19
M24256-B, M24128-B
Figure6. Write Mode Sequences with WC=0 (data write enabled)
STOP
START
BYTE WRITE DEVSEL BYTE ADDR BYTE ADDR DATAIN
START
PAGE WRITE DEVSEL BYTE ADDR BYTE ADDR DATAIN1
DATAIN2
AI01106B
PAGE WRITE
(cont’d) (cont’d)
STOP
DATAINN
ACK
R/W
ACK ACK ACK
ACK ACK ACK ACK
R/W
ACKACK
Minimizing System Delaysby PollingOn ACK
Duringthe internal write cycle,the memory discon-
nects itself fromthe bus, and copiesthe data from
its internal latchestothe memory cells. The maxi-
mum write time (tw)is shownin Table9,butthe
typical timeis shorter.To makeuseof this,an Ack
polling sequence canbe usedbythe master.
The sequence,as shownin Figure7,is: Initial condition:a Writeisin progress. Step1:the master issuesa START condition
followedbya Device Select Code (thefirst bytethe new instruction). Step2:ifthe memoryis busy withthe internal
write cycle,noAckwillbe returned andthe mas-
ter goes backto Step1.Ifthe memory haster-
minatedthe internal write cycle,it responds with Ack, indicating thatthe memoryis readyto
receivethe second partofthe next instruction
(thefirst byteofthis instruction having been sent
during Step1).
Read Operations
Read operationsare performed independentlyof
the stateofthe WC pin.
Random Address Read dummy writeis performedto loadthe address
intothe address counter,as shownin Figure8.
Then, without sendinga STOP condition,the mas-
ter sends another START condition, and repeats
the Device Select Code, withthe RWbitsetto‘1’.
The memory acknowledges this, and outputsthe
contentsofthe addressed byte. The master must
not acknowledgethe byte output, and terminates
the transfer witha STOP condition.
Current Address Read
The device hasan internal address counter which incremented each timea byteis read. Forthe
Current Address Read mode, followinga START
condition,the master sendsa Device Select Code
withthe RWbitsetto‘1’. The memory acknowl-
edges this, and outputsthe byte addressedbythe
M24256-B, M24128-B
8/19
Acknowledgein Read Modeall read modes,the memory waits, after each
byte read,foran acknowledgment duringthe9th
bit time.Ifthe master doesnot pullthe SDA line
low during this time,the memory terminatesthe
data transfer and switchestoits stand-by state.
internal address counter. The counteris thenin-
cremented. The master terminates the transfer
witha STOP condition,as shownin Figure8, with-
out acknowledgingthe byte output.
Sequential Read
This mode canbe initiated with eithera Current
Address Readora Random Address Read. The
master does acknowledgethe data byte outputin
this case, andthe memory continuesto outputthe
next bytein sequence.To terminatethe streamof
bytes,the master mustnot acknowledgethelast
byte output, and must generatea STOP condition.
The output data comes from consecutive address-
es, withthe internal address counter automatically
incremented after each byte output. Afterthelast
memory address,the address counter ‘rolls-over’
and the memory continuesto output data from
memory address 00h.
Figure7. Write Cycle Polling Flowchart using ACK
WRITE Cycle Progress
AI01847
Next
Operationis
Addressingthe
Memory
START Condition
DEVICE SELECT
withRW=0
ACK
Returned
YES
YESNO
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
Send
Byte Address
Firstbyteof instruction
withRW=0 already
decodedby M24xxx
9/19
M24256-B, M24128-B
Figure8. Read Mode Sequences
Note:1.The seven most significantbitsofthe Device Select Codeof aRandom Read(inthe1stand4th bytes)must beidentical.
START
DEVSEL* BYTE ADDR BYTE ADDR
START
DEVSEL DATAOUT1
AI01105C
DATAOUTN
STOP
START
CURRENT
ADDRESS
READ
DEVSEL DATAOUT
RANDOM
ADDRESS
READ
STOP
START
DEVSEL* DATAOUT
SEQUENTIAL
CURRENT
READ
STOP
DATAOUTN
START
DEVSEL* BYTE ADDR BYTE ADDR
SEQUENTIAL
RANDOM
READ
START
DEVSEL* DATAOUT1
STOP
ACK
R/WACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NOACK
R/WACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NOACK
M24256-B, M24128-B
10/19
Table7.DC Characteristics
(TA= –40to85°C; VCC=4.5to5.5Vor2.5to5.5V)
(TA= –20to85°C; VCC=1.8to3.6V)
Note:1.Thisis preliminarydata.
Table8. Input Parameters1(TA =25°C,f= 400 kHz)
Note:1. Sampledonly,not 100% tested.
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current
(SCL, SDA) 0V ≤ VIN≤VCC ±2 μA
ILO Output Leakage Current 0V≤ VOUT≤ VCC,SDAin Hi-Z ±2 μA
ICC Supply Current
VCC=5V, fc=400kHz (rise/falltime< 30ns) 2mA series: VCC=2.5V, fc=400kHz (rise/fall time< 30ns) 1mA series: VCC=1.8V, fc=100kHz (rise/fall time< 30ns) 0.51 mA
ICC1 Supply Current
(Stand-by)
VIN=VSS orVCC ,VCC=5V 10 μA series: VIN =VSSorVCC ,VCC=2.5V 2 μA series: VIN =VSSorVCC ,VCC=1.8V 11 μA
VIL InputLow Voltage (SCL, SDA) –0.3 0.3VCC V
VIH Input High Voltage(SCL, SDA) 0.7VCC VCC+1 V
VIL InputLow Voltage
(E0-E2, WC) –0.3 0.5 V
VIH Input High Voltage
(E0-E2, WC) 0.7VCC VCC+1 V
VOL Output Low
Voltage
IOL=3mA,VCC=5V 0.4 V series: IOL=2.1mA,VCC=2.5V 0.4 V series: IOL=0.7mA,VCC=1.8V 0.21 V
Symbol Parameter Test Condition Min. Max. Unit
CIN Input Capacitance (SDA) 8 pF
CIN Input Capacitance (other pins) 6 pF Input Impedance (E0-E2, WC) VIN≤0.5V 50 kΩ Input Impedance (E0-E2, WC) VIN≥ 0.7VCC 500 kΩ
tNS Pulse width ignored
(Input Filteron SCLand SDA) Single glitch 100 ns

Partno	Mfg	Dc	Qty	Available	Descript
MM24256-BMW6T \|MM24256BMW6T	STM	N/a	160	avai	256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines