MM24164WMN6T Fast Delivery |IC PHOENIX CO.,LIMITED

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MM24164WMN6T
16 Kbit Serial I2C BUS EEPROM
M24164
16 Kbit Serial I2 C BUS EEPROM
PRELIMINARY DATA
January 1999 1/16
Figure 1. Logic Diagram
TWO WIRE I2 C SERIAL INTERFACE
SUPPORTS 400kHz PROTOCOL
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
2ms TYPICAL PROGRAMMING TIME
SINGLE SUPPLY VOLTAGE: 4.5V to 5.5V for M24164 2.5V to 5.5V for M24164-W 1.8V to 5.5V for M24164-R
HARDWARE WRITE CONTROL
BYTE and PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH-UP
PERFORMANCES
DESCRIPTION
The M24164 is a 16 Kbit EEPROM. The memory
is an electrically erasable programmable memory
(EEPROM) fabricated with STMicroelectronics’s
High Endurance Single Polysilicon CMOS technol-
ogy which guarantees an endurance typically well
above one million erase/write cycles with a data
retention of 40 years. The "-W" version operate with
a power supply value as low as 2.5V and the "-R"
version operate down to 1.8V.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
Table 1. Signal Names
Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents. Depends on range. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). EIAJ IC-121 (Condition C) (200pF, 0 Ω).
Table 2. Absolute Maximum Ratings (1)
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
The memory is compatible with the two wire serial
interface which uses a bi-directional data bus and
serial clock. The memory offers 3 chip enable
inputs (E2, E1, E0) so that up to 8 x 16K devices
may be attached to the bus and selected individu-
ally. The memory behaves as a slave device with
all memory operations synchronized by the serial
clock.
Read and write operations are initiated by a START
condition generated by the bus master. The START
condition is followed by a stream of 7 bits, plus one
read/write bit and terminated by an acknowledge
bit (see Table 3). When writing data to the memory
it responds to the 8 bits received by asserting an
acknowledge bit during the 9th bit time. When data
is read by the bus master, it acknowledges the
receipt of the data bytes in the same way. Data
transfers are terminated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent any possible data corruption and
inadvertent write operations during power up, a
Power On Reset (POR) circuit is implemented.
Until the VCC voltage has reached the POR thresh-
old value, the internal reset is active, all operations
are disabled and the device will not respond to any
command. In the same way, when VCC drops down
from the operating voltage to below the POR
threshold value, all operations are disabled and the
device will not respond to any command. A stable
VCC must be applied before applying any logic
signal.
DESCRIPTION (cont’d)
2/16
M24164
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Chip Enable (E2 - E0). These chip enable inputs
are used to set 3 bits (b6, b5, b4) of the 7 bit device
select code. These inputs may be driven dynami-
cally or tied to VCC or VSS to establish the device
select code.
Write Control (WC). A hardware Write Control pin
(WC) is provided on pin 7 of the memory. This
feature is useful to protect the entire contents of the
memory from any erroneous erase/write cycle. The
Write Control signal is used to enable (WC=VIL) or
disable (WC=VIH) write instructions to the entire
memory area. When unconnected, the WC input is
internally read as VIL and write operations are
allowed. When WC=1, Device Select and Address
bytes are acknowledged, Data bytes are not ac-
knowledged.
Refer to Application Note AN404 for more detailed
information about Write Control feature.
Note: The MSB b7 is sent first.
Table 3. Device Select Code
Note:1. X = VIH or VIL.
Table 4. Operating Modes (1)
DEVICE OPERATION 2 C Bus Background
The memory supports the I2 C protocol. This proto-
col defines any device that sends data onto the bus
as a transmitter and any device that reads the data
as a receiver. The device that controls the data
transfer is known as the master and the other as
the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The memory is always a slave device
in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the memory continu-
ously monitors the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the memory and the
bus master. A STOP condition at the end of a Read
sequence, after and only after a No-Acknowledge,
forces the standby state. A STOP condition at the
end of a Write command triggers the internal
EEPROM write cycle.
3/16
M24164
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2 C Bus
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the memory samples
the SDA bus signal on the rising edge of the clock
SCL. Note that for correct device operation, the
SDA signal must be stable during the clock low to
high transition and the data must change ONLY
when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave memory, the
master must initiate a START condition. Following
this, the master sends onto the SDA bus line 8 bits
(MSB first) corresponding to the Device Select
code (7 bits) and a READ or WRITE bit.
Three out of the four most significant bits of the
Device Select code are the Device Select bits (b6,
b5, b4). They are matched to the chip enable
signals applied on pins E2, E1, E0. Thus up to 8 x
16K memories can be connected on the same bus
giving a memory capacity total of 128 Kbits.
After a START condition any memory on the bus
will identify the device code and compare the 3 bits
to its chip enable inputs E2, E1, E0. The 8th bit sent
is the read or write bit (RW).
This bit is set to ’1’ for read and ’0’ for write
operations. If a match is found, the corresponding
memory will acknowledge the identification on the
SDA bus during the 9th bit time. If the memory does
not match the Device Select code, it will self-dese-
lect from the bus and go into standby mode.
Write Operations
Following a START condition the master sends a
Device Select code with the RW bit set to ’0’. The
memory acknowledges it and waits for a byte ad-
dress, which provides access to the memory area.
After receipt of the byte address, the memory again
responds with an acknowledge and waits for the
data byte. Writing in the Memory may be inhibited
if input pin WC is taken high.
Any write command with WC=1 (during a period of
time from the START condition until the Acknow-
ledge of the last Data byte) will not modify the
memory content and will NOT be acknowledged on
data bytes, as shown in Figure 9.
Byte Write. In the Byte Write mode, after the
Device Select code and the address, the master
sends one data byte. If the addressed location is
write protected by the WC pin, the memory send a
NoACK and the location is not modified. If the WC
pin is tied to 0, after the data byte the memory
sends an ACK. The master terminates the transfer
by generating a STOP condition.
4/16
M24164
Table 6. DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Note: 1. Sampled only, not 100% tested.
Table 5. Input Parameters (1) (TA = 25°C, f = 400 kHz )
5/16
M24164
Notes:1. Sampled only, not 100% tested. For a reSTART condition, or following a write cycle. The minimum value delays the falling/rising edge of SDA away form SCL = 1 in order to avoid unwanted START and/or STOP
condition.
Table 7. AC Characteristics
Table 8. AC Measurement Conditions
Figure 4. AC Testing Input Output Waveforms
6/16
M24164
Figure 5. AC Waveforms
Page Write. The Page Write mode allows up to 16
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the most significant memory ad-
dress bits are the same. The master sends from
one up to 16 bytes of data, each of which is
acknowledged by the memory if the WC pin is low.
If the WC pin is high, each data byte is followed by
a NoACK and the location will not be modified. After
each byte is transferred, the internal byte address
counter (4 least significant bits only) is incre-
mented. The transfer is terminated by the master
generating a STOP condition. Care must be taken
to avoid address counter ’roll-over’ which could
result in data being overwritten. Note that, for any
byte or page write mode, the generation by the
master of the STOP condition starts the internal
memory program cycle. All inputs are disabled until
the completion of this cycle and the memory will not
respond to any request.
7/16
M24164
Figure 6. I2 C Bus Protocol
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master. The sequence is: Initial condition: a Write is in progress (see Figure
7). Step 1: the master issues a START condition
followed by a Device Select byte (1st byte of the
new instruction). Step 2: if the memory is busy with the internal
write cycle, NoACK will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it will respond
with an ACK, indicating that the memory is ready
to receive the second part of the incoming in-
struction (the first byte of this instruction was
already sent during Step 1).
8/16
M24164

Partno	Mfg	Dc	Qty	Available	Descript
MM24164WMN6T	ST	N/a	234	avai	16 Kbit Serial I2C BUS EEPROM