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MCM67Q909ZP12MOTON/a1469avai512K x 9 Bit Separate I/O Synchronous Fast Static RAM
MCM67Q909ZP12MOT N/a6avai512K x 9 Bit Separate I/O Synchronous Fast Static RAM


MCM67Q909ZP12 ,512K x 9 Bit Separate I/O Synchronous Fast Static RAMBLOCK DIAGRAMMEMORYREG DECODERSA0 – A18 ARRAYSH512K x 9 ARRAYBSRSHBSRSENSE AMPSMUXOUTPUTD0 – D8 REG ..
MCM67Q909ZP12 ,512K x 9 Bit Separate I/O Synchronous Fast Static RAMfeatures transparent–write and data pass–throughcapabilities.The synchronous design allows for prec ..
MCM6810CP ,1 MHz; V(cc/in): -0.3 to +7.0V; 450ns; 128 x 8-bit randon-access memoryMOTOROLA" fEf/l1fc'fultf?h""oR Ii-ill-ill-li-lil-------MCM6810128 x 8-Bit Random-Access MemoryThe M ..
MCM6810P ,1 MHz; V(cc/in): -0.3 to +7.0V; 450ns; 128 x 8-bit randon-access memoryTHERMAL CHARACTERISTICSCharacteristic Symbol Value Unit 1Thermal Resistance BJA 'C WPlastic 120Cerd ..
MCM6926AWJ12R ,128K x 8 bit fast static random access memoryBLOCK DIAGRAMV9 VSS24 DDA DQ DQ1023VDDADQ DQ1122VSSW AA1221AA A13 20MEMORYROWMATRIXAA A 1419DECODER ..
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MCM67Q909ZP12
512K x 9 Bit Separate I/O Synchronous Fast Static RAM
Advance Information
512K x 9 Bit Separate I/O
Synchronous Fast Static RAM

The MCM67Q909 is a 4M–bit static random access memory, organized as
512K words of 9 bits. It features separate TTL input and output buffers, which
drive 3.3 V output levels, and incorporates input and output registers on–board
with high speed SRAM. It also features transparent–write and data pass–through
capabilities.
The synchronous design allows for precise cycle control with the use of an
external single clock (K). The addresses (A0 – A18), data input (D0 – D8), data
output (Q0 – Q8), write–enable (W), chip–enable (E), and output–enable (G), are
registered on the rising edge of clock (K).
The control pins (E, W, G) function differently in comparison to most synchro-
nous SRAMs. This device will not deselect with E high. The RAM remains active
at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G
is registered low. The transparent write feature allows the output data to track the
input data. E, G, and W must be asserted to perform a transparent write (write
and pass–through). The input data is available at the ouputs on the next rising
edge of clock (K).
The pass–through function is always enabled. E high disables the write to the
array while allowing a pass–through cycle to occur on the next rising edge of
clock (K). Only a registered G high will three–state the outputs.
The MCM67Q909 is available in an 86–bump surface mount PBGA (Plastic
Ball Grid Array) package. Single 5 V ± 5% Power Supply Fast Cycle Time: 12 ns Max Single Clock Operation TTL Input and Output Levels (Outputs LVTTL Compatible) Address, Data Input, E, W, and G Registers On–Chip 83 MHz Maximum Clock Cycle Time Self–Timed Write Separate Data Input and Output Pins Transparent–Write and Pass–Through High Output Drive Capability: 50 pF/Output at Rated Access Time Boundary Scan Implementation PBGA Package for High Speed Operation
This document contains information on a new product. Specifications and information herein are subject to change without notice.87654
Not to Scale21
TOP VIEW
86–BUMP

VSSVSSA17A15D7
A16 VSSKGA14
VSS Q8VSS VSS
VCC
VSS
SDOSDIVCCWE A4 A0 D8A6 D6D4D2A1
VSS Q7
VCC Q5D3
VSS D1
A12Q1 A5A8A9VSSA10
A18 VSS VSS VSS VSS
VSS VSS VSS VSSVSS
VSS VSS VSS VSSVSS
VSS VSS VSS VSSVSSVSS VSS
VSS VSS VSS VSSVSS
VSS
PIN ASSIGNMENT
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