MCM67M618BFN9 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAMBLOCK DIAGRAM (See Note)BURST LOGICINTERNALADDRESSBAAA1′Q1K16BINARY64K x 18COUNTERMEMORYARRAYA0′Q0L ..
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MCM67M618BFN9
64K x 18 Bit BurstRAM Synchronous Fast Static RAM
Advance Information
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed WriteThe MCM67M618B is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the MC68040 and PowerPC microprocessors. It is organized as 65,536
words of 18 bits, fabricated using Motorola’s high–performance silicon–gate
BiCMOS technology. The device integrates input registers, a 2–bit counter, high
speed SRAM, and high drive capability outputs onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control sig-
nals, except output enable (G), are clock (K) controlled through posi-
tive–edge–triggered noninverting registers.
Bursts can be initiated with either transfer start processor (TSP) or
transfer start cache controller (TSC) input pins. Subsequent burst
addresses are generated internally by the MCM67M618B (burst
sequence imitates that of the MC68040) and controlled by the burst
address advance (BAA) input pin. The following pages provide more
detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising
edge of the clock (K) input. This feature eliminates complex off–chip
write pulse generation and provides increased flexibility for incoming
signals.
Dual write enables (LW and UW) are provided to allow individually
writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW
controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory. Single 5 V ± 5% Power Supply Fast Access Times: 9/10/12 ns Max Byte Writeable via Dual Write Strobes Internal Input Registers (Address, Data, Control) Internally Self–Timed Write Cycle TSP, TSC, and BAA Burst Control Pins Asynchronous Output Enable Controlled Three–State Outputs Common Data Inputs and Data Outputs High Board Density 52–PLCC Package 3.3 V I/O Compatible
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MCM67M618B/D-
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENTDQ9
VCC
DQ8
DQ6
DQ7
VSS
DQ4
DQ5
DQ2
DQ3
VSS
VCC
DQ0
DQ1
VCC
VSS
VSS
VCC
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17A7EUW K A8A9A10LW G
A15A3A2
A13A14 A12A1 A0
BAATSCTSP
All power supply and ground pins must be con-
nected for proper operation of the device.
