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Partno Mfg Dc Qty AvailableDescript
MCM56824AFN20MOTN/a26avai8K x 24 Bit Fast Static RAM
MCM56824AFN35MOTN/a500avai8K x 24 Bit Fast Static RAM


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MIC10937P-40 , V. F. Alphanumeric Display Controller
MIC10937P-50 , V. F. Alphanumeric Display Controller
MIC10937P-50 , V. F. Alphanumeric Display Controller
MIC10939P-50 , V. F. Alphanumeric and Bargraph Display Controller Summary Information-Not Recommended for New Designs
MIC10939P-50 , V. F. Alphanumeric and Bargraph Display Controller Summary Information-Not Recommended for New Designs
MIC1232 , μP Supervisory Circuit


MCM56824AFN20-MCM56824AFN35
8K x 24 Bit Fast Static RAM
DSPRAM
8K x 24 Bit Fast Static RAM

The MCM56824A is a 196,608 bit static random access memory organized as
8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple
chip enable inputs, output enable, and an externally controlled single address pin
multiplexer. These functions allow for direct connection to the Motorola
DSP56001 Digital Signal Processor and provide a very efficient means for imple-
mentation of a reduced parts count system requiring no additional interface logic.
The availability of multiple chip enable (E1 and E2) and output enable (G) in-
puts provides for greater system flexibility when multiple devices are used. With
either chip enable input unasserted, the device will enter standby mode, useful
in low–power applications. A single on–chip multiplexer selects A12 or X/Y as the
highest order address input depending upon the state of the V/S control input.
This feature allows one physical static RAM component to efficiently store pro-
gram and vector or scalar operands by dynamically re–partitioning the RAM
array. Typical applications will logically map vector operands into upper memory
with scalar operands being stored in lower memory. By connecting
DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control
pin, such partitioning can occur with no additional components. This al-
lows efficient utilization of the RAM resource irrespective of operand
type. See application diagrams at the end of this document for addition-
al information.
Multiple power and ground pins have been utilized to minimize effects
induced by output noise.
The MCM56824A is available in a 52 pin plastic leaded chip–carrier
(PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA. Single 5 V ± 10% Power Supply Fast Access and Cycle Times: 20/25/35 ns Max Fully Static Read and Write Operations Equal Address and Chip Enable Access Times Single Bit On–Chip Address Multiplexer Active High and Active Low Chip Enable Inputs Output Enable Controlled Three State Outputs High Board Density PLCC Package Low Power Standby Mode Fully TTL Compatible
For proper operation of the device, all VSS
pins must be connected to ground.
PIN ASSIGNMENTS

DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ23
DQ22
DQ21
VSS
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
VSS
DQ14
DQ13
DQ1A8A7A6
DQ12E1E2
A10A1
A12 A5A4A3A2A1A0X/YV/S
PLCC

D21
VSS
VSS
VCC
X/Y
A11
D23
V/S
A12
A10
D22
D20D17D16
D15D14
D13
D12
VSSD11
VSS A5
D18
D19 7 6 5 410 1
VIEW OF PBGA PACKAGE BOTTOM
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SEMICONDUCTOR TECHNICAL DATA
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