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MC88LV926DW
LOW SKEW CMOS PLL 68060 CLOCK DRIVER
SEMICONDUCTOR TECHNICAL DATA --
The MC88LV926 Clock Driver utilizes phase–locked loop technology
to lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins
provide a processor reset function designed specifically for the
MC68/EC/LC030/040/060 microprocessor family. To support the 68060
processor, the 88LV926 operates from a 3.3V as well as a 5.0V supply.
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
locations on a board. The PLL also allows the MC88LV926 to multiply a
low frequency input clock and distribute it locally at a higher (2X) system
frequency. 2X_Q Output Meets All Requirements of the 50 and 66MHz 68060
Microprocessor PCLK Input Specifications Low Voltage 3.3V VCC Three Outputs (Q0–Q2) With Output–Output Skew <500ps CLKEN Output for Half Speed Bus Applications The Phase Variation From Part–to–Part Between SYNC and the ‘Q’
Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew) SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4 All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level Compatible Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice
the ‘Q’ output frequency. The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the
tight duty cycle spec of the 50 and 66MHz 68060. The QCLKEN output is designed to drive the CLKEN input of the 68060 when
the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure
that CLKEN setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X
multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided)
the input/output frequency relationships are fixed. The Q3 output provides an inverted clock output to allow flexibility in the clock
tree design.
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88LV926 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.
The RST_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT
pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a
pull–up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the
RST_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.
Description of the RST_IN/RST_OUT(LOCK) FunctionalityThe RST_IN and RST_OUT(LOCK) pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also
acting as a lock indicator. If the RST_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until
steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the
RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the
