MC88914D ,LOW SKEW CMOS CLOCK DRIVER WITH RESET
MC88914D ,LOW SKEW CMOS CLOCK DRIVER WITH RESET
MC88914N ,LOW SKEW CMOS CLOCK DRIVER WITH RESET
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MC88914D-MC88914N
LOW SKEW CMOS CLOCK DRIVER WITH RESET
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SEMICONDUCTOR TECHNICAL DATA - -
The MC88914 is a high–speed, low power, hex divide–by–two D–type
flip–flop with matched propagation delays, an internal power–on–reset,
and external synchronous reset. With TTL compatible buffered clock and
external reset inputs that are common to all flip–flops, the MC88914 is
ideal for use in high–frequency systems as a clock driver, providing
multiple outputs that are synchronous. Power–on–Reset and External Synchronous Reset TTL Compatible Positive Edge–Triggered Clock Matched Outputs for Synchronous Applications Outputs Source/Sink 24mA Part–to–Part Skew of Less Than 3.0ns Guaranteed Rise and Fall Times for a Given Capacitive Load
VCC
VCC
GND
GND
CLK
GND
GND
Pinout: 14–Lead Plastic (Top View)
LOGIC DIAGRAMCLK
NOTE: This diagram is provided only for understanding of logic operation and should not be used to estimate propagation delays
