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MC74VHC1G09-MC74VHC1G09DFT2-MC74VHC1G09DTT1 Fast Delivery,Good Price
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MC74VHC1G09ONN/a3120avaiSingle 2 Input AND Gate, Open Drain
MC74VHC1G09MOTON/a455avaiSingle 2 Input AND Gate, Open Drain
MC74VHC1G09DFT2ONSEMIN/a51000avai2-Input AND Gate with Open Drain Output
MC74VHC1G09DTT1ONN/a200000avai2-Input AND Gate with Open Drain Output


MC74VHC1G09DTT1 ,2-Input AND Gate with Open Drain OutputELECTRICAL CHARACTERISTICST = 25°C T ≤ 85°C −55 ≤ T ≤ 125°CA A AV VCC CC(V) Min Typ Max Min Max Min ..
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MC74VHC1G125DFT1 ,Single Non Inverting Buffer, 3-State3MC74VHC1G125SWITCHING WAVEFORMSVCCOE50%V GNDCC50%t tPZL PLZAGND HIGHtt PHL IMPEDANCEPLH50% VY CCV ..
MC74VHC1G125DFT1 ,Single Non Inverting Buffer, 3-StateFeatures• These are Pb−Free DevicesPin 1d = Date Code• High Speed: t = 3.5 ns (Typ) at V = 5.0 VPD ..
MC74VHC1G125DFT1G ,Noninverting 3-State BufferELECTRICAL CHARACTERISTICS C = 50 pF, Input t = t = 3.0 nsload r fÎÎÎÎÎT = 25°C T ≤ 85°C −55 ≤ T ≤ ..
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MC74VHC1G09-MC74VHC1G09DFT2-MC74VHC1G09DTT1
Single 2 Input AND Gate, Open Drain
MC74VHC1G09
2-Input AND Gate with
Open Drain Output
The MC74VHC1G09 is an advanced high speed CMOS 2−input AND
gate with open drain output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including an open
drain output which provides the capability to set output switching level.
This allows the MC74VHC1G09 to be used to interface 5.0 V circuits to
circuits of any voltage between VCC and 7.0 V using an external resistor
and power supply.
The MC74VHC1G09 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. High Speed: tPD = 4.3 ns (Typ) at VCC = 5.0 V Low Internal Power Dissipation: ICC = 1 �A (Max) at TA = 25°C Power Down Protection Provided on Inputs Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 62; Equivalent Gates = 16
VCCIN B
IN A
OUT YGND
IN A
IN B OUT Y
Figure 1. Pinout (T
op View)
Figure 2. Logic Symbol
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