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MC74HC74
Dual D Flip-Flop with Set and Reset
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High–Performance Silicon–Gate CMOSThe MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two D flip–flops with individual Set, Reset,
and Clock inputs. Information at a D–input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip–flop. The Set
and Reset inputs are asynchronous. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2.0 to 6.0 V Low Input Current: 1.0 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 128 FETs or 32 Equivalent Gates
LOGIC DIAGRAMRESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE*Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
