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MC74HC4514MOTON/a7avai1-of-16 Decoder/Demultiplexer with Address Latch
MC74HC4514NMOTON/a126avai1-of-16 Decoder/Demultiplexer with Address Latch


MC74HC4514N ,1-of-16 Decoder/Demultiplexer with Address LatchMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
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MC74HC4514-MC74HC4514N
1-of-16 Decoder/Demultiplexer with Address Latch
SEMICONDUCTOR TECHNICAL DATA " -
High–Performance Silicon–Gate CMOS

The MC74HC4514 is identical in pinout to the MC14514B metal–gate
CMOS device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors; they are compatible with LSTTL outputs.
This device consists of a 4–bit storage latch with a Latch Enable and Chip
Select input. When a low signal is applied to the Latch Enable input, the
Address is stored, and decoded. When the Chip Select input is high, all
sixteen outputs are forced to a low level.
The Chip Select input is provided to facilitate the chip–select, demultiplex-
ing, and cascading functions.
The demultiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using the Chip Select as a
data input. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 268 FETs or 67 Equivalent Gates
LOGIC DIAGRAM

BINARY
ADDRESS
INPUTSLATCH
ENABLE
CHIP
SELECT
PIN 24 = VCC
PIN 12 = GND
Y10
Y11
Y12
Y13
Y14
Y15
ACTIVE–HIGH
OUTPUTS
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