MC74HC4020AFL1 ,14-Stage Binary Ripple Counter3MC74HC4020ATIMING REQUIREMENTS (Input t = t = 6 ns)r fGuaranteed LimitV VCC CCSymbol Parameter V – ..
MC74HC4020AFL1 ,14-Stage Binary Ripple CounterMaximum Ratings are those values beyond which damage to the device may occurÎ .Functional operation ..
MC74HC4020AN ,14-Stage Binary Ripple CounterMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC4024D ,7-Stage Binary Ripple CounterMaximum Ratings are those values beyond which damage to the device may occur.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC4024N ,7-Stage Binary Ripple CounterMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC4040A ,Monolithic WFR, Binary CounterMaximum Ratings are those values beyond which damage to the device may occur.Functional operation s ..
MD2001FX ,High voltage NPN power transistor for standard definition CRT displayElectrical characteristicsSymbol Parameter Test conditions Min. Typ. Max. UnitV = 1500VCollector cu ..
MD2103DFH , High voltage NPN power transistor for standard definition CRT display
MD2200-D24 , Disk OnChip 2000 DIP
MD2200-D24 , Disk OnChip 2000 DIP
MD2202 , Disk OnChip 2000 DIP
MD2219A ,Dual TransistorsMAXIMUM RATINGSMD2218,A,M92219” M02218AFAF_ - M02218.A MD2218AFRating Symbol M02219,A MD2219AF Unit ..
MC74HC4020ADT-MC74HC4020AFL1
14-Stage Binary Ripple Counter
--
High–Performance Silicon–Gate CMOSThe MC74C4020A is identical in pinout to the standard CMOS
MC14020B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 master–slave flip–flops with 12 stages
brought out to pins. The output of each flip–flop feeds the next and the
frequency at each output is half of that of the preceding one. Reset is
asynchronous and active–high.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
HC4020A for some designs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 398 FETs or 99.5 Equivalent Gates
LOGIC DIAGRAMQ10
Q11
Q12
Q13
Q14
Clock 10
Reset
Pin 8 = GND
VCC
Q11 Q10 Q8 Q9 Reset Clock Q1
Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND
