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MC74HC273ADONN/a36avaiOctal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS


MC74HC273AD ,Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOSELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)L r fGuaranteed LimitÎÎV – 55 toÎ CCÎÎÎ ..
MC74HC273ADTR2 ,Octal D-Type Flip-FlopLOGIC DIAGRAM20 273ADT SUFFIXALYW1CASE 948E23Q0D0154Q1D1A = Assembly Location7 6D2 Q2WL = Wafer Lot ..
MC74HC273ADTR2G , Octal D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS
MC74HC273ADW ,Octal D Flip-Flop with Common Clock and ResetELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)L r fGuaranteed LimitÎÎV – 55 toÎ CCÎÎÎ ..
MC74HC273ADWR2 ,Octal D-Type Flip-Flopresistors, they are compatible with LSTTL outputs.This device consists of eight D flip–flops with c ..
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MC74HC273AD
Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS
------High–Performance Silicon–Gate CMOS
The MC74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of eight D flip–flops with common Clock and
Reset inputs. Each flip–flop is loaded with a low–to–high transition of
the Clock input. Reset is asynchronous and active low. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating V oltage Range: 2.0 to 6.0 V Low Input Current: 1.0 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 264 FETs or 66 Equivalent Gates
LOGIC DIAGRAM

DATA
INPUTSCLOCK18RESET
PIN 20 = VCC
PIN 10 = GND
NONINVERTING
OUTPUTS
FUNCTION TABLE

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ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
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MARKING
DIAGRAMS
= Assembly Location = Wafer Lot = Year = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
PDIP–20
N SUFFIX
CASE 738

TSSOP–20
DT SUFFIX
CASE 948E

ORDERING INFORMATION

PIN ASSIGNMENT

RESET
GND
VCC
CLOCK
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